DE1280925B - Binary stage with a galvanically coupled trigger circuit - Google Patents

Description

Binary stage with a galvanically coupled multivibrator The invention relates to a binary stage consisting of a galvanically coupled flip-flop, having a memory output, and an A to antivalent output Ä and is controlled by clock signals T and their intivalente signals T. Such a binary stage, which effects a frequency reduction in the ratio of 2: 1 , is used with particular advantage for the construction of so-called static binary counters, which, compared to the counters whose binary stages are made up of dynamically coupled flip-flops, on the one hand have a significantly higher counting reliability and on the other hand in the do not depend essentially on the form of the counting pulses.

Known static counters require two static memories per binary level, i. H. increased effort compared to dynamic counters. In addition, problems arise when counting pulses occur in an irregular sequence.

The invention is based on the object of avoiding these disadvantages and still apply the known advantages of static technology to counting circuits.

Starting from a binary stage, consisting of a galvanically coupled bistable multivibrator, which has a memory output A and an output 7f that is complementary thereto and is controlled by clock signals T and their complementary signals 7 ' , this is achieved according to the invention in that a delay element (6) with an upstream AND element (11, 12, 13), the input signals of which are 7 and A , the output variable (C) of which represents the original switching state by means of a further AND link (control AND element 8, 9, 1 -0) is conjunctively linked with the signals, whereby the output signal of this AND link switches the level.

The binary stage according to the invention has the advantage that any pulse sequence can be reduced to 2: 1 with just one static flip-flop circuit without an intermittent auxiliary clock.

On the basis of the exemplary embodiments shown in the drawing the invention described in more detail. To understand the binary level according to the invention to facilitate, should first be on the principle of the 2: 1 reduction with bistable Flip-flops, hereinafter referred to as storage elements, received.

While a 2: 1 reduction according to F i 2. 1 a can be effected with dynamic binary levels with one storage element, this is the case with a static storage element according to F i g. 1 not easily possible. As can be seen from FIG. la results, the memory is to be set by the clock T if it was previously deleted, d. H. 7f = L. On the other hand, it must not be set by the clock T, but must be deleted when it is set. d. H. A = L. The following applies: 1. Set if 51 = L AND T = L. 2. Delete if A = L AND T = L.

Your own memory status is therefore decisive for the switchover of memory. As one can easily see, these conditions cannot be met will.

If T # L, then A # L and thus 7f = 0, so that when T occurs, the setting condition is no longer fulfilled; the same applies to the deletion, because with T = L A = 0 immediately and the deletion condition is no longer present.

In order to avoid these difficulties, an auxiliary signal is generated in the known static binary stages with the aid of an additional storage element during the state T = O and A = O, ie when TUND 7f = L. This can e.g. B. according to FIG. 1 b happen that, while 51 = L, d. H. A = 0 , sets the second memory by means of an intermittent auxiliary clock TH and holds this auxiliary signal beyond T for some time. The setting of the actual counting memory is then made dependent on T AND H, where H represents the state #I = L, since the state #I is kept delayed by the time T, so to speak.

It is the same when clearing the memory. Here the state A = L is represented by the state H = 0 , which lasts longer than A = L and thus creates a secure deletion.

In summary, the known methods therefore amount to holding the original memory state by means of a second toggle switch until the actual counting memory has switched.

The binary stage according to the invention manages without this second trigger circuit. With it, the necessary short-term maintenance of the state takes place ; T = L and A = L for the time T ( FIG. 1 a) with very simple means, in particular passive members can be used.

The F i g. 2 shows a basic circuit diagram of the binary stage according to the invention. It only contains a static memory, which in this example has logically linked holding conditions. The memory is constructed in a known manner from the AND gates 1 to 3, the OR-NOT element 4 and the inversion stage 5 . Furthermore, the delay element 6 is provided with an upstream logic. This delay element is used to delay the return of the memory output to the input, so that clear conditions for switching the memory are given. For the following considerations, the delay element 6 should be thought of as implemented by a capacitor according to an essential feature of the invention. This capacitor is not to be equated with the capacitor in dynamic multivibrators. In the case of the invention, it is rigidly connected to one pole of the supply voltage on one side, while the other side is galvanically connected to logic gates. This results in the following mode of operation: In the initial state of the binary stage CÄ = L and A = 0) , the capacitor is charged with the condition T AND #f = L, i.e. initially whenever, as in FIG. 2 a shown, there is no counting cycle T and the memory is cleared (A = 0). However, the capacitor is also charged when T = L AND A = L, i.e. H. during the counting pulse duration for setting. The reasons for this will be explained later.

The delayed output signal C first reaches the AND element 1, which links this delayed signal representing the state 51 with the clock signal T conjunctively. The AND condition is satisfied & 1, d. i.e., the memory is set (A = L) when T = L AND C = L. It is therefore essential that the state 51 = L is maintained via the capacitor with C = L for so long that the memory is set unambiguously. The memory for & 1 is held for the duration of T. It must now, as shown in FIG. 2a, continue to be held until the second bar T arrives. In the case of an ideal flank change between T and T, the AND element 3 would be sufficient for this, since the AND condition & l is fulfilled when A = L and T # L.

In order to ensure the storage capacity over a possible gap in the signals T = L and TN = L, the conjunction &, with C = L AND A = L, is used as a so-called redundancy condition of the memory .

For the duration of the counting cycle T it runs alongside the storage condition. However, since, as already explained, the capacitor is also charged by the condition T = L and A = L, i.e. during the pulse duration, the state C = L remains for a certain time after T = 0 has already become. During this time, however, T has definitely become L, so that the memory is then held over & i. It should also be mentioned that a brief discharge of the capacitor still occurs during the switching time of the memory.

After the counting cycle has subsided, the charge reversal of the capacitor begins, which is necessary to avoid that the memory by the second counting pulse clock is set again instead of deleted.

This discharge can take place once via a logic circuit that responds when * T = L and A # L (interval between storage and erase cycles) or T = L and A = 0 (pulse duration of the second cycle).

On the other hand, it is advantageous to save the unloading logic the charging logic or conjunction for the storage condition is dimensioned so that the capacitor is automatically held when it is not to be charged. This type of discharge lies in the exemplary embodiments to be explained in detail underlying. It should also be mentioned that during the reloading when switching the memory a short-term charging takes place through the second cycle.

The memory and thus the binary level are deleted by the second Counting cycle.

If T = 0 is &, no longer fulfilled, so are & 1 and &, not because C = L. This interrupts the self-heating, and A becomes equal to 0 or 51 = L. The first cycle is ended, and because of #T = L and T = L, the capacitor starts to recharge after the second counting cycle, which is the case with the third Counting cycle leads to the setting of the binary level. In summary, for the circuit according to the invention according to FIG. 2 the following relationships: Charging with T = L AND 7f = L OR T # L AND A = L. Discharging with T # L AND A = L OR T = L AND; 1 = L. Set: C = L AND T = L . Hold: C = L and A = L or A L and t = L, A # (T & C) \ 1 (A & C) V (A & T), C = (T 21) V (A & T).

Since the capacitor is charged at a time when static conditions prevail, it does not affect the speed of the switching processes. This depends on the switching speed of the transistors. A maximum pulse frequency is given by the fact that the capacitor has to be reloaded between two cycles. On the other hand, the capacity must be so large that the necessary conjunction & 1 = T & C is maintained long enough over the switching time of the static memory.

In the following it will first be explained how the circuit according to FIG. 2 is implemented in detail. First of all, FIG. 3 explained, which reveals the essence of the invention in detail regardless of the memory type. Based on the memory type according to FIG. 2 shows the FIG. 3 shows the structure with respect to the OR-NOT element 4, the capacitor 6 with the charging logic and the AND element 1.

The transistor 7 is the active part of the OR gate 4. The passive input part (diode gate) is not shown because the FIG . 3 shows only one controlling AND element, namely element 1 . This AND element is implemented by the diodes 9, 10 and the resistor 8 . One input signal is the clock T, the other the voltage of the capacitor 6. This capacitor is charged via an AND gate formed by the diodes 11, 12 and the resistor 13 , regardless of T AND Ä. The second charging condition, namely T = L AND A = L, is in FIG. 3 not shown. An essential feature of the circuit according to FIG. 3 it can be seen that the AND operation & is carried out directly at the base of the transistor, which is important for a favorable dimensioning.

The F i g. 4 shows the circuit according to FIG. 2 in great detail. In addition to the transistor 7 , the transistor 5 is shown, which is the reverse stage according to F 1 g. 2 forms and delivers the equivalent output A.

The AND operation & 1 is, as already in connection with FIG. 3 , formed by the diodes 9, 10 and the resistor 8 . The AND gate 2, which simulates the redundancy hold condition & 2, is formed by the diodes 9, 14 and the resistor 15 . Finally, the AND element 3 is implemented by the diodes 16, 17 and the resistor 18 .

The passive input network of the OR element 4 consists of the diodes 19 to 21, 30. It is noteworthy that the diodes 20 and 21 are brought forward, since the variable C occurs in both associated AND operations (&"&,).

The charging logic includes, on the one hand, the AND element formed from the diodes 11, 12 and the resistor 13, and on the other hand the AND element formed from the diodes 22, 23 and the resistor 24. Both AND links act on the capacitor 6 via OR diodes 25, 26 .

While the F i g. FIG. 4 shows a memory with logically linked hold conditions, in which the logical links indicate exactly how long the memory should be cleared or set, FIG. 5 represents a memory with self-holding (RS - Speieliei-), that is to say a so-called flip-flop (Kippscbaltung), in which it is only necessary to specify at which point in time it is to be set or deleted. This flip-flop contains the transistors 5 and 7 as a switching element. The control of the transistor 7, the setting. is analogous to the circuit according to FIG. 3. The transistor 5 is controlled (deletion) in a very corresponding manner; the corresponding switching elements are each marked with a »'«. A capacitor is provided for each of the two controls. However, the capacitor 6 'is not charged by λ, but by the signal A = L, so that the second pulse T, together with the capacitor charge CL which is preparing by A = L, clears the memory.

The following relationships apply: Charge capacitor with T = L AND Ä L, set memory with A = Cs AND T, clear memory with Ä = CL AND T, where capacitor 6 is charged with A = L AND TL.

The mode of action results from what has been said so far or from the pulse pattern according to FIG. 5a.

The F i g. 6 shows a circuit with an RS flip-flop according to FIG. 5 (corresponding components are identified in the same way) with the difference that only one capacitor 6 is required. This capacitor is once, as in FIG. 5 shown in the left part, charged by T AND Ä. In addition, however, it is still loaded by the condition T AND A , i. that is, the charge corresponds to that according to FIG. 4, the OR diodes 25, 26 also being provided.

When setting and clearing, the clock T is not linked directly to the voltage C , but only after the interposition of a transistor 27. The set input (transistor 7) is connected to the emitter and the clear input (transistor 5) to the collector of this transistor.

The mode of operation is as follows (cf. also Fig. 6 a): If one of the charging conditions is met, i. That is , if C = L, then transistor 27 is overdriven. If, on the other hand, the charging conditions are not met, d. i.e. , if C = 0, it is blocked. The RS flip-flop is set via the AND gate, consisting of diodes 9, 10 and resistor 8 (A = L) when T = L AND C = L.

When the transistor is blocked, i. H. C = 0, on the other hand, the flip-flop is cleared via the diode 10 ' by T # L.

The F i g. 7 shows a circuit with an RS flip-flop in which, in contrast to FIG. 5 the delay is not caused by a capacitor, but by the charge storage effect in an overdriven transistor. The transistors 28, 29, to whose collectors the clock T is fed, are used for this purpose. These transistors are relatively slow compared to the transistors 5, 7. The transistor 28, which is used for setting, is, as already explained several times, via an AND element (11, 12, 13) depending on the condition T AND Ä, i.e. H. a = L overdriven.

If the AND condition does not apply, i. H. if T = L occurs, the point a briefly holds its potential due to the charge storage effect, so that during this time a certain part of the pulse T passes the transistor 28. There is therefore a pulse at point e, which sets the flip-flop, i. H. A = L ( Fig. 7 a).

A corresponding process takes place on the delete side. The transistor 29 is overdriven as long as the condition T = L AND A = L, i.e. H. b = L is fulfilled. Because of the charge storage effect, after T = 0 , b is briefly equal to L, so that the pulse T can pass through the diode 10 ' and the transistor 29 for this time. A pulse therefore arises at d which clears the flip-flop.

In FIG. 8 , a particularly advantageous embodiment is shown, which is based on the embodiment according to FIG. 5 , but has the advantage over this that it is independent of the alternation between T and T, and is also well suited for setting up decimal counters. Compared to FIG. 5 shows the RS flip-flop according to FIG. 8 no resistors, but diodes in the return. The main difference compared to the circuit according to FIG. 5 can be seen, however, in the fact that in the circuit according to FIG. 8 only one signal, namely the clock T, is fed into the circuit from the outside. As already explained several times in the previous circuits, the capacitor 6 is charged via the diode 31 via the AND element 11, 12, 13 depending on the condition C = T AND 51. The capacitor voltage is linked conjunctively with the clock T in its negated form by means of the transistor 32. The transistor 32 controls the transistor 5 in such a way that it blocks it (A = L) when C = L AND T = 0, i. H. T = L.

The switching of the RS flip-flop (here by blocking instead of conducting a transistor) is therefore also dependent on the AND link C = L AND T = L, with the signal T only being available indirectly.

The embodiment according to FIG. 9 is based on the design according to FIG. 7 , in which relatively slow transistors 28, 29 are used to control the flip-flop transistors 5, 7 . The execution according to the advantage, F i g. 9 has that like the drive pulses F i g. 9a refer to the flip is' Flop (row e, d) a defined width, namely, the width of the clock pulses T have. These clock pulses are analogous to FIG. 7 fed to the collector of the transistors 28, 29. However, the clock T is no longer supplied from the outside, but is generated in the circuit by negating T by means of the transistors 28, 29 . For this purpose, the collector of transistor 29 is connected to point a and the collector of transistor 28 is connected to point b . However, via these feedbacks, the clock T also reaches the base of the transistors 28, 29 and thereby keeps the transistor that has just been opened open for the clock pulse duration.

As already mentioned at the beginning, several binary levels can become one static counters are interconnected, the interconnection according to the desired coding is done.

Claims (2)

Claims: 1st binary stage, consisting of a galvanically coupled bistable multivibrator, which has a memory output (A) and an output (Ä) complementary thereto and is controlled by clock signals (7) and their complementary signals (T), characterized in that a Delay element (6) with an upstream AND element (11, 12, 13), whose input signals (T and 2) are provided, whose output variable (C) reproducing the original switching state by means of a further AND operation (control AND Element 8, 9, 10) is conjunctively linked to the signals (T), the output signal of this AND link switching the stage. 2. Binary stage according to claim 1, characterized in that the delay element, OR-linked, a second AND element (22, 23, 24) is connected upstream, the input signals of which are the variables (T and A) (F i g. 4, 6). 3. Binary stage according to claim 1 or 2, characterized in that a capacitor is provided as a delay element (F i g- 3). 4. Binary stage according to claim 1 or 3 with a flip-flop which has an internal self-holding (RS memory), characterized in that delay elements are provided with the logic elements according to claim 1 at both the set and the clear input, wherein the AND- Element, which is connected upstream of the capacitor on the quenching side, is controlled by the signals (A and T) (Fig. 5, 8). 5. Binary stage according to claim 2 or 3 with a flip-flop which has an internal self-holding (RS memory), characterized in that a transistor (27) is connected between the delay element and the control AND element, the emitter of which is connected to linking signal derived from (C) or from the collector of which the control signal for the extinguishing side is taken, the clock (T) being fed into the collector circuit via a diode (FIG . 6). 6. Binary stage according to claim 1 or one of the following, characterized in that an overdriven transistor using the charge storage effect is provided as the delay element (F i g. 7, 9). 7. binary stage according to claim 6 with a trigger circuit which has an internal self-holding (RS memory), characterized in that the control electrodes of the two switching elements of the trigger circuit are each connected to the emitter of a transistor (28, 29) , in each of its collector circuits the clock (T) is fed in and an AND element is connected to its base circuit, one AND element (11 to 13) through the signals (Ä and T) and the other AND element (11 ' to 13 ') is controlled by the signals (A and T) ( FIG. 7). 8. Binary stage according to claim 1 and 2 or claim 3, in which a storage element with logically linked input conditions is provided as a bistable multivibrator, which consists of an OR-NOT element (output #i) with a downstream inverter (output A) , the OR-NOT element is controlled by three AND elements, characterized in that an AND element is controlled by the signals (C and A) and the third AND element is controlled by the signals (T and A) (F i g. 2, 4). 9. binary stage according to claim 1 or one of the following, characterized in that the AND elements are each formed by passive elements consisting of diodes and a resistor. 10. Binary stage according to claim 3 and 9, characterized in that the common connection point of the diodes of the control AND element is connected directly to the base of the controlled transistor. 11. Binary stage according to claim 1 or one of the following, characterized in that several binary stages are interconnected to form a static counter. Documents considered: German Auslegeschrift No. 1 214 729.