DE1512450A1 - Bistable logic circuit - Google Patents

Description

Patent attorney Dr. CLAUS REINLÄNDSH PATENT ADVOCATE

DIPL-ING. H. KLAUS BERNHARDT ^{s6 P11}

8000 MÖNCHEN 23 ■ MAINZERSTR.5

SYLVMIA ELECTRIC PRODUCTS INCORPORATED Wilmington, Delaware, TJSA

Bistable logic circuit

Priority: February 8, 1966 - United States Ser.No. 525.894

The invention relates, and more particularly, to bistable logic circuits Flip-flops and input circuits for checking the operating status of flip-flops.

Bistable circuits are used in digital computers and electronic data processing systems to perform various logic tasks. A bistable logic circuit is commonly called ¹¹ JK. Flip-flop ".

The operating state of this known circuit is the flip-flop changed by the fact that periodic clock pulses and information signals appear at the information inputs of the circuit.

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A control circuit stores a charge during the passage of the leading edge of a clock pulse if the signals at the information inputs indicate this. The stored charge triggers the flip-flop from one operating state to another when the trailing edge of the time pulse expires.

This circuit has better operating speed and better Trigger properties even when there are poor trigger impulses and the load has a high fading capacity. The time pulse also blocks the information inputs as soon as they have been used. In addition, the circuit has a discharge network so that each clock pulse removes the remnants of a stored charge that was not used in the previous clock cycle became.

However, residual effects from previous operating cycles are sometimes disturbing undesirably, the operation of the circuit in subsequent operating cycles.

According to the invention, a bistable logic circuit is characterized in that that an input circuit for processing input information and for checking the operating status of a flip-flop Has elements that change the state of the flip-flop depending on the input information received and that of the effects of the Input information is cleared immediately after it has been used to change the state of the flip-flop.

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In particular, the bistable logic circuit according to the invention contains a · first and a second flip-flop section, each of which has two operating states « have, and feedback connections between the two flip-flop sections, which ensure that the two sections imaer have different operating states. A control circuit has input terminals from the flip-flop that receive signals Velche show the operating status of the two flip-flop sections, and output connections to the flip-flop sections with which signals that change the operating state of the flip-flop sections. Periodic clock pulses are sent to an input signal terminal given to the control circuit.

The control circuit includes an input connection and to the Input signal terminal connected devices that can be actuated in this way are that a charge store during the presence of a clock pulse is charged at the input signal terminal. Another device in the control circuit is with the charge store and connected to an output connection and is actuated so that prevents a signal from occurring on the output connection while a signal is present on the input signal terminal will. This device can also be operated, da.3 in the charge storage stored charge is used to generate a signal on the output connection that indicates the operating status of the Flip-flop sections upon termination of the clock pulse signal at the Input signal is changed.

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In addition, the control circuit contains a device! the one Connects input connection to the charge storage device and which can be actuated so that it is used for discharging the charge storage device The occurrence of a signal on the input connection provides that the charge stored in the charge storage device has been used for this purpose is to bring about a change in the operating state of the flip-flop sections and therefore the charge is no longer required.

Further objects, features and advantages of the logic circuit according to the invention emerge from the following description in conjunction with the drawing, in which a schematic circuit diagram of a bistable Circuit is shown with features of the invention.

general description

The bistable circuit according to the invention shown in the drawing operates to have a high voltage signal at either output terminal A or output terminal B and a signal low voltage at the respective other output terminal. A positive clock pulse of about the same voltage as that The high voltage signal is periodically applied to the clock input terminal.

Two sets of information inputs are provided for the circuit, each having two groups clamped in. The clamps of one

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Groups of the first set of clamps are marked with J ', J _? and J, and the terminals of the other group of the first set are marked L., L "and L ... The terminals of one group of the second set of terminals are marked K., " S. and K, and those of the other group of the second set with M., M "and M ,. Either high-voltage or low-voltage signals are applied to the information input terminals.

The circuit switches its operating state and accordingly the Voltage level at output terminals A and B according to time pulses depending on the voltage levels of the signals at input terminals J, K, L and M. When a high voltage signal is present at output B and a low voltage signal at output A, and all J input terminals or all L input terminals are at high voltage, a time pulse changes the operating status of the Circuit, and there will be a low voltage signal at output B and a high voltage signal at output A. In a similar way In this way, the circuit will return to its original operating state at the next clock pulse if a high voltage signal occurs is at every K input or at every M input.

When the output terminal B is high voltage, and at the same time any of the J input terminals and any of the L input terminals a low voltage signal is present, a time pulse does not trigger a change in the operating status. Similarly, if the

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Output terminal A carries high voltage and at the same time at an or several of the K input terminals and one or more of the M input terminals If there is a low voltage signal, a clock pulse will not trigger any change in the operating status. Venn a High voltage signal at all J input terminals or at all L input terminals and there is also a high voltage signal at all K input terminals or all M input terminals, a time pulse provides for the circuit to complement, i.e. the operating states changes. This switching characteristic brings the circuit into the category of a J-K-Plip-Flop.

Flip-Flop Sections - Description

The circuit shown has two flip-flop sections, a first flip-flop section 10 with the output terminal A and a second flip-flop section 11 with the output terminal B. Two transistors Qg and Q ™, each in one of the two Flip-flop sections, form a
Pair of flip-flops. The base of each flip-flop transistor is connected to the positive operating voltage B + via the resistor · Rg or H_.

Each of the transistors of the pair of flip-flops is connected to a circuit as described in the earlier application US Ser. No. 281.183
on May 17, 1963 by Richard E. Bonn and Richard C. Sirrine, assigned to the assignee of the present application

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is · Wi * is described in more detail in this earlier application, each flip-flop section provides a high voltage output signal at the associated output terminal when it is in its operating state "Off" and supplies a low voltage signal at the output terminal when it is is in its "On" operating state. A section is switched either "On" or "Off" when certain signal combinations occur at the input.

The collector of the first NPN flip-flop transistor Qg is directly connected to the base of an NFN input transistor Q ^. The input transistor has two emitters to which the input signal is applied. One emitter is connected to an adjusting terminal 17 and the other emitter is connected to a first input connection line 12. The collector of the input transistor Q ₁ . a · NFN coupling transistor Q is connected directly to the base. The collector of the coupling transistor is connected to the positive operating voltage B + through a collector resistor R, and the emitter is connected to ground via an emitter resistor Rc. An NFN output _{transistor Q 1} has its base connected directly to the emitter of the transistor Q., the emitter is connected directly to ground and the collector is connected directly to the output terminal A.

Another NPN transistor Q, with its base is directly connected to the Collector of transistor Q. connected, its collector is connected to the

positive operating voltage B + connected through a resistor R_,

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and the emitter via two series-connected resistors R. and R ₁ - with earth. An NPN voltage setting transistor Q_ has its base connected directly to the emitter of the transistor Q, the collector is connected _{to the positive operating voltage B + through a resistor R 1} , and the emitter is connected directly to the output terminal A.

A second section of the flip-flop contains the second transistor Q_ of the flip-flop pair and another circuit similar to that of the first section. The base of an input transistor Q ₀ is directly connected to the

Collector of the flip-flop transistor Q ″ connected, and the collector is directly connected to the base of a coupling transistor Q _q . The input transistor has two emitters to which input signals are given. One emitter is connected to a reset terminal 13 and the other emitter is connected to a second input connection line 14.

The collector of the coupling transistor Q is connected to the operating voltage B + _{via a resistor R fl} , and the emitter is connected to ground _{via a resistor R 11.} The emitter of the coupling transistor Q _Q is also connected directly to the base of an output transistor Q ₁₉ , the emitter of which is directly connected to earth and the collector of which is connected directly to the output terminal B.

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A voltage setting transistor Q ₁₀ is connected to the base directly to the collector of the coupling transistor Q, the collector ± s% connected to operating voltage B + via a resistor R _q , and the emitter is connected to ground _{via series-connected resistors R 12} and R _{1 -} . The emitter of the transistor Q _Q is also connected directly to the base of a further voltage _{setting transistor Q 11} , the collector of which is connected _{to the operating voltage B + via a resistor R 10} and the emitter of which is connected directly to the output terminal B.

Feedback between the first and second sections of the flip-flop is provided by feedback connections I5 and 16. The first feedback connection 15 connects the collector of the first Coupling transistor Q directly to the emitter of the second flip-flop transistor Q. The second feedback connection 16 connects the collector of the second coupling transistor Q directly to the emitter of the first flip-flop transistor

Flip-flop sections operation

The flip-flop circuit operates in the following manner, with first it is assumed that the first section 10 is in the "on" state, so that the voltage at the output terminal A is at a low level and the second section 11 is in the "off" state, so that the voltage is on output terminal B is high. There are high tensions on the

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terminal 17 and the reset terminal 13 · The input connection lines 12 and I4 Bind connected to elements showing high impedance, as will be shown in detail later, so that the other emitters of the input transistors Q_ and Q _{8 are} high.

When the circuit is in this operating state, current flows through resistor R ₇ and the forward-biased base-emitter path of the second flip-flop transistor Q "to the collector of the first

Coupling transistor Q, which is at low voltage because of this Transistor is highly conductive, the reasons for this will be explained later. The current continues to flow through transistor Q. to earth via resistor

stood Rp. or the base-emitter path of the transistor Q., the conductive is.

Current flow through resistor R ₇ and the base-emitter path of the flip-flop transistor Q ensures a large voltage drop across resistor R ₇ , so that the voltage at the base of transistor Q _{7 is} quite low · Even if transistor Q _{7 is} in the control area works, the line in the collector circuit is low and the voltage at the collector remains low. This low voltage is applied to the base of the input transistor Q so that it operates in the low conduction state, with low conduction in the collector circuit and low voltage at the collector.

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The arrangement of the in series connected resistors R "and R. ₁ with the coupling _{transistor Q Q} is chosen so that when the low voltage from the collector of the input _{transistor Q 8 is applied} to the base of the transistor Q _Q , only a very narrow reverse current through the transistor and the series of resistors R _Q and R. flows. There is therefore a fairly high voltage at the collector of transistor Q and ** at the emitter there is a fairly low voltage.

Due to the rather high voltage at the collector of the transistor Q, no current can flow from the operating voltage source B + through the resistor Rg and the base-emitter path of the first transistor Qg of the flip-flop pair, as it does through the resistor R ₇ and the flip -Flop transistor Q ₇ flows. The feedback voltage at the emitter of the transistor Qg together with the voltage at the base biases the transistor Qg into the conductive state, so that current flows in the collector circuit and at the collector of the transistor Qg causes a voltage that is higher than that at the collector of the other flip- Flop transistor Q ₇ is. The voltage at the base of the input transistor Q ₁ . is such that because the adjustment terminal is high voltage and the first input connection line 12 is high impedance, current is in the

Collector circuit of the transistor Q _c flows, so that one at the collector

relatively high voltage. The base of the coupling transistor Q.

thus holds a signal that turns the transistor into a highly conductive State preloaded.

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Relatively strong current flow through the coupling transistor Q. and the series resistors R, and R_ ensures a relatively low voltage at the collector and a relatively high voltage at the emitter. As already mentioned, it is this low voltage at the emitter of the second flip-flop transistor Q_ that ensures that the transistors Q ₇ , Q _fl and Q _Q operate in the manner described.

The arrangement of the transistors Qg, Q and Q. with the associated circuit forms the first element of a flip-flop, and the arrangement of the transistors Q ₇ , Q _fl and Q_ with the associated circuit form the second element of a flip-flop. As described, the first works

Element of the flip-flop in the "On" state and the second element in the state "The end". These states can be reversed in a manner to be described so that the first flip-flop element is in the "off" state. and the second flip-flop element operates in the "on" state. The feedback connections 15 and 16 of the coupling transistors of each element to the flip-flop transistor of the other element result in the operating conditions of the elements being maintained.

As has already been explained, when the second flip-flop element is in the "off" state, the voltage at the emitter of the coupling transistor Q _{Q is} low. This voltage is applied to the base of the output transistor QP and biases this transistor into the blocked state. In this state, the transistor Q _ represents a high impedance between the output terminal B and ground.

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The fairly high voltage at the collector of transistor Q is at the base of transistor Q ... Since the sum of the emitter resistances R ₁₉ and * R ₁ . is large compared to the resistance R ", transistor Q ₁ -not in strong conductivity biased. However, a small current flows through transistor Q ₁₀ * Only a leakage current flows through transistor Q ₁₁ and this transistor can be considered to be essentially non-conductive. The voltage drop across the forward resistances of the base-emitter diodes of transistors Q and Q ₁₁ ensures a high voltage level at output terminal B.

When the first flip-flop element is in the "on" state, the voltage is relatively high high voltage at the emitter of the coupling transistor Q. the output transistor Q in the conductive state, so that between the output terminal A and ground a path of low impedance is created, as a result of which there is a low voltage level at the output terminal A. the Voltage at the base of transistor Q is relatively low so it is ensured that this transistor conducts only weakly and that transistor Q essentially does not conduct, so that the output terminal A is held at the low signal voltage level.

The output _{transistor Q 1} and the voltage setting transistors Q and Qp together with the associated circuit serve as the output part of the first flip-flop section, which isolates the flip-flop elements against the effects of the load connected to the output terminal A. _{The output transistor Q 12 is} used in the same way

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and the voltage _{setting transistors Q 10} and Q ₁₁ as an isolating output circuit for the second flip-flop section. The output circuits are controlled by the voltage signals at the collectors and emitters of the relevant coupling transistors Q. and Q _q .

Control circuit - description

The circuit that controls the operating state of the flip-flop contains an information input or actual control circuit 20 and a charge control circuit 21. The first part 22 of the actual control circuit contains a first ϊΤΡΝ information input transistor Q_, the base of which via a resistor R ₁ , - with the positive operating voltage B + is connected. As shown, the transistor has four emitters. An emitter is connected directly to the output terminal B of the second flip-flop section 11. The other three emitters are connected to information input terminals _{labeled J 1} , J. and J. The circuit of the first information input transistor Q _{? (} . Performs a logical AND operation, which provides a signal at the collector corresponding to the presence of voltage signals of high voltage at all emitters.

The first part 22 of the actual control circuit further contains a second NPN information input transistor Q _? / · »Whose base is connected to the positive operating voltage B + _{via a resistor R 17}

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is. This transistor also has four emitters, and one of the emitters is directly connected to output terminal B. The other three emitters are connected to information input terminals labeled L., L- and L, are designated. The circuit of the second information input transistor Q-g also fulfills the task of a logical AND-So hold and delivers a signal to the collector when signals are high Voltage value on all emitters.

The collector of the first information input transistor Q _{? {} . is directly connected to the base of a first clock pulse input transistor Q- ... The emitter of the transistor Q ₉₁ is connected directly to the input signal terminal 23, to which periodic clock pulses are applied. A second clock time input transistor Q_ _? is similarly connected to the base directly to the collector of the second information input transistor Q_g, and its emitter is connected to the clock signal input terminal 23.

The collector of the first clock time input transistor Q _? . is directly connected to the base of a first charging transistor Q ₁₇ . The collector of the charging transistor Q ₁₇ is connected to the positive operating voltage B + via a resistor R ₁ -, and its emitter is connected _{to ground via a capacitive element C 1} in the first section of the charge control circuit 21. The emitter of the charging transistor Q ₁₇ is also connected directly to the base of a switching transistor Q in the first section 24 of the charging control circuit. The emitter of the transistor Q,.

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is directly connected to the TJhrzeitimpuls input 25. The input connection 12 to the emitter of the input transistor Q- of the first flip-flop section 10 is directly connected to the collector of the switching transistor Q. so that an output connection from the first section 22 to the Control circuit is established.

The collector of the second clock time input transistor Q "" is directly connected to the base of a second charging transistor Q. _. The collector of this charging transistor is connected directly to the collector of the first charging transistor Q ₁₇ , and its emitter is connected directly to the emitter of the first charging transistor Q._.

Control circuit - charging mode

The first sections 22 and 24 of the control circuit control the operating state of the flip-flop in the following manner. If one or more of the emitters of the first input transistor Q _ are at a low voltage, no current flows in the collector circuit and the potential of the collector is low. This low voltage at the base of the first clock time input transistor Q biases this transistor into the blocked state, regardless of whether a TThrz ei timpuls high voltage is at the input terminal 23 or not. No current flows in the collector circuit of transistor Q ₂₁ , and there is thus a low voltage at the base of the first charging transistor _{Q 17 transistor}

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Q ₁₇ is thereby biased to a high impedance, ie essentially blocked. Similarly, if one or more emitters of the second information input transistor Q'r have a low voltage, no current flows into its collector and the potential of the collector is low. The second time input transistor Q _?? is thus blocked and the charging transistor Q. _Q is biased to high impedance,

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i.e. essentially disabled.

If both load transistors Q ₁₇ and Q ₁ are "substantially closed, is also the base of the first switching transistor Q. ₁ on low voltage. The transistor Q ₁ . is thus also essentially blocked and represents a high impedance for the input connecting line 12 to the first flip-flop section 10.

When the first section 10 of the flip-flop is in the "on" state and the second section 11 is in the "off" state, the output terminal B is at high voltage. An input signal of a high voltage level is therefore present at one of the emitters of each of the information input transistors Q_ and Qp £. If signals with a high voltage level are also present at all J input terminals or at all L input terminals, current flows in the collector circuit of the relevant information input transistor Q _pf - or Q ₉ C

If there is no time pulse signal at signal input terminal 2] 5, current flows in the collector circuit of transistor Q ₉₁ - or Q ₉ > - via the forward-biased base-emitter path of the associated time

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input transistor Q. or Q ₂ ? * ^The strong flow of current ensures that the potential at the base of the clock time input transistor is low. Therefore, there is only a small conduction in the collector circuit of the clock time input transistor Q. or Q_ ₂ , and the Ladetransietoren Q ₁₇ and Q ₁₈ remain essentially blocked.

If there is an AND state at the emitters of one of the information _{input transistors Q _ or Q 2} ^, because high voltage signals are present at all emitters of one of the transistors, the occurrence of a clock pulse signal at a high voltage level at the signal input terminal 23 reduces the current flow via the base emitter - Path of the associated clock time _{input transistor Q 1} or Q ₉₉ · The voltage at the base of this transistor rises and ensures current flow in the collector circuit. Current in the collector circuit also flows into the base of the associated charging transistor Q "" or Q._ and biases this transistor

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into the conductive state. In effect, a low impedance path is created between the voltage source B + and the capacitance C ₁ , and the capacitance C ₁ is charged very quickly. The transistors Q _? c> Q. and Q ₁₇ and the transistors _Q2 gt ^So section 22 ^and ^ 18 in ^each case together with the associated circuit, a gate circuit in which a load signal having the capacitance C ₁ via a transistor Q ₁₇ is coupled and Q ₁₈ when corresponding input signals to the transistors Q _9,. and Q ₉₁ or at the transistors Q ₂ g and Q _2? stand.

When the capacitance C charges, the voltage at the emitters of the charging transistors Q ₁₇ and Q ₁₈ increases and the voltage increases accordingly

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also at the baths of the switching transistor Q ₁ -. However, the high voltage of the clock pulse is also at the emitter of transistor Q ₁ , and therefore transistor Q ₁ remains blocked. The end result of an AND state at the emitters of one of the information _{input transistors Q 9} - or Q ₂₆ in the presence of a time pulse at the signal input terminal 23 is that a charge is stored _{in the capacitor C 1.}

The shorted transistor Q _{? Q} between the signal input terminal and ground acts as an oppositely biased diode that prevents the terminal from dropping below a voltage that is more than slightly below ground. This arrangement prevents the clock pulse input signal from becoming too negative and accidentally blocking the Sehalttransistor Q ₁ - conductive Kaoht.

Control unit and flip-flop switching operation

When the clock pulse ends, the voltage at the clock pulse terminal begins to drop, so that _{the voltage drops in the collector circuit of the conductive clock input transistor Q 21} or Q and the associated charging transistor Q ₁₇ or Q _{1b is switched} to the blocked state. The voltage at the emitter of the switching transistor Q ₁₄ / that is directly connected to the clock 23 is reduced.

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When the voltage at the emitter of transistor Q ₁ . is reduced and the current flow in the emitter circuit of the charging transistors Q "" and CL _Q

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ceases, the charging capacitance C ₁ ensures that a charge is stored in the forward-biased base-emitter path of the switching transistor Q ₁ , so that this transistor becomes conductive. When the charge in the transistor is used up, it is continuously replenished _{by the charge in the capacitance C 1.}

The switching transistor Q ₁ . thus forms a low impedance between the input connection line 12 and the low voltage level at the signal input terminal. Current flow in the collector circuits of the switching transistor Q along the input connecting line 12 ensures a strong current flow via the forward-biased base-emitter path of the first input transistor Q of the first flip-flop section 10 ^.

The reduction in the current flow in the collector circuit of the transistor Q ensures reduced conduction in the transistor Q and the series-connected resistors R ₁ and R 1 -. The voltage at the collector of the coupling transistor Q therefore rises and that at the emitter falls.

With the increase in the voltage at the collector of the coupling transistor Q the base-emitter path of the second flip-flop transistor Q " no longer forward biased so that the current flow through the base

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Resistance R _{7 is} reduced and the voltage at the base of transistor Q is increased. As a result, current flows in the collector circuit and tries to raise the voltage at the collector of transistor Q ".

Since the voltage values at the emitters of the input transistor Q _Q by the high voltage at the reset terminal 13 and the high impedance of the locked switching transistor Q _1t - which is connected to the EingangsverMndungsleitung 14 are high, the increased tension makes the base of the transistor Q ₀ for current flow in its collector circuit and

an increase in the voltage on the collector. The transistor Q _Q becomes conductive, and a strong current flows through the transistor and the series connection of the resistors R_ and R ₁₁ * The voltage at the collector of the coupling transistor Q falls, and the current flow through the forward-biased base-emitter path of the first Flip-flop transistor Qg rises. This flow of current reduces the voltage at the base of transistor Qr and reduces the flow of current in the collector circuit and the voltage at the collector.

The relatively low voltage at the base of the first input transistor Q biases this transistor in the blocked state whenever the switching transistor Q. is returned to the blocked state thereby creating a high impedance for the input connection line 12. The switching process is now complete and the Flip-flop elements are held in their reverse operating states, regardless of the existence or expiry of the operating states on the input connection line 12, which triggered the switching process

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The switching operation of the flip-flop elements reverses the voltage values at the output terminals A and B through the output parts of the flip-flop sections which are connected to the coupling transistors Q. and Q _q . In the first flip-flop section 10, the reduced voltage at the emitter of the coupling transistor Q. biases the base of the output transistor Q. so that this transistor essentially blocks. The output transistor CL thus forms a high impedance between the output terminal A and ground. The increased voltage at the base of transistor Q, together with the low bias voltage at the emitter due to the low voltage at output terminal A, ensures that transistor Q conducts strongly, which again ensures that transistor Q ₂ conducts strongly. These transistors conduct vigorously until the voltage at the output terminal A is returned to the high Vert, which is predetermined by the operating voltage, minus the bias voltage drop β at the base-emitter path of the transistors Q, and Q-.

The voltage at the output terminal A does not need to return _{to the high value immediately upon termination of the current flow through the output transistor Q 1,} taking into account various capacitance effects on the output terminal A and the associated external connections. This capacitive load must be charged so that the voltage at output terminal A can rise. The strong current flow from the operating voltage B + through the voltage setting transistors Q, and Q_ charges the load capacitance very quickly. When the output terminal A has the high

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Voltage value reached by the leakage current through the forward biased resistances of the base-emitter paths of the transistors is set, the transistors no longer conduct vigorously, and the first section of the flip-flop is in the "off" state.

In the second flip-flop section 11, the stronger current flow through the coupling transistor Q _Q and the series connection of the resistors R and R _{41 increases} the voltage at the emitter of the transistor Q _n . Of the

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Output _{transistor Q 1} - then becomes conductive, so that a low impedance path is created between output terminal B and ground, and a low voltage is set at output terminal B. The • wide flip-flop section 11 is thus in the "on" state.

Because the feedback connections between the flip-flops _{are removed from the coupling transistors Q. and Q 4} , the flip-flops are isolated from the output terminals A and B by the output parts of the flip-flop sections. The loads on the output terminals do not affect the switching speed of the flip-flop elements. In addition, the capacitive value of the charge _{store C 1 can be} smaller than if the stored charge were required for this, the switching transistor Q ₁ . to be kept in the conductive state until the voltage value at the output terminals A and B has stabilized. The smaller capacity also enables faster charging during the leading schedule of the time pulse.

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Discharge circuit - description and operation

The first section 24 of the charge control circuit 21 of the control circuit includes means for removing any excess charge _{remaining in the capacitance C 1} after the charge stored in the capacitance has been used to remove the flip-flop circuit from an operational state trigger in the other. The first capacitance C> is a first discharge transistor Q _1, parallel, whose collector is connected directly to the base of the switching transistor _Q1, and its emitter is connected directly to earth. The base of the discharge transistor Q ₁ is connected to the connection of the resistors R. and R ₁ , which are connected in series between the emitter of the voltage setting transistor Q 1 and ground.

When the first flip-flop section 10 is in the "on" state with the output terminal A at low voltage, the voltage at the emitter of the transistor Q is so high that the voltage at the base of the discharge _{transistor Q 1} , this transistor substantially biased to the locked state. Under these conditions, the transistor Q _{1 represents} a high impedance in parallel with the capacitance C, and the presence of the transistor has essentially no effect on the capacitance C,

When the first flip-flop element switches from the "on" state to the "off" state, the voltage at the collector of the coupling transistor Q rises and the transistors Q and Q ₉ conduct vigorously to the voltage value

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of exit mine A can be attributed to the high value. The voltage at the emitter of the transistor Q, increases and forth by the corresponding increase in voltage across resistor R _1, the discharge transistor Q ₁ is brought into the conductive state. The discharge transistor Q ₁ is thus a small parallel impedance to earth for any residual charges in the capacitance C ₁ or those in the base-emitter path of the switching transistor Q ₁ . remain saved. When the high voltage at the output terminal A is restored, the voltage at the emitter of the transistor Q is so high that the discharge transistor Q ₁ - is further biased into the conductive state, whereby it is ensured that the capacitance C _{1 is} completely discharged.

The arrangement is such that the voltage which is required at the collector of the coupling transistor Q. in order to produce conduction in the collector circuit of the flip-flop transistor Q _{7 is} less than that which is required for conduction through the transistor Q. , which is sufficient to _{bias the discharge transistor Q 1} into the conductive state. "Regardless of any effects that cause a delay in the processes described, the capacitance C ₁ cannot be discharged until the switching process has progressed to an irreversible point .

The discharge circuit works in such a way that the capacity immediately after using the stored charge to switch over

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of the flip-flop is discharged into the other operating state. This process is independent of the extent to which output terminal A is connected to the high voltage level has been fed back. The charge control circuit is thus freed from the effects of the input information, without delays occurring which may be caused by the load on the output terminal.

Additional circuit and operation

The control circuit includes second sections 25 and 26 of the information input circuit 20 and the charge control circuit 21 similar to the first sections. The information _{input transistors Q? 7} and Q _{? Fi} together with time _{input transistors Q 9} and Q_. and charging transistors Q _iq and Qp ₀ work in the same way as the information _{input transistors Q and Q 2} g »time input transistors Q and Q""and charging transistors Q ₁ " and Q. _{o of} the first section of the information

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tion input circuit. Similarly, the switching transistor Q is

to a second charge store C _? and its collector is connected to the second input connection line I4 to the emitter of the second input transistor _{Q Q of} the second flip-flop section 11. A discharge device with a discharge transistor Q. ^ parallel to the charge store C- is provided in a similar manner, which is also actuated by the output part of the second flip-flop section 11 by means of a connection to the emitter of the voltage setting transistor Q _10.

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When the operating state of the flip-flop has been changed and the first section 10 is in the "off" state and the second section 11 is in the "on" state, the second sections 25 and 26 of the information input circuit and the charge control circuit operate in a similar manner to the first Sections to switch the operating state of the flip-flop during the following clock pulse cycle if signals with a high voltage level are present at all K input terminals or all M input terminals. Switching takes place regardless of which information signals are at the J and L input terminals. Because one of the emitters of the information input transistors Q _9,. and Q -, - is connected to the output terminal B, which is at a low voltage level, the clock pulse has no effect on the first section of the control circuit.

As previously mentioned, the set and reset terminals 17 and 13, respectively, are normally connected to a source of high voltage. The connection of one of these terminals can be interrupted in order to produce a low voltage of a terminal and thus to set a desired operating state of the flip-flop. A low voltage signal at the emitter of an input transistor Q, or Q, _ft is used to trigger the flip-flop in the same way as a low impedance at one of the other emitters via input connection lines 12 or 14.

9098U / U02

Claims (1)

PATENT ADVOCATE DIPL-ING. H. KLAUS BERNHARDT
8000 MÖNCHEN 23 ■ MAINZERSTR.5 3a, Claims 1. Control circuit with which a signal is supplied to a circuit with which the operating state of this circuit is changed, with an input signal connection, an output connection from the control circuit to the circuit to be controlled, in which the change signal is transmitted, and an input connection to the control circuit of the circuit to be controlled, with which a signal is transmitted which indicates the state of the circuit to be controlled, characterized by a charge store, a connection between the input signal connection and the charge store, which can be actuated in such a way that it ensures
that a charge in the charge storage device during the presence of a
Signal is stored at the input signal terminal, a connection
of the charge storage with the output connection, which can be actuated in this way
is that the occurrence of a signal in the output connection is prevented when there is a signal at the input signal connection, and
The 6o can be actuated that the charge stored in the charge storage device is used to generate a signal at the output connection, with which the state of the circuit to be controlled on termination
of the signal at the input signal terminal is changed, and a connection between the input connection and the charge storage device, the 9098U / U02 is operable to discharge the charge storage device in response to the presence of a signal in the input connection indicating that the charge stored in the charge storage device was used to to cause a change in the state of the circuit to be controlled. 2. Input circuit for controlling the operating state of a flip-flop, a first section with a first input connection through which signals are transmitted that indicate the operating status of the flip-flop, a first output connection and a first charge store, a second section with a second input connection that transmits signals indicating the operating status of the flip-flop, a second output connection and a second charge accumulator, and an input signal terminal associated with the first and the second section is connected, characterized by a device in the first section, with which it is ensured that a load is stored in the first charge store when a signal is at the input signal terminal is, while a predetermined signal is on the first input connection, a device in the second section, with which it is ensured that a charge is stored in the second charge store when a signal is applied to the input signal terminal stands, while a predetermined signal is on the second input connection, a device in the first section with which the im First charge storage stored charge is used to generate a signal at the first output connection with which the operating state of the flip-flop on the termination of the signal at the input ... / A 5 909844/1402 _ÖAD oBiGiNAL output signal connection is changed, one device in the second Section with which the charge stored in the second charge storage device is used to send a signal to the second output connection to generate, with which the operating state of the flip-flop is changed on the termination of the signal at the input signal terminal, one first discharge device, which is connected to the first charge store and has an input connection thereto, the signals records, which indicate the operating status of the * flip-flop, and which are operable to respond to the occurrence of a signal at the Input connection indicating that the first charge store stored charge has been used to cause a change in the operating state of the flip-flop, ensures that the first Charge storage device is discharged, and a second discharge device which is connected to the second charge storage device and an input connection thereto which receives signals which indicate the operating state of the flip-flop, and which can be operated so that aie when it occurs a signal on the input connection which indicates that the charge stored in the second charge storage device has been used for this purpose is to cause a change in the operating state of the flip-flop, ensures that the second charge store is discharged. 3. Bistable circuit with a first flip-flop element that has two operating states has and a second flip-flop element that also has two operating states, feedback links between the two Flip-flop elements that ensure that the flip-flop elements 909844/1402 IS work in different operating states, and a control circuit, has the input connections from the two flip-flop elements and output connections to the two flip-flop elements, characterized in that the control circuit has two charge stores has an input signal terminal connected to the control circuit means in the control circuit is connected to one input connection, the input signal terminal and the first Charge storage device and can be operated in such a way that the first charge storage device is charged when an input signal is present at the input signal connection, while the second flip-flop element is in the first operating state and the first flip-flop element is in the second operating state, a device in the control circuit with an input connection, the input signal connector and the second charge storage device is connected and so on can be actuated that the second charge store is charged when an input signal is ate input signal terminal when the first flip-flop element in the first operating state and the second flip-flop element is in the second operating state, a device in the control circuit having an output connection, the input signal connection and the first Charge storage is connected and on a charge in the first charge storage and on the termination of the signal at the input signal connection can be actuated to put the first flip-flop element in the first operating state and the second flip-flop element in the "second operating state." to trigger a device in the control circuit with an output connection, the input signal connection and the second charge 909844 / U02 storage is connected and on a charge in the second charge storage towards and upon the termination of the signal at the input signal connection can be actuated in such a way that the second flip-flop element is in the first operating state and the first flip-flop element is triggered into the second operating state, a discharge device in the control circuit connected to an input connection and the first charge storage device and can be operated in such a way that it ensures that the first charge store is triggered in the first Operating state and the second flip-flop element in the second operating state is discharged towards, and a discharge device in the control circuit with the input connection and the second charge store is connected and can be operated in such a way that it ensures that when the second flip-flop element is triggered in the first operating state and the first flip-flop element in the second operating state towards the second charge storage device is discharged. 4. Bistable circuit with a first flip-flop section with two operating states, which can be set in such a way that there is a signal on a first output connection which indicates the operating status, and a second Flip-flop section with two operating states, which can be set so that there is a signal at a second output terminal that indicates the Operating state indicates a first feedback connection from the first flip-flop section to the second flip-flop section, with the it is ensured that the second flip-flop section works in the second operating state when the first flip-flop section is in the first 9098U / U02 3? Is operating state, and a second feedback connection from the second flip-flop section to the first flip-flop section, with which it is ensured that the first flip-flop section operates in the second operating state when the second flip-flop section is in the first operating state, characterized by an input signal connection, a control circuit with two sections, a first input circuit in the first section of the control circuit which is connected to the second output _; g connection of the second flip-flop section and the input; mgS3signalenschluß is connected and can be operated so that when an input signal is present at the input signal connection at the output connection, a signal is generated while the second flip-flop section is in the first operating state, e ^ no first charge store in the first section of the control circuit, a device in the first section of the control circuit which is connected to the output connection of the first input circuit and rax '; the first charge storage device and can be operated in such a way that it charges the first charge storage device when there is a signal at the output connection of the first input switching device, switching device! in the first section of the control circuit, which are connected to the first charge store, aem input signal terminal and the first flip-flop section, and ΰθ actuate _, 'bar that they are the first fiip-flop oektion from. switch the second operating state to the first operating state on the basis of a charge in the first charge store and the termination of the signal at the Singangsösignalanschluss, a discharge device in the first ... A 7 909844 / U02 'BAD ORIGINAL -rt-r - Section of the control circuit with the first Ladungsepeicher and the first flip-flop section is connected and operable in that the first charge storage due to the switching of the first flip-flop section is discharged in the first operating state, a second input circuit in the second section of the control circuit which is connected to the first output terminal of the first flip-flop section and the input signal terminal and is operable to generate a signal at its output connection when there is an input signal at the input signal terminal when the first flip-flop Section is in the first operating state, a second charge storage device in the second section of the control circuit, a device in the second section of the control circuit which is connected to the output connection of the second input circuit and the second charge storage device and can be operated such that the second charge storage due to the presence of a signal on the Au The output connection of the second input circuit is loaded, a switching device in the second section of the control circuit which is connected to the second charge store, the input signal connection and the second flip-flop section and can be actuated so that the second flip-flop section can be operated from the second operating state is switched to the first operating state due to a charge in the second charge store and the termination of the signal at the input signal connection, and a discharge device in the second section of the control circuit, which is connected to the second charge storage and the second flip-flop section and the second charge storage discharges due to the switching of the second flip-flop section into the first operating state. 9098AA / U02 bad original 5 bistable circuit, consisting of a first flip-flop section with a first operating state, during which a first predetermined voltage level is generated at the first output terminal, and a second operating state, during which a second predetermined voltage level is generated at the first output terminal, a second flip- Flop section with a first operating state, during which the first predetermined voltage level is generated at a second output terminal, and a second operating state, during which the second predetermined voltage level is generated at the second output terminal, a first feedback connection from the first flip-flop section to the second Flip-flop section which ensures that the second flip-flop section works in the second operating state when the first flip-flop section is in the first operating state, a wide feedback connection from the second flip-flop section to the first flip-flop section, with the ge it ensures that the first flip-flop section works in the second operating state when the second flip-flop section is in the first operating state, characterized in that the first flip-flop section has a first input connection and can be actuated in the second operating state , while a high impedance of the first input connection is presented, the second flip-flop section has a second input connection and can be actuated in the second operating state, while a high impedance of the second input connection is presented that an input signal connection is provided, a control circuit with two sections., a first input circuit in the first section of the control circuit, ^ ie BATH 909844 / U02 can be actuated so that a signal during the simultaneous occurrence of the first predetermined voltage level is generated at both input connections, the second output connection of the second flip-flop section is connected to the first input terminal of the first input circuit and the input signal terminal is connected to the second input terminal of the first input circuit, so that in order for the first input circuit to send a signal to the Output connection generated, the second flip-flop section must be in the first operating state and the first predetermined voltage level must be at the input signal terminal, a first charge storage device is provided is, a first charging transistor is connected between the first charge storage device and a voltage source and can thus be actuated is that when biased to the low impedance state, it enables the first charge store to be charged from the voltage source is, the first charging transistor is connected to the output connection of the first input circuit and this connection can be actuated is that it puts the first charging transistor in the high impedance state biased when a signal is absent from the output connection and the first load transistor is biased to a low impedance state if a signal occurs at the output connection, so that the first charge memory is loaded by the voltage source, a first Switching transistor is connected to the first input connection of the flip-flop section and can be operated so that it is biased the first flip-flop section in the low impedance state ... / A 10 9098U / U02 switches from the second operating state to the first operating state, the first Sehalttransistor with the first charge storage and the Input signal terminal is connected, and that this connection can be operated so that the first switching transistor in the. State high Impedance due to the presence of the first predetermined voltage level at the input signal connection and due to the lack of a charge is biased in the first charge storage, and is actuated so that the first switching transistor in the low impedance state through the presence of a charge in the first charge storage device is biased if the first predetermined voltage level is not at the input signal connection stands, so that the first flip-flop section is switched from the second operating state to the first operating state, a first discharge transistor in parallel across the first charge store lies and can be actuated in such a way that it enables the first charge storage device to be discharged when biased into the state of low impedance, the first discharge transistor is connected to the first flip-flop section and this connection is operable so that the first Discharge transistor is biased into the high impedance state while the first flip-flop section is in the second operating state, and can be operated so that the first discharge transistor in the low impedance state is biased when the first flip-flop section from the second operating state to the first operating state is switched over, so that the ere te charge storage device is discharged, a second input circuit in the second section of the control ... / 11 9 0 9 8 k A / U 0 2 eAD device is provided which can be operated so that a signal is generated at the output connection when the first predetermined voltage level is at the same time at the first and second input terminal, the first output terminal of the first flip-flop section is connected to the first input terminal of the second input circuit and the input signal terminal is connected to the second input terminal of the second input circuit, so that the first flip-flop section must be in the first operating state and the first predetermined voltage level must be at the input signal terminal if the second input circuit is to generate a signal at the output, a second charge store is provided, a second charging transistor is connected between the second charge storage device and a voltage source and can be actuated so that when biased into the low impedance state it enables the second charge storage device to be charged by the voltage source, the second charging transistor as well The output connection of the second input circuit is connected and this connection is operable so that the second charging transistor is biased into the high impedance state when a signal is absent at the output connection, and the second charging trantiistor is biased into the low impedance state when a signal occurs at the output connection, so that the second charge store is charged by the voltage source, a second switching transistor is connected to the second input connection of the second flip-flop section and can be operated so that it is biased into the low impedance state the second flip -Flop section from the second operating state to the first ... / A 12 909844 / U02 bad The operating state switches over, the second switching transistor with the second Charge storage and the input signal terminal is connected and this connection can be operated in such a way that the second switching transistor is biased to the high impedance state when at the input signal terminal the first predetermined voltage level is and no charge is contained in the second charge storage device, and is actuatable so that the second holding transistor is biased to the low impedance state if a charge is contained in the second charge storage device while the first predetermined voltage level is not at the input signal terminal stands, so that the second flip-flop section stops from the second operating state to the first operating state, a second Discharge transistor is parallel across the second charge store and can be operated in such a way that it enables the second charge storage device to be discharged when biased into the low impedance state, and the second discharge transistor is connected to the second flip-flop section wherein the connection is operable to bias the second discharge transistor into the high impedance state, when the second flip-flop section is in the second operating state, and can be actuated in such a way that the second discharge transistor is in the state low impedance is biased as soon as the second flip-flop section a switch is made from the second operating state to the first operating state, so that the second charging store is discharged will. 6. A bistable circuit claimed in claim [:, in ladurch, DAJ the first charge storage capacitive egg _L 'ENSC:. ;; f: he. has, the L:; itter des 909844 / U02 BATH ORIGINAL first charging transistor connected to ground through the first charge storage device the collector with the voltage source and the base with the output connection of the first input circuit, the emitter of the first switching transistor is connected to the input signal terminal, the collector to the first input connection of the first flip-flop section and the base is connected to the emitter of the first charging transistor, the emitter of the first discharging transistor is connected to ground, the Collector with the base of the first switching transistor and the base with the first flip-flop section, the second charge storage capacitive Properties, the emitter of the second charging transistor through the second charge storage device is connected to ground, the collector to the voltage source and the base to the output connection of the second Input circuit, the emitter of the second switching transistor with is connected to the input signal terminal, the collector to the second input connection of the second flip-flop section, and the base to the emitter of the second charging transistor, and the emitter of the second Discharge transistor is connected to ground, the collector to the Base of the second switching transistor and the base with the second Flip-flop section. 7. Bistable circuit with two flip-flop elements, both flip-flop devices which have a leading input connection and an outgoing gonge connection, characterized in that, that a second coupling circuit is provided in the second flip-flop element is, which has two operating states, the second coupling circuit ... / A 14 9098U / U02 ORIGINAL BATHROOM fs- connected to the input connection of the first flip-flop device and is operable to cause the first flip-flop device works in the first operating state when the second coupling circuit is in the second operating state, and ensures that the first flip-flop device operates in the second operating state when the second coupling circuit is in the first operating state, one first input circuit in the first flip-flop element is connected to the output connection of the first flip-flop device and a Having input connection, the first input circuit can be actuated in a first operating state as soon as a first signal state prevails at the input connection, can be actuated in the first operating state is when the first flip-flop device is in the first operating state and can be actuated in a second operating state when a second The signal state at the input connection is when the first flip-flop device is in the second operating state, a first coupling circuit is provided in the first flip-flop element, which has two operating states, the first input circuit with the first coupling circuit is connected and can be operated so that it ensures that the first coupling circuit operates in the first operating state when the first input circuit is in the first operating state, and can thus be actuated is that it ensures that the first coupling circuit operates in the second operating state when the first input circuit in the second operating state is that the first coupling circuit with the Input connection of the second flip-flop device is connected and can be operated so that it ensures that the second fllp-flop ... / A 15 1 ! 909844 / U02 Device in a first operating state works when the first Stick shift is in the second operating state, and ensures that the second flip-flop device works in the second operating state, when the first coupling circuit is in the first operating state, a second input circuit in the second flip-flop element with the output connection is connected by the second flip-flop device and has an input connection, the second input circuit in the presence a first signal state at the input connection can be actuated into a first operating state when the second flip-flop device is in the first operating state and can be actuated in a second operating state when a second signal state is present at the input connection when the second flip-flop device is in the is the second operating state and the second input circuit is connected to the second coupling circuit and can be actuated so that it ensures that the second coupling circuit operates in the first operating state when the second input circuit is in the first operating state and can be operated in such a way that it ensures that the second coupling circuit operates in the second operating state when the second input circuit is in the second operating state. 8. Bistable circuit according to claim 7 # characterized in that the The first flip-flop device contains a transistor, the base of which is connected to a first reference voltage source, the emitter of which is connected to the second coupling circuit and deesen collector is connected to the first input circuit, the first input ... / A 16 909844 / U02 circuit contains a transistor whose base is connected to the collector of the Transistor of the first flip-flop device is connected, whose collector is connected to the first coupling circuit and whose Emitter creates the input connection, the first input circuit contains a transistor whose collector is connected to the first reference voltage source and is connected to the input connection of the second flip-flop device, the emitter of which is connected to a second reference voltage. voltage source is connected and its base to the collector of the transistor the first input circuit is connected to the second flip-flop Device contains a transistor, the base of which is connected to the first reference voltage source, the emitter of which is connected to the collector of the transistor of the first coupling circuit is connected, and whose collector is connected to the second input circuit, the second Input circuit contains a transistor whose base is connected to the collector of the transistor of the second flip-flop circuit, whose collector is connected to the second coupling circuit and whose emitter provides the input connection, and the second coupling circuit contains a transistor whose collector rit the first Reference voltage source and the emitter of the transistor of the harvest flip-flop device whose emitter is connected to the second reference voltage source and whose J base is connected to the & collector of the Transistor of the second input circuit is connected. 9 «bistable circuit according to claim 7» characterized in that one Control circuit with the input connection of the first input formwork ... / A 17 909844 / U02 L - and the input connection of the second input circuit is connected and the control circuit can be actuated in such a way that it supplies the second signal state at the input connections and can be actuated in such a way that it that they have the first signal state at the input connection of the input circuit supplies that works in the second operating state. 10. Bistable circuit according to claim 7 »characterized in that a first output circuit is connected to the first coupling circuit and is operable to have a first output voltage level generated at the first output terminal when the first coupling circuit is in the first operating state, and can be operated so that it is a second output voltage level generated at the first output voltage terminal when the first coupling circuit is in the second operating state and a second output circuit is connected to the second coupling circuit and is operable to have the first output voltage level generated at the second output voltage terminal when the second coupling circuit is in the first operating state and can be actuated in this way, that they the second output voltage level at the second output terminal generated when the second coupling circuit is in the second operating state. 11. bistable circuit according to claim 10, characterized in that a Control circuit is provided with two sections, an input signal terminal, a first input control circuit in the first section of the ... / A 16 9098AA / U02 Control circuit with the second output terminal of the second output circuit and is connected to the input signal terminal and is operable to generate a signal on the output connection when one input signal is at the input signal connection, while the second Output terminal is at the first voltage level, a first charge storage device is provided in the first section of the control circuit, with a device in the first section of the control circuit the output connection of the first input control circuit and the first Charge storage is connected and can be operated so that the first charge storage is charged when a signal on the output connection the first input control circuit is a switching device in the first section of the control circuit with the first charge store, the input signal connection and the input connection to first input circuit is connected in the first flip-flop element, the switching device can be actuated so that it has the second signal state generated on the input connection, and is operable to generate the first signal state on the input connection when a charge is contained in the first charge storage device and the signal ends at the input signal terminal, a discharge device in the first Section of the control circuit is connected to the first charge store and the first output circuit and can be operated so that the first charge storage device is discharged when the first coupling circuit a second input control circuit switches to the first operating state in the second section of the control circuit with the first output terminal of the first output circuit and the input signal 909844 / U02 SO Connection is connected and can be actuated so that it is connected to the output connection a signal is generated while an input signal is connected to the input signal, while the first output connection is connected to the first Voltage level, a second charge accumulator in the second section the control circuit is provided, a device in the second section of the control circuit to the output connection of the second Input control circuit and the second charge storage device is connected, and can be operated in such a way that the second charge store is charged when a signal is present at the output connection of the second input control circuit is a switching device in the second section of the control circuit with the second charge store, the input signal terminal and the input connection is connected to the second input circuit in the second flip-flop element, and this switching device can be actuated in such a way that the second signal state is generated at the input connection and can be actuated in such a way that the first signal state is generated at the input connection when there is a charge in the second charge store and the signal at the input signal connection ceases, and a discharge device in the second section of the control circuit with the second charge storage device and the second output circuit is connected and can be operated so that the second charge storage device is discharged when the second coupling circuit in the first Operating status changes. 12. Logical gate circuit with a first input transistor circuit with a first input transistor, a first input connection ... / 20 9 0 9 8 Λ 4 / IA 02 u i> ο ρ BAD ORiGSNAL ζ λ to an emitter of the first input transistor, a second input transistor circuit with a second input transistor, "in which the base of the second input transistor connects to the collector of the first Input transistor is connected and a second input connection to an emitter of the second input transistor, characterized in that that the first input transistor circuit can be actuated so that it sends a signal to the collector of the first input transistor generated when a signal is present on the first input connection, the second input transistor gate is actuated so that a signal is generated at the collector of the second input transistor when a Signal is on the second input connection when a signal · on Collector of the first input transistor is, and a coupling transistor circuit is provided with a Koppoltransistor whose Base is connected to the collector of the second input transistor, the coupling transistor circuit can be actuated so that a signal is generated at another electrode of the coupling transistor when a signal is at the collector of the second input transistor. 13 · Gate circuit according to Claim 12, characterized in that the Base of the first input transistor via a resistor r.it a Voltage source is connected to the collector of the first input transistor directly connected to the 3ίϊ8ΐε of the second input transistor is, the collector of the second input transistor directly with the base of the coupling transistor is connected to the collector of the coupling transistor over a resistance; -nd r.with the voltage source vtrbun- ... / A 21 9098AA / U02 d «n let, and the emitter dee coupling transistor via an impedance old brothers tied 1st. 14 * Gatteriohaltung according to claim 13 »characterized in that the first · input transistor has a number of emitters, each to one others are connected by several first input connections, and the first input transistor circuit is operable to have a Signal as the collector of the first input transistor is only available if signals appear at all input connections at the same time. ' _BAD ORIGINAL 909847/1 A 02. -