DD134406B1 - CIRCUIT ARRANGEMENT FOR DETECTING CIRCULAR ARC DETERMINATION BY MEANS OF A POLYGON TRAIN - Google Patents

Description

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Field of application of the invention

The field of application of the invention are numerical path controllers "which approximate an arcuate trajectory through a polygon, the vertices of which are determined in a non-incremental manner"

Characteristic of the known technical solutions

From "Progress - Reports of the VOI magazines" 1974, row 2, no, 27, pages 34 to 37 is known to approximate the trajectory of a circle by an equally long secant of this circle existing polyline. Each secant is bounded by two adjacent vertices of the polygon. These vertices are again on a circle. As a result, its determination requires a circuit that follows the geometric relationships of the circle equation. Components of this circuit arrangement are thus summation elements, multipliers, squaring members and members for performing the root extraction

 The disadvantage of this known circuit arrangement is that the time for determining the vertices of the traverse is relatively long.

Object of the invention

The aim of the invention is to be achieved that the time for the determination of the vertices of the traverse is shortened.

Explanation of the essence of the invention

The defect described in the characteristic of the known technical solutions is due to the use of too large a number of circuit components.

To remedy this cause, the invention has the object, a circuit arrangement for approximate arc determination by means of a polygon, the vertices are in a plane defined by two axes of a numerical path control and successively set in non-incremental operation, using the path control belonging achszugeordneter Lageregelkreise and to provide a sequence control part, which is reduced in their circuit complexity «without a noticeable for the practical reasons increase in the error occurs in the approach of the circular path through the polygon.

According to the invention this is achieved in that a series circuit of a stepping angle, a squaring and a gate, another series circuit of a clock and a clock divider whose output is connected to the control input of the gate, two achszugeordord summation register, an initial value to which the set inputs of the Summationcregister in each case a first multiplier upstream of each summation register, the first input of which is respectively connected to the step angle sensor and whose second input is respectively connected to the output of the unassigned summation register, in each case a second multiplier upstream of each summation register, the first input of which

gear respectively connected to the output of the gate and the second input is connected to the output of the associated Sumraationsregisters, a linear interpolator connected by two inputs to one output of the summation register, by means of another input to the sequence control part and by means of two outputs with the position control circuits is connected and provided by the clock generator to the summation registers and multipliers connection.

Working Example

The figure shows the circuit arrangement according to the invention. In this case, a step angle encoder 1, a squaring 2, and a gate circuit 3 are provided in a series circuit. A clock 4 is the output side connected to a clock divider 5, the output of which is guided to the control input of the gate circuit 3.

Assigned to the x-axis is a summation register 6 and assigned to the y-axis another summation register 7 · The set inputs of both summation registers 6 and 7 are connected to an initial value transmitter 8. The summation register 6 is connected via its first input to the output of a first multiplier 9 and via its second input to the output of a second multiplier 10. In an analogous manner, connections of the summation register 7 exist between its first input and the output of a third multiplier 11 and between its second input and the output of a fourth multiplier 12.

The first inputs of the first multiplier 9 and of the third multiplier 11 are connected to the output of the step angle sensor 1 and the second inputs of the first multiplier 9 and the fourth multiplier 12 to the output of the second summation register 7.

The first inputs of the second multiplier 10 and the fourth multiplier 12 are connected to the output of the gate circuit 3, the second inputs of the second multiplier 10 and the third multiplier 11 to the output of the first summation register 6. A linear interpolator 13 is connected via separate inputs to a sequence control part 14, to the output of the summation register 6 and to the output of the summation register 7. The outputs of the linear interpolator 13 lead separately to the axis-associated position control circuits 15 and 16. Both summation registers 6 and 7 and all four multipliers 9 to 12 are connected to the clock 4 in combination.

The operation of the circuit arrangement is as follows: From the initial value transmitter 8, the initial coordinate values x referenced to the center of the circle and signed are used. and y _{A of} the arc output. With them both summation registers 6 and 7 are set to the initial position and the linear interpolator acted upon. The initial coordinate value χ. is returned to the second multiplier 10 and the third multiplier 11, the initial coordinate value y. the first multiplier 9 and the fourth multiplier 12 · The step angle sensor 1 outputs a set step angle value к, which is a measure of the angle over which the part of the approaching circular arc replaced by a polygon straight line extends. In this case, the step · angle value k; at a given allowable deviation of the actual trajectory of this circular arc in a size dependent on the circular radius, wherein step angle value к and circular radius are inversely proportional to each other. The sign of the step angle value к determines the direction in which starting from the initial value coordinates x. and у. the vertices are determined. The step angle value к is fed directly to the first multi-applicator 9 and the third multiplier 11 .

against it reaches the second multiplier 10 and the fourth multiplier 12 as the squared value k ² .

Thus, the first multiplier 9 forms the product κ · у _д , the third multiplier 11 forms the product к · χ _Δ · analogous to the other axis from the second multiplier

10, on the other hand, the product κ · χ., From the fourth multiplier 12 the analogous with respect to the other axis Pro

duct · output ·

The clock divider 5 changes the incoming clocks in a ratio of 2: 1 and actuates the gate circuit 3 · The Sumeationsregistern 6 and 7 different linking rules are fixed. Activated by the clock 4, they determine the coordinate values of the first corner point either with the values, depending on the position of the clock divider 5

4 - ^k · ^X A ⁺ VA or with the fourth

X ₁ «- k ² . k _a - к. y _A * x _A

V ₁ - - k ² . y _{A +} к. x _A + y _A

For the determination of the coordinate values X ₂ and Y _{2 of} the next vertex, these relations apply mutatis mutandis, whereby x _{A is} replaced by y and y _A by y- «The other vertices are then determined in the sequence determined by the clocks. The linear interpolator 13 ensures that the path to be determined between two adjacent corner points is a straight line. It triggers via the sequence control part 14 dis determination of the next vertex in stock ₉ The sequence control 14 also informs the linear interpolator 13 of the end coordinate values of the circular arc.

gens with. The linear interpolator 13 outputs the axis-related current path setpoint values to the position control circuits 15 and 16.

The described circuit arrangement is also applicable to the determination of the path velocity to be taken along the polygon access. Instead of the coordinate values of the vertices, the velocity components are determined which are used along the straight line extending to the vertex. The interpolator 13 as a whole thus only has tasks of the final value recognition and of the general process organization. Although the circuit arrangement is also suitable for the determination of standardized values, additionally required multiplications can be avoided when determining absolute values.

The circuit arrangement described has the advantage that it allows with few and simple means a very fast-running circular interpolation. This results in a high traversing speed with high measuring resolution. The investigations of the polygon tucking points and the axis-related velocity components, which proceed in an analogous manner, simplify the linear interpolator 13 used. Even with large step angles, a negligibly small bending of the approximated circular arc occurs. This feature also applies to the approach of a full circle.

Claims (1)

Brfindungsanspruch Circuit arrangement for approximate arc determination by means of a polygon whose vertices lie in a plane defined by two axes of a numerical path control and are determined successively in nlchtinkrementaler operation, with summation, multipliers and a squaring, using the .bahn control belonging achagierten Lagerβgelkreise, a flow control part, a Linear interpolator, a clock generator, an initial value transmitter and a step angle sensor, and further use of a gate circuit,
characterized by in that a series circuit of the step angle sensor (1), of the tyuadrierglieds (2) and the gate circuit (3) and a further series circuit of the clock (4) and a clock divider (5) are provided, the output of the clock divider (5) with the öteuereingang the gate (3) is connected, as summation two axis associated summation register (6} 7) are provided, the set inputs of both summation registers (65 7) are connected to the Anfangswertgeoer (8), each of the summation registers (6 | 7) Qin jev / ails first of Multipliers (9j 11) is connected upstream, the first input of each of the first multipliers (9l 11) connected to the step angle sensor (1) and the second input of each of the first multipliers (9; 11) each with the output de3 unassigned Sumraationsregiäters (6; 7), each of the summation registers (6j 7) is further preceded by a respective second of the multipliers (10j 12), the first input of each of the second. Multipliers (10; 12) connected to the output of the gate circuit (3) and the second input of each of the second multipliers (1С; 12) to the output of the associated Sunmationsregistars (6; 7), the linear interpolator (13) by means of two inputs in each case one output of the summation register (6, 7) is closed, by means of another input to the flow control part (14) and by means of two outputs with the Jaguar circuits O5 | 16) and a connection leading from the clock (4) to the summation registers (6 | 7) and multipliers (9i 101 11 j 12) is provided. For this 1 page drawing