CZ153897A3 - Method of accelerated coming up with clock time after undervoltage - Google Patents

Abstract

The time correction method has a microcomputer (11) which stores the measured time interval of an interruption in the normal operating voltage, allowing accelerated correction of the time after the normal operating voltage is restored by multiplying the frequency of the indexing pulses for the clock by a given factor. The stored interruption time interval held in the microprocessor is indexed backwards during the accelerated time correction, with the normal indexing frequency restored when the zero value is reached.

Description

Technical field.

The present invention relates to a method for accelerating catching up of an hour after undervoltage, the clock being powered at five, equipped with a microcomputer and in normal operation catching up with the first clock signal, detecting the duration of the undervoltage and memorizing the microcomputer. the time is quickly caught up by the second clock signal with respect to the pulses of the first clock signal that occur during the catching up time required for the quick clock up, each time the second clock clock pulse decreases in the microcomputer terminated when the catch-up value stored in the microcomputer is zero.

A method of the kind mentioned above is known therefrom. U.S. Pat. DE 43 07 854 C, which discloses Prep NaCl clock supplied from the mains and having switching processor clock, the switching clock are _NAV soldered through a network rectifier, a divider for -napětí-j-E Control w paméíovým condensate Orem. The clock switching processor comprises a quartz oscillator controlled clock time counter and an electromechanical clock drive controlled by this counter by means of periodically pulse-step pulses, so that a changeover contact is actuated depending on the position. The switching processor includes a total number of clock step pulses to be transmitted but not yet transmitted and which each time the clock step pulse is transmitted will see their value by one. When a clock step pulse is transmitted, the counter is checked in the direction whether all the clock step pulses to be transmitted were also actually transmitted. If this is not the case, the counter increments the value by one, and the program continues to query the hour counter to determine if another hour step pulse should be sent.

invention.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of the above-mentioned kind which enables, after the undervoltage has ended, a fast and reliable catching up of the clock time without the need for a two-way counter.

This object is achieved according to the invention in that the accelerated catching-up is interrupted at the time of starting the regular, regular line, which is then continued.

Embodiments of the invention are set forth in the subclaims.

The embodiment shown in the drawings.

FIG. 1 shows a circuit diagram of a device for catching up the time detected by the clock.

FIG. 2 shows a flow diagram of a first variant of the device according to the invention.

FIG. An overview of a second variant of the device according to the invention is shown.

FIG. 4 is a characteristic of a first variant characterizing the duration of the second undervoltage that occurs before the duration has completely ceased ^; first preload.

Fig. 5 is a characteristic of a second variant characterizing the duration of the second stress that occurs before the duration of the first undervoltage has completely disappeared.

EXAMPLE 2

The apparatus, the wiring diagram of which is shown in FIG. 1, for catching up the time detected by the clock, comprises, for example, a bridge rectifier 1, a first voltage regulator 2, a second voltage regulator 3, a voltage divider 4 »switching transistor 5,

resistor 6, emitter. a resistor 7, a memory capacitor 10, controlled by a horseradish oscillator 9, and preferably contained in a free running PRC ("Pree Running Counter") »microcomputer 11, a relay 12 and a clock module 13. The clock module 13 drives. disc, 15-s-hexasulfurate The sliders or cams control the make contact 16 according to an adjustable and forwarded timer program. The clock module 7 is, for example, a stepper motor. Gray alternating on five feeds the voltage divider 4 through rectifier 1, as well as the inputs of both voltage regulators 2 and 3. The haptic divider 4 consists of two supports 4a and 4b, which are electrically connected In series, the series connection of resistors 4a, 4y. is arranged between the output of the rectifier 1 and the ground. The first voltage regulator 2 is e.g. a 12 volt regulator and the second voltage regulator 3 is e.g. 5 volt regulator,

- On the outputs of both voltage regulators 2, 3, there is always a capacitor C1 resp. C2 between the respective output and the ground. The output voltage of the first voltage regulator 2 is relative to the ground 12 V and is supplied via a base resistor 6 based on the switching transistor 5 and connected via the coil 12a of the relay 12 to the first output 11a of the microcomputer 11. Output voltage 5 V with respect to ground, the second voltage regulator 3 is connected partly to the supply inlet 11b of the microcomputer 11 and through the collector-amitor sleeps nacího transistor 5 as well ^{as, and} it included the emitter resistor 7 to the first terminal of the storage capacitor 8 and the power input to the counter PRC. With AC mains voltage U · ^ and so on. in the presence of an output voltage of 12 V on the voltage regulator 2, the output voltage of 5 V second on the pole regulator 3, via the switching transistor 5 and the emitter resistor 7, charges the memory capacitor 8 whose second pole is grounded. The switching node of both from 5 pores 4a and 4b is connected to the voltage control input 11c of the microcomputer 11. The return input 11d of the microcomputer 11 is connected to the return input 18 of the PRC counter, whose numerical value output 19 is connected to the data input 11e. microcomputers 11. Pulse output of microcomputer 11f; The lig is connected in two poles to the new motor 14, while the other input 11h of the microcomputer 11 is connected via a make contact 16 to the engine. As soon as the line voltage AC and thus the voltage divider 4 controlled by the output voltage of the rectifier 1 as well as the output voltage of the voltage divider 4 which falls below a certain value at the voltage-controlled input 11c of the microcomputer 11, the microcomputer 11 operates the PRC counter. they are disconnected via relay 12 simultaneously with clock motor 14. Due to capacitors C1 and C2 at the outputs of voltage regulators 2 and 3, their output voltage only disappears after about 3θ ms, so that the remaining and still connected part of the device remains both voltage regulators 2 and 3. powered during this time. Thereafter, only the PRC counter, which requires minimal supply power and which is then exclusively fed by the memory capacitor 8, is supplied. When the counter FRC_ is set, this counter is set to zero in regular operation. Thereafter, during a power failure or undervoltage occurring at the AC mains voltage U1, the pulse pulses of the quartz oscillator-driven pulse generator 10. calculate the time elapsed since the power failure by counting the pulse input CLI ». optionally from the beginning of the occurrence of no p-dpg. The microcomputer 11 is only switched on when the AC voltage rises again and exceeds a certain minimum voltage. When the recurrence minimum a voltage adopts microcomputer 11 gi _e i _n y ₉ of t _and the counter PRC in its counter JUCC imikropočí the counter 11 (Microcomputer Counter) and promptly catching up with the time detected by the clock module 13, as described hereinafter, since the clock during network failure or undervoltage remained.

In all variants of the method according to the invention, the clock of the clock module 13 is energized, equipped with a microcomputer 11 and, in normal operation, is guided by a first clock signal CLI, whose frequency is, for example, 1 Hz. At each undervoltage A, also in the event of a failure of the AC mains voltage U1, the duration of these four times is determined and memorized at least in the microcomputer 11. Since during the undervoltage A the clock remains stationary, CL2, this being performed taking into account the pulses of the first clock signal CL1, which are transmitted during the catch-up time required for fast catch-up. This is necessary because the frequency of the fast catch-up clock signal is limited by the low power of the clock motor 14 and the accelerated catch-up can therefore take a long time, for example several hours. During this relatively long run-in period, the clock must not forget its regular line, the pulses of the regular clock signal CL1 during this run-in period must be counted and taken into account by the clock. In all variations, at least every pulse of the pulse is less than one catch-up value stored in the microcomputer 11 by one. The accelerated catch-up time is completed when the catch-up value stored in the microcomputer 11 is zero.

The flow diagram of the first variant of the method according to the invention shown in FIG. 2 comprises eight function blocks 21 to 28 which are connected in series according to their numbering, the ninth function block 29 being connected via a separate input to the function block 25. Function blocks 1 to 29 they carry out the following functions in sequence consecutively designated by 'Roman numerals' I to IX, indicating:

v.

I: The voltage supply reappears after undervoltage A.

XI: Construction of supply voltages,

III: The contents of the FRC counter are transferred to the microcontroller 11C and stored there.

IV: The counter of the microcomputer 11 yUGC memorized value is multiplied by a factor (1 + L / f _n) to create účeken catch-up value.

In the accelerated catching up of the clock time by the fast clock signals CL2, the factor (1 + 1 / f _n ) multiplied by a value of 1 each time a single clock pulse of the fast clock signal CL2 is made.

XX — tAppearance of the next, second — undervoltage — B before the clock time induced by the first previous undervoltage A has been completely caught up.

VI: Multiplication of coasting value by factor (f / (1 + f _n )) remaining at the moment of the second undervoltage in the counter CC,

VII: The value multiplied by the factor (f _n / (l + f _R )) is taken from the counter / jCC of the microcomputer 11 to the counter

PRC and there will be remembered.

VIII: The second undervoltage B becomes effective and the supply voltages fall below their minimum value necessary for correct clock operation.

Thus, in a first variant of the method according to the invention, at the beginning of catching-up, respectively. The accelerated catch-up multiplies in the microcomputer the stored value of the undervoltage duration by the divisor (1 + 1 / f _n ), where f is the frequency of the second clock signal CL2, while still taking into account the pulses of the first clock signal CL1 for accelerated catching up. In this case, the value multiplied by the factor (1 + 1 / f _n ) is the aforementioned catch-up value memorized in the microcomputer 11. If, before the end of the accelerated catching-up, the second undervoltage B appears, of the previous under voltage A multiplied by the factor (f _n / (1 + f _n )) and then the value of the duration of the second undervoltage B is determined and the remaining catching up value multiplied by the factor (f _n / (1 + f)) The undervoltage duration value is the numerical value of the pulses of the first clock signal QLL, which SC preferably detects, for example, by an external counter PRG. IN

In this case ^: after the end of the first undervoltage A, the determined numerical value t1 of the counter pulses is assumed.

The memory PRC into the memory, e.g., the uCC of the microcomputer 11, is stored there. At the second undervoltage B ge, at the moment of starting the second preload B, the catch value of the first undervoltage A, increasing in the memory of the microcomputer 11, is then multiplied by a factor (f _n / (l + f _n )). there it will be remembered. Then, starting from this memorized value, the duration t _{9 of the} second undervoltage B is determined by counting the umpulses of the first clock pulse CL1 by the counter PRC and connected to the memorized value. The sum value thus obtained is transferred to the memory of the microcomputer 11 after the end of the second undervoltage B and is stored there to create a new valid catch-up value, in the same way as for the first undervoltage A.

In a second variant of the method according to the invention, see FIG. 3, the accelerated catching-up is interrupted during the current regular operation 31 to be carried out. regular operation 31 to the end, whereupon accelerated catching-up is continued. To this end, the accelerated catch-up is divided into a plurality of shorter catch-ups of 32 ^ to + n + 1 ^{and the} reuse is corrected before or after shorter accelerated catches of 32p ... »32 _{n +} ^ or between two successive catch-ups. 32 _n ^a Accelerated catching-up is performed again by the frequency f of the second clock signal CL2, whose pulses again decrease the catch-up value stored in the microcomputer every time they occur.

11, Because during each shorter catching-up 32 ^,

2 ^ _{n +} i is generally followed by several such reduction, the time interval T _n ^Me2 as two mutually consecutive catching up preferably multiple interval Tn second clock signal CL2. The time interval is, for example, 125 ms, which, for periodically short-circuit catching 32 ^, » ² n + 1 ^from P ° ví, sees the frequency f = 8 Hz of the second clock signal CL2. The time interval between two consecutive periodic regular operations is equal to one period TI = -ls of the first clock signal CLI if its frequency is 1 Hz. The period T1 of the first clock signal CL1 is advantageous by the period of the period T _n , the synchronous second clock signal CL2, which makes a shorter catching-up of 32 _ρ ··· »32 _{n +} ^. The regular operation 31 then enters the timing correctly instead of the time equal to the shorter catch _- up time 32 _{n + 4} , while being delayed by a period T _{n of} e.g. 125 ms after the second clock signal CLI. In the overview shown in FIG. 3, the second variant of the method according to the invention shows two consecutive two normally extending lines 30 and 31 between each other. which is. retracted, eg .. more shorter .dohánění? 2-L »^ 32» ·· »32 * _n at least one shorter doháne32" _{t (following} normal ongoing operation line 31, if at the moment of the beginning of the accelerated catching up is not yet completed.

In the first sub-variant of the second variant according to the invention, two interlocked centrally controlled interrupt signals are provided for the microcomputer 11; which during accelerated catching-up are effective on an identical clock-controlled pulse output 11f; At the same time as the pulses of the first clock signal CL1, the first of the two interrupt signals for the normally running line 30 and 30 respectively is called. 31, while the pulses of the first clock signal _{CII are at regular time intervals T _{n are} each _(N f -1) excited by the second interrupt signals for shorter catching 31-> 32 ", -

In a second sub-variant of the second variant according to the invention, a single interrupt signal is provided for the microcomputer 11. which during normal running 30 and 30 respectively. 31 is energized at the clock of the first clock signal CL1 and during accelerated deceleration 32 ^, 32 ^, ... or 32 _{n +} ^ in the clock of the second clock signal CL2.

If no values are stored in the PRC counter, then in all variants and sub-variants, the method of the invention is varied according to one of the following two methods:

If, up to the beginning of the second undervoltage B, at most half of the steps t _η + ί „„

U, f XZV between the start of the undervoltage A and B, then when the second undervoltage is detected before the end of the accelerated catching-up, the winding time t of the second phase is detected. jb is associated with the duration value t1 + t, _f lying between za and f x ZV of the start of both undervoltage A and B in order to create a new downstream validation value. Duration value t 2 income>; t _{u 2} is preferably a numerical pulse value of the first clock signal CLI, which is detected by an external counter PRC. After the end of the first undervoltage A, the detected pulse numerical value, as before, is transferred to the memory of, for example, the microcontroller '* and stored there. In the second undervoltage B, the duration value t _u j + t _zv , lying between the two starts of the two undervolutions, is then added by the pulse counting in the external counter PRC to the duration value t 'second undervoltage B.

The thus obtained sum value t, + t + t ', u, lv u, 2, after the second undervoltage B has ended, is taken into the memory of the microcomputer 11 and memorized there to create a newly connected, valid catch-up value. This is shown in principle and in the form of a characteristic in FIG. 4, where the contents of the PRC counter are shown. jtiCC as a function of time tB. During the first undervoltage A, the numerical value of the PRC citation pulses increases linearly along the line MN. At the end of the first undervoltage A, the catch-up value stored in the counter decreases during its time t (shown in dashed lines). Before t, +

For 9 -L t, accelerated catching-up can be introduced, ie at point D of the characteristic, a second undervoltage occurs. In this case, only part t _n of duration t of the first undervoltage A has passed. rise according to the corrected line DS (set point) which is parallel to the line MN, which would only be possible if only the remaining catch-up value of the first undervoltage was stored in the PRC at this time, which is not the case in this case. Therefore, the microcomputer 11 causes, for the second under five B to take into account, when the point of characteristic L is reached, the operating point of the device immediately jumps back to the linearly rising characteristic line MN of the PRC counter and moves upwards thereafter. ). This generates a positive error P at the time measured by the clock: The clock is prevented by a maximum of one-half of the second undervoltage B. the sum of the duration t ' _{Ί of the} first undervoltage A and the duration t lying between the two undervoltage A and B.

If, on the other hand, at least half of the dwell times between the beginnings of both undervoltage A and B have already been carried out at the beginning of the second undervoltage B, then the duration value t 'is determined as a new follow-up catching current. value. The duration value t _{u 1} or t ₂ preferably again is a numerical value of the first clock signal CLI, which is detected by an external FRC counter. After the first undervoltage U jumps, the detected pulse numeric value is transferred to the memory uCC of the microcomputer 11 and stored there. At the second undervoltage B, the external PRC counter is reset and the duration t _{of 2 of the} second undervoltage B is determined by counting the pulses. and appends and appends lt to zero. After the second undervoltage B has been completed, the pulse number thus obtained is transferred to the microcomputer memory 11 and stored therein in order to create a newly valid valid catch-up value. This is in principle and in the manner of characterization shown in FIG. 5, where again the content of the PRC or the PRC. The microcomputer? 11 is shown as a function of time t. FIG. 5 is similar to FIG. 4, with the difference that after the end of the first undervoltage A, more than 50% of the duration t _η + t _{ww is carried out} in the accelerated deposition mode at point D, and U 9 X zw liv at this point During the second undervoltage B, the numerical value of the im pulses in the PRC counter would actually have to be represented in a correcting manner according to the line DS (set point), rising linearly parallel to the line MN ·, which would be possible only if the FRC has memorized the value of the remaining catch-up value of the first delay A, which is not the case here. Therefore, the micro-counter 11 for taking into account the second undervoltage B causes the FRC to reset when the D point is reached, so that the operating point of the device jumps to zero and from there continuously moves along the RT characteristic running parallel to the MH characteristic. upwards (actual value). This gives rise to a negative error in time, measured in hours: The clock is late by a maximum of half of the sum of the duration t ' _Ί and the time t, Uj -L -2W, which is between the two undervolts A and B after complete catching up of the second undervoltage B.

These procedures keep the error F as small as possible. In addition, it is important that the time t between the two delays is taken into account, since during this time there may also be normal catch-up that must be reflected in the clock control.

J OC o <

o ο-χ o

and

Claims (14)

PATENT CLAIMS A method of accelerating the clock time after undervoltage, wherein the clock and the voltage supply are equipped with a microcomputer and are routed in normal operation by a clock signal, the duration of the undervoltage is determined and memorized in the microcomputer. the clock signal taking into account the pulses of the first clock signal that occur during the catch-up time required for accelerated catching-up, at each pulse of the second clock signal, the memorized catch-up value is reduced by one in the microcomputer; the catch-up value stored in the microcomputer is zero, characterized in that the accelerated catch-up is interrupted during the current regular catch-up (31) in order to carry out this catch-up (31) and is then continued. Method according to claim 1, characterized in that in rapid catch-up it is divided into several shorter catch-ups (32j to 32 _{n + 4} ) and time-corrected regular into the catch (31) and is carried out after one of the shorter catches (32j). 32 ^), or between two consecutive two shorter catch-ups (32 _n , 32 _{n +} p. Method according to claim 2, characterized in that the period (1) of the first clock signal (CLI) is a multiplier of the period (Τ _β ) of the synchronous second clock signal (CL2) _{t by} which the shorter catch-up (3) is performed. 32 _{β +} <|) ^and that the regular catch-up (31) time-corrected takes place instead of a shorter catch-up < ³ W-, which is followed by a delay of one period ( ^T n) of the second clock signal (CL2). Method according to claim 2 or 3, characterized in that for the microcomputer (11) two interlocking, centrally controlled interrupt signals are provided which act on one of the two identical outputs (11f; lig) during accelerated catching-up. microcomputers (11) controlling the clock that simultaneously the pulses of the first clock signal (θ ^ Ι) always excite the first of the two interrupt signals for regular catch-up (30; 31) and that between clocks the clock pulses of the first clock signal (CLI) time intervals (T) each _(n _J f) species, e interrupt pulse shorter catching (32 ^ 32 AŘ _{+ n} <j)> where f is the frequency of the second clock signal (CL2). Method according to claim 2 or 3, characterized in that for the microcomputer (11) there is a readily interrupt signal which, during regular catch-up (30, 31), wakes in the clock of the first clock signal (CLI) and during accelerated post-clock second clock signal (θ ¹ * ^). 6. Method of accelerated catching up of clock time after undervoltage, while clock is powered - voltage is equipped with microcomputer and in normal operation catching up with the first clock signal, detection of undervoltage time17 and memorized in microcomputer. by means of a second clock signal with respect to the pulses of the first clock signal that occur during the catch up time required for accelerated catching-up at each pulse. the second clock signal decreases the stored catch-up value by one in the microcomputer. when the catch-up value stored in the microcomputer is zero, characterized in that at the beginning of the accelerated catch-up, to take into account the pulses of the clock signal (CLI) occurring at the time 3 multiplies the value of the undervoltage duration stored in the microcomputer (11) by a factor (1+ l / f _n ), where f is the frequency of the second clock signal (CL2) and that by the factor (1 + 1 / f) ), the catch-up value is stored in the microcomputer (11) U, 1. Method according to claim 6, characterized in that, at the next, second undervoltage (B), before the end u -. of the quick catch up multiplies the remaining catch up value of the first undervoltage (A) at this moment stored in the microcomputer (11) by the factor (f / (l + f _n )) and then the second duration value below five (B) is determined and connected to the remaining catch-up value of the first undervoltage (A) multiplied by the factor (f / (l + f _n )) to create a new, continuing valid catch-up value. 8. The method of claim 7, wherein the duration value (T ^ T?) '3 ^e numerical value always counts the first pulse signal (CLI), which is detected by a counter (PRC), that after the first undervoltage ( A) the detected pulse numeric value is transferred to the memory (yuCC) of the microcomputer (11) and there is memorized that at the second undervoltage (B) the remaining catch-up value of the first undervoltage (A) multiplied by the factor (f _n / (1+) f _n )) »is transferred to and stored in an external computer (PRC) and then, starting from this value, connected by pulse counting, the duration (t ₉ ) to the second undervoltage (B), which summation is the second undervoltage (B) is taken over (> uCC) by the microcomputer (11) and is memorized there in order to create a new consecutive valid catch-up value. Method according to any one of claims 1 to 6, characterized in that, at the next second undervoltage (B), the duration of the second undervoltage (t ₉ ) is determined before the end of the accelerated catching-up and joined to the duration value (t, + t,) lying between the beginnings of both undervoltage (A, B) in order to establish a continuing, valid catch-up value if, up to the beginning of the second undervoltage (B), a maximum of half the duration (t " _Ί + t". beginnings·· Uj 1 zw of both undervoltage (A, B). --- Ιϋ.-method of claim 9 and further comprising the value of time (t _l, t _u2) Undervoltage numerical value always counts the first pulse signal (CLI) which is detected by an external computer (PRC), the upon termination of the first undervoltage (A), the detected pulse numeric value is transferred to the memory (uCG) of the microcomputer (11) and there it is remembered that at the second undervoltage (B) starting from the value stored in the external memory (PRC) the duration (t.) of the second undervoltage is added to the duration (t, _η + t) lying between the starts of both undervoltage (A, B) by counting the pulses in the external counter (PRC), _η + t + t _o ) after the end of the second u, l zw u, 2 ^r undervoltage (B) is taken into memory (yuCC) of the microcomputer (11) and is memorized there to create a new consecutive valid catch-up value. Method according to one of Claims 1 to 6, characterized in that, at the next second undervoltage (B), the duration (t ₉ ) of the second undervoltage (B) is determined as a new consecutive valid catch-up value before the end of accelerated catching-up. in to. At the beginning of the second undervoltage, at least half of the duration (t ,, _η + ti lying between the beginnings) was caught up U | X ZW of both undervoltage (A, B). Method according to claim 11, characterized in that the duration value (t _u t _{u 2} ) of the undervoltage is always a numerical value of the pulses of the first clock signal (CLI), which is detected by an external counter (PRC) that after termination The first numerical value of the pulses (A) determined in the previous five pad (A) is transferred to the memory. (/ ifiC) of the microcomputer (11) and there it is remembered that at the second undervoltage (B) the external, counter (PRC) is cleared to zero and the duration value is determined by counting the pulses. (t ₉ ) of the second undervoltage (B), which after the second undervoltage (B) is over, takes over the memory (yj.CC) of the microcomputer ¢ 11) and records there for a new, consecutive valid catch-up value. 13. A method according to any of claims 1 to 6, characterized in that the value of the duration (tu ^ t ^^ _in each numerical value of the first pulse signal at a timing (CLI). Method according to claim 13, characterized in that) the numerical value of the pulses is determined by means of a counter (PRC), to whose counting input a first clock signal (CLi) * is supplied. Method according to claim 14, characterized in that the counter (PRC) is an idle external counter and, after the undervoltage (A, B) has been terminated, the count value of the duration pulses (t, t ₉ ) detected by it is transferred to the memory (ytCC). (11) and there it will be remembered.