CY1117018T1 - Κυκλωμα με τοπικη μοναδα τροφοδοσιας για τη μειωση διαρροων - Google Patents

Κυκλωμα με τοπικη μοναδα τροφοδοσιας για τη μειωση διαρροων

Info

Publication number
CY1117018T1
CY1117018T1 CY20151101048T CY151101048T CY1117018T1 CY 1117018 T1 CY1117018 T1 CY 1117018T1 CY 20151101048 T CY20151101048 T CY 20151101048T CY 151101048 T CY151101048 T CY 151101048T CY 1117018 T1 CY1117018 T1 CY 1117018T1
Authority
CY
Cyprus
Prior art keywords
section
circuit
supply unit
reduction
local supply
Prior art date
Application number
CY20151101048T
Other languages
English (en)
Inventor
Fadi Adel Hamdan
Anthony D Klein
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of CY1117018T1 publication Critical patent/CY1117018T1/el

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

Κοινοποιείται κύκλωμα με τοπική μονάδα τροφοδοσίας (408) για τη μείωση διαρροών. Το κύκλωμα έχει ένα πρώτο τμήμα (402) και ένα δεύτερο τμήμα (404, 406). Το πρώτο τμήμα (402) είναι ρυθμισμένο να λειτουργεί υπό ουσιαστικά υψηλότερη συχνότητα λειτουργίας σε σχέση με μια συχνότητα λειτουργίας του δεύτερου τμήματος (404, 406). Το δεύτερο τμήμα έχει μια τοπική μονάδα τροφοδοσίας (408) ρυθμισμένη για την αποσύνδεση του δεύτερου τμήματος αν το δεύτερο τμήμα είναι ανενεργό για τη μείωση του ρεύματος διαρροής που σχετίζεται με το δεύτερο τμήμα χωρίς να θυσιάζεται η απόδοση του πρώτου τμήματος.
CY20151101048T 2007-07-10 2015-11-19 Κυκλωμα με τοπικη μοναδα τροφοδοσιας για τη μειωση διαρροων CY1117018T1 (el)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/775,376 US7622975B2 (en) 2007-07-10 2007-07-10 Circuit having a local power block for leakage reduction
EP08781646.8A EP2171848B1 (en) 2007-07-10 2008-07-10 Circuit having a local power block for leakage reduction

Publications (1)

Publication Number Publication Date
CY1117018T1 true CY1117018T1 (el) 2017-04-05

Family

ID=39722692

Family Applications (1)

Application Number Title Priority Date Filing Date
CY20151101048T CY1117018T1 (el) 2007-07-10 2015-11-19 Κυκλωμα με τοπικη μοναδα τροφοδοσιας για τη μειωση διαρροων

Country Status (7)

Country Link
US (2) US7622975B2 (el)
EP (1) EP2171848B1 (el)
JP (1) JP4995323B2 (el)
KR (1) KR101073247B1 (el)
CN (2) CN101689857A (el)
CY (1) CY1117018T1 (el)
WO (1) WO2009009703A1 (el)

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US7622975B2 (en) * 2007-07-10 2009-11-24 Qualcomm Incorporated Circuit having a local power block for leakage reduction
US7893722B2 (en) * 2008-09-11 2011-02-22 Arm Limited Clock control of state storage circuitry
US7683666B1 (en) * 2009-01-21 2010-03-23 Xilinx, Inc. Circuit component with programmable characteristics and method of operating same
KR101698010B1 (ko) * 2010-06-10 2017-01-19 삼성전자주식회사 스캔 플립플롭 회로 및 이를 포함하는 스캔 테스트 회로
US8456193B2 (en) * 2010-09-17 2013-06-04 Qualcomm Incorporated Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
US9097764B2 (en) * 2013-01-21 2015-08-04 Texas Instruments Incorporated Scan chain in an integrated circuit
KR102216807B1 (ko) * 2015-03-25 2021-02-19 삼성전자주식회사 반도체 회로
US9786339B2 (en) 2016-02-24 2017-10-10 International Business Machines Corporation Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation
US10033356B2 (en) * 2016-06-15 2018-07-24 Apple Inc. Reduced power set-reset latch based flip-flop
US11005459B1 (en) 2019-04-22 2021-05-11 Apple Inc. Efficient retention flop utilizing different voltage domain
US10890623B1 (en) 2019-09-04 2021-01-12 International Business Machines Corporation Power saving scannable latch output driver
US11139803B1 (en) 2020-09-23 2021-10-05 Apple Inc. Low power flip-flop with balanced clock-to-Q delay

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Publication number Priority date Publication date Assignee Title
US6078194A (en) 1995-11-13 2000-06-20 Vitesse Semiconductor Corporation Logic gates for reducing power consumption of gallium arsenide integrated circuits
WO2003067759A1 (en) 2002-02-06 2003-08-14 Koninklijke Philips Electronics N.V. Digital electronic circuit with low power consumption
US6667440B2 (en) * 2002-03-06 2003-12-23 Commscope Properties, Llc Coaxial cable jumper assembly including plated outer conductor and associated methods
US20030188241A1 (en) 2002-03-29 2003-10-02 International Business Machines Corporation CMOS low leakage power-down data retention mechanism
CN100372232C (zh) * 2002-10-29 2008-02-27 高通股份有限公司 减少集成电路内泄漏的系统
US6853212B2 (en) * 2002-12-20 2005-02-08 Texas Instruments Incorporated Gated scan output flip-flop
US20040119052A1 (en) 2002-12-20 2004-06-24 Beavers William Anthony Process for preparing alpha- and beta- methyl-gamma-butyrolactone and 3-methyltetrahydrofuran
US7092307B2 (en) * 2003-04-02 2006-08-15 Qualcomm Inc. Leakage current reduction for CMOS memory circuits
US7437634B2 (en) * 2003-05-13 2008-10-14 Intel Corporation Test scan cells
JP2005032102A (ja) 2003-07-09 2005-02-03 Matsushita Electric Ind Co Ltd スキャンテスト設計方法、スキャンテスト回路、スキャンフリップフロップ回路、スキャンテスト回路挿入用ｃａｄプログラム、大規模集積回路及び携帯デジタル機器
US7278076B2 (en) * 2004-06-30 2007-10-02 Intel Corporation System and scanout circuits with error resilience circuit
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US20070085585A1 (en) * 2005-10-13 2007-04-19 Arm Limited Data retention in operational and sleep modes
US7622975B2 (en) 2007-07-10 2009-11-24 Qualcomm Incorporated Circuit having a local power block for leakage reduction

Also Published As

Publication number Publication date
JP4995323B2 (ja) 2012-08-08
US20090015321A1 (en) 2009-01-15
KR101073247B1 (ko) 2011-10-12
CN105162449B (zh) 2018-10-30
JP2010532974A (ja) 2010-10-14
CN101689857A (zh) 2010-03-31
EP2171848B1 (en) 2015-08-19
US20100019815A1 (en) 2010-01-28
CN105162449A (zh) 2015-12-16
US7622975B2 (en) 2009-11-24
KR20100038436A (ko) 2010-04-14
US8314643B2 (en) 2012-11-20
WO2009009703A1 (en) 2009-01-15
EP2171848A1 (en) 2010-04-07

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