CS254232B1 - Connection for control of reversing pulse converter in bridge circuit - Google Patents

Abstract

The solution concerns a simple method of generating four phases of control voltage for complete unipolar control of a transistor reversing converter in a bridge connection with relief circuits for minimizing switching losses, which guarantees linearization of discontinuities in static dependences of the feedback characteristics, expands the controllability band of phase shifts of individual control voltages of the converter. It consists of three monostable flip-flop circuits, a bistable flip-flop circuit and a decoder, the truth table of which is defined by four equations for each orientation of the voltage on the load. The control signals are a width-modulated logic signal and a logic signal defining the orientation of the voltage on the load.

Description

The invention relates to a circuit for controlling a reverse pulse converter in a bridge circuit that solves a simple way of generating four phases of the control voltage for complete unipolar control of a transistor reverse converter ensuring linearization of discontinuities in static dependencies of the control characteristics.

In the control technology of electric drives, it is known to employ a unipolar control of a 4-quadrant reversing converter which makes it possible to halve the switching frequency of the transistor power transistors against the frequency of the ripple current under load. In contrast to conventional bipolar and bipolar suppressed control, current ripple and efficiency increase are halved. In principle, the logic levels of the control phases of the conducting branch are symmetrical and offset by π / 2, the time of simultaneous switching on of both transistors of this branch being given by the time of overlap of these phases. The logic levels of the control phases of the non-conducting branch are inverted relative to the neighboring phases in the individual bridges, taking into account the protection times that prevent the transistors from being switched on simultaneously in the danorn bridge.

Such unipolar control, however, does not accept the fact that, in the conventional wiring of an inverter with RLCD shunting circuits for switching the power transistors on and off, the current flows through the RL as a result of the non-uniformity of static characteristics around the zero-width control. modulated signal. In this way, a transient transducer - resistive-inductive load generates a measurable current region, whose width is proportional to twice the ratio of the protection time to the total clock time of the transducer.

These drawbacks are largely overcome by the wiring of the umipolar control of the reversing pulse converter of the invention, consisting of three momostable flip-flops, a bistable flip-flop, and a decoder.

Its essence is that the input width modulated control signal is connected to a bistable flip-flop, further to a monostable flip-flop triggered by the leading edge, to the monostable flip-flop triggered by the deceleration edge, and also to the decoder input. The input logic signal defining the direction of the load voltage is connected to the input of the monostable flip-flop triggered each time the input signal changes and is also connected to the decoder input.

The outputs of the three monostable flip-flops, the bistable flip-flop, together with the input width modulated signal and the logic signal defining the voltage direction on the load, form an input premature in parallel to the decoder input. The output of the decoder is four logic signals defining the control phases of the converter.

The advantage of this circuit is that it extends the bandwidth of the phase shifting of the individual control voltages of the reversing converter in the bridge circuit towards the protection period, without affecting the switching safety. The extension of controllability in this connection is achieved by a suitable way of dissipating the leading and coasting edges of the individual phases of the control voltage of the converter, by generating additional signals for the control voltage phase decoder.

By extending the drive control bandwidth, control continuity is achieved in the zero-frequency areas of the width-modulated signal, which has a beneficial effect on the course of the static dependencies of the drive, such as e.g. functional dependence of mean value of current on alternating current, when working with RL load. The characteristics are continuous, without relay type non-linearities, which significantly improve the inverter's control characteristics and can be used even for servo systems with the most demanding requirements for control characteristics.

1 is a block diagram of a reversing pulse converter control. Figure 2 is a block diagram of the drive with individual control phases.

The input width modulated logic control signal G terminal B is connected to the leading edge input of the triggered monostable flip-flop 1 whose output is connected to the address input 8 of the decoder 5. Furthermore, the input width modulated logic control signal 6 terminal 6 is connected to the leading edge input of the triggered bistable flip-flop 2, the output of which is connected to the address input 9 of the decoder 5.

The terminal B of the input width modulated signal 6 is also connected to the address input 11 of the decoder 5, as well as to the coasting edge of the triggered monostable flip-flop 3, the output of which is connected to the address input 10 of the decoder.

5. The input control logic signal of direction 7 is connected both to the address input 13 of the decoder 5 and to the input by changing the logic level of the triggered monostable flip-flop 4 whose output is connected to the address input 12 of the decoder 5. the control phase levels of each inverter switch.

Individual blocks can be characterized as follows:

The leading edge-triggered monostable flip-flop circuit 1 generates an auxiliary variable to the closing edge, through which the control voltage phases of the transducer of the conductor branch of the converter are alternately triggered. The pulse width is equal to the inverter's protection time.

234232

The leading edge-triggered bistable flip-flop 2 generates an auxiliary variable whose logic level determines the alternation of the simultaneous closing of switches S1, S3, respectively. S.2, S4 of the converter, in the interval of the decrease of the absolute value of the load current, in each such converter. In this way, the switching losses are evenly distributed over all the switches and a half switching frequency is achieved. power transistors versus the frequency modulated logic control signal frequency.

The ramp-down monostable flip-flop 3 forms an auxiliary variable that provides protection against the simultaneous switching on of the power transistors of switches S1, S2, or more. S3, S4. The width of the pulse generated is equal to the inverter protection time.

By changing the logic level, the triggered non-instable flip-flop 4 generates an auxiliary variable that provides protection against the simultaneous switching on of the power transistors of switches S1, S2 and S2, respectively. S3, S4 for asynchronous reversal request. The width of the pulse generated is equal to the width of the inverter protection time.

The decoder 5 implemented, for example, by the PROM, converts the instantaneous value of the input code into an output code that uniquely identifies the four phases of the control voltages. The operation of the decoder 5 is described by the following logical variables: A8, A9, A10, All, A12, A13 as the address inputs and D14, D15, D16, D17 as the data outputs of the decoder, the indexing corresponding to the individual address inputs and data outputs The data outputs 14 and 15 control the first branch and the data outputs 16 and 17 of the converter branch according to FIG. 2. Logic signals are in positive logic. For the required one direction of stress on the load:

D14 = (A8, A9 + A11, A9j, A12 ~

D15 = (A8 \ A9 + All. A9j .A12 _

D16 = (A8 · A9 + All. A9, A8, AID, ΑΪ2

D17 = (A8A9 4A114a9). A8. A10. AI2

For the second direction of stress on the load:

D14 ~ (A8 ~ .A9j ^ AUL · A9). AS. AÍO. ΑΪ2

D15 = (88, 99 + 44 A9). Á8. ΑΪ0. ΑΪ2

D16 = (88. A9 + All. A9 j. Al ~ 2

D17 = (88, 99 + all, 99). Alf

Claims (2)

234232 A leading edge bistable flip-flop circuit 2 generates an auxiliary switch, the logic level of which determines the simultaneous switching of the switches S1, S3 and S3 respectively. S.2, S4 of the transducer, in the range of the decrease of the absolute value of the load current, in the individual inverter. As a result, the switching losses are distributed evenly across all switches and half the switching frequency is achieved. power transistors to the frequency of the width modulated logic signal. The mono-stable flip-flop circuit 3, which is triggered by the running edge, forms an auxiliary circuit which provides protection for the simultaneous switching on of the power transistors of the slices S1, S2, p1sp. S3, §4. The generated pulse width is equal to the inverter protection level. By varying the logic level, the triggered non-steady flip-flop circuit 4 generates an auxiliary variable that protects against simultaneous tripping of the power transistors of switches S1, S2, and S2, respectively. S3, S4 for asynchronous reversing request. The generated pulse width is equal to the transducer latency. For example, the decoder 5 implemented by the pama PROM converts the instantaneous value of the code at the input to the output code, which are the unambiguous four-phase control sequences identified. The operation of the decoder 5 is described by the following logical variables: A8, A9, A10, All, A12, A13, as address inputs and D14, D15, D16, D17, as data outputs of the decoder, while indexing does not correspond to the individual address marking The data outputs 14 and 13 control the primary and data outputs 16 and 17 of the converter types according to FIG. 2. Logic signals in positive logic. For the required one load direction, the following applies: D14 = (A8 '. A9 + All. A9j. A12 ~ D.15 = (A8 + A9) .A12 _D16 = (A8. A9 + All. A9 A8, A10, A8, A17, A8, A9, A117, A8, A10, A12, A12, A14, A10, A12, A12, A12, A12, A12, A12, A14, A14, A14, A, D, - Alf. 'A9) .A8 .A0 .A2 D18 = (A8. A9 + All. A9 j. Xf (D17 = (A8. A9 + All. A9). Alf PSED Μ ET Reverse Pulse Converter Control Connection. in a bridge circuit consisting of a leading edge of the triggered monostable (flip-flop, leading edge of the triggered bistable flip-flop, run-in edge-triggered monostable flip-flop, varying the logic level of the trigger monostable flip-flop circuit, characterized in that the input terminal (6) is A modulated logic control signal is connected to the input edge by a trigger edge as well as the inlet edge of the triggered bistable flip-flop (2), as well as the input of the down-flush monostable flip-flop (3) and the address input (decayer (5j, the output leading edge) In the case of a monostable flip-flop triggered (1J is connected to an address input (3j of the decoder (5), the output of the leading edge bistable flip-flop (2) is connected to an address input (9) of the decoder (drawbar, output run-in) the edge-triggered monostable flip-flop (3) is connected to the address input (10) of the decoder (5), the terminal (7) of the directional control signal being connected to the address input (13) of the decoder (5j as well as the input by changing) the logical level triggered monostable flip circuit (4), the output of which is connected to the address input (12) of the decoder (5) dajové outputs (14, 15, 16, 17j pre-expose the four control phases výkonovýchspínačov · reverzačného AC-pulse bridge connection meničav. 1 sheet of drawings