CS253269B1 - Device for fast fourier transformation - Google Patents

Abstract

Fast Fourier Device transformation is concerned with computing and is intended for use in the apparatus for spectral correction analysis of signals. The essence of the solution is that the which contains four input registers, first summator, four product registers, two rotation vector registers, commutator and control block, moreover the second, third and fourth summators are involved, wherein the commutator is connected to the input registers attached to the appropriate summators whose outputs are connected to product registers, product outputs registers are attached to the respective summators and rotation vector registers outputs to the control block that is connected to the ee summers, with product registers and these to the commutator.

Description

AND

SaHBrijen: 07.07.81 3a «BKa: N> 3356015 / 18-24 MKH3 G 06 G 15/332

Abtoph: í> .A.MaKCHMOB, B.B.CyMapoKOB η Β.Φ.Ηβρβηοβ 3aBBHT & ni>: aBTopw

HasBaHHe H3ofipeTeHHH: YCTPOftCTBO ΛΠΒ KHCTPOrO ΠΡΕ0ΒΡΑ30ΒΑΗΗΒ ΦΥΡΒΕ

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He, aocTaTKOM H3secTHoro ycToTBaBbHeTCH Majioe 6bicTpofleňcTBHe,

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Bjiok ynpaBJiHH coctoht H3 sneMeHTOB H 25 h 26, HeTbipexpa3pHAHoro peracTpa27 CABHra, Tpexpa3pHAHoro cneTHHKa 28 h Sjioxa 29 ποοτοηηηοη naMHTH.

YcT leastcTBo BbinojiHHeT cjieAywiUHe onepauHH (npope »HB3HHe no nacTOTe):

ReAi + 1 = ReA i + ReB; ImA, ·. 1 = ImA, + ImB; ReBi + 1 - ReW. (ReA · - ReB,) - ImW, (imA. - ReB.) + ReW .1 1 1 1 (imA j - ImB rAe A. - nepBoe BxoAHoe KOMnjieKCHoe hhcjio; - BTopoe βχοαηοθ KOMiuieKCHoe hhcjio; w - Ββκτορ noBopoTa. ycTpoĚCTBO paSoTaeT cjieAyromHM o6pa3OM. b HCXOAHOM COCTOHHHH perHCTpbl 9 "12 ΠρθΗ3ΒΘΑβΗΗή OĎHyJieHbI. KoMMyTaTOp 13HanpaBJíneT b perHCTpbl 1 h 2 BenHHHHy Res., b peracrpM 3 h 4 BejniHHHy IMA;, CyMMHpyncb C 9-12 HyneBHM coAepxHMbiM perHCTpOB Ha cyMMaTopax 5-8, 3th βθληηηημ6e3 η3μθηθηηη 3anncbiBawTCH b perHCTpbl 9-12. Ha one hundred meters nepBbiň τβκτ PaSoRi ycTpoň-CTAB 3aKOHneH. KoMMyTaTop 13 HanpaejiHeT b perHCTpbl 1 h 2 BxoAHyw pejiHHHHy REB; ab perHCTpbl 3h 4 bxoahvw BejiHHHHy ImBj, h Ha cyMMaTopax 5-8 o6pa3y »TCH cne-Aywmne BejiHHHHbi: Ha cyMMaTope 5 - (ReA ·, + ReB;), Ha cyMMaTope 6 - (ReA; - 253269 3 - ReBj); ImA. + ImB ;, Ha cyMaTope 8 - (imA; - ImB /. Benn-HHHbt C BHXOAOB CyMMaTOpOB 3anHCHBaWTCH B ρβΓΗΟΤρ 9 "1 2. C BblXOfta perncTpoB 9 H11 BejiHHHHM ReA ^ · h IMB; ,,, paBHue οοοτΒβτοτΒβΗΗο (ReA; + ReB;) h (ImA ·, ++ ImB j), wepe3 KoMMyTaTop 13 nonawTCH Ha Bwxo, qM 23h 24 ycTtvcTBa εοοτΒβτετ-B6HHO · Ha 3TOM BTOpoft THKT paROTbl yCT at leastBBa 3aKOHH6H.

CoMMyTaTop Γ3 pa B T T ο ο ο ο ο ΐΗΜ b b ix ix ix ix ix ix ix ix ix ix ix ix ix ix ix ix h h h h h b b b b b b b b b b b b Ha stomTpeTHň τβκτ paRoTti ycTkolikcTBa 3aKOHneH. 3aTeM 0J1OK ynpaBJiHHHHHHtT onepaiiHio yMHomeHHH, ofLHOBpeMeHHo (JrapMHpyHHa perHCTpax 9-12 werbipe BeJiHHHHw; [ReW; - ReB;)}; ;)} - [LMW · (IMA, - IMB;)]. YMHoxeHHe AHHTCHCTOfl &amp; KO tsktob, ckojibko paapnAOB perncTpoB ΒβκτοροΒ noBOpoTa (b HanSojiee pac-πρροτρβΗβΗΗΟΜ cjiyuae BoceMb pa3pnAOB) 0 RacTHHHbie npoH3Bep, ehhh tfcopMHpyioTCHnyTeM cflBHroB b perHCTpax 1- 4h 3anHCWBawTCH b perHCTpw 9-12, ecjiH οοοτΒβτετ-bymnmft pa3pafl perHCTpa BexTopa noBopoTa paeeH eAHHHue.

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Bjiok 14 ynpaBJiHHH pafioree cjieaywmHM oSpaaoM. B HCXO4HOM coctohhhh Ha Βχο, η perHCTpa 27 c of [bhrami noflaeTCH jiornnecKaH eflHHH-ua, cneTHHK 28 τβκτοΒ yMHOxeHHH c6poraeH b Hyjib Ha Bcex Bbixoflax 6noKa 29 amino-CTOHHHoň πημητη JioruHecKue HyjiH h cjieflOBaTejibHo, He HHHHHpyeTca hh oflHa mhkpo-onepanHH .

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flHHTenbHocTb Bcero HHKJia npeo6pa30BaHHH b npe / viaraeMOM ycTteencTBe npw HajiH HHH 8-ρβ3ρΗΛΗΟΓΟ VMHOKeHHH COCTaBJIHeT 11 T3KTOB BMeCTO 34 ΤβΚΤΟΒ B H3BeC.THOMycT at least cTBe. B cnyqae ΗΜ ο »π M M M M M H H H H H H H H H H H H H H H H H H H H

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Claims (2)

6 OBJECT OF THE INVENTION A rapid Eourier transform apparatus comprising four input registers, a first summer, four product registers, two rotation vector registers, a commutator and a control block, wherein the inputs of the rotation vector registers represent inputs of the real and imaginary parts of the rotation vector in the device the outputs of the product registers are connected to the first group of commutator information inputs, the first control block output to the vector register shift control inputs, the second control block output to the input register control inputs, the third control block output to the commutator control input characterized in that the second, third and fourth summators are connected to accelerate the operation of the device, while the first output of the commutator is connected to the information inputs of the first and second input registers, the second output of the commutator is connected to the information inputs of the third and fourth registers the input registers, the outputs of the input registers are connected to the first information inputs of the respective summators, the outputs of the summators to the information inputs of the respective product registers, the outputs of the product registers to the second information inputs of the respective summators, the serial outputs of the registers of the rotation vector are connected to the respective control inputs of the control block, the fourth output of the control block is connected to the input of the summator operation mode input, the fifth output of the control block to the inputs to control the record of the first and third product registers, the sixth output of the control block to the inputs for the control of the second and fourth product registers, the second and third group of the commutator information inputs represent the input of the first and the second complex device operand, the third and fourth commutator outputs represent the complex result of the device. 253269 7 2. The apparatus of claim 1, wherein the control block comprises a four-row shift register, a three-row counter, two product members, and a memory block, wherein the first inputs of the product members are connected to the device clock input, the output of the first product a member to a shift register control input, a shift register fourth order register to input its first order, a shift register third order output to a second input of a second product member, a second product member output to a counter input, a "counter overflow" output is connected to a second input of the first product member, the control inputs of the control block are connected to the first group of permanent memory block address inputs and the block outputs permanent memory represent the control block outputs · 253269