JP2955734B2 - Charge signal halving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used not only as a component of an AD converter or a DA converter using a charge transfer element or the like, but also as a charge signal bisecting device widely used for signal processing using charges as a medium. It concerns the device.

[0002]

2. Description of the Related Art Conventionally, an operation of bisecting a charge signal itself is generally a method in which charges are charged in a state in which capacitive elements having the same capacitance are connected in parallel and divided by a switching device. When the precision of each capacitive element is insufficient, the precision of division decreases in proportion to the precision of the element itself, and a sufficiently high precision bisecting device is realized while being compatible with miniaturization of a circuit. It was extremely difficult.

[0003] The above-mentioned conventional technical problems are unavoidable as long as it is assumed that the accuracy required in one operation is mainly secured in the operation of bisecting the charge signal.

[0004]

SUMMARY OF THE INVENTION The present application solves the above-mentioned problems of accuracy in the prior art at once, and
An object of the present invention is to provide a charge signal bisecting apparatus that can execute a bisecting operation with extremely high precision by repeatedly using it in series even if the bisecting apparatus does not have sufficient accuracy.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above viewpoints, and has as its main requirements first and second charge signals for dividing one input charge signal into approximately two equal parts. An equalizer, at least one routing device and at least one charge signal summing device,
One input charge signal is roughly divided into two output charge signals by a first charge signal dividing device, and one output charge signal is divided into two charge signals by a second charge signal dividing device. , The other output charge signal is independently subdivided into two charge signals, and the routing device is used to divide one of the output charge signals into one subdivided charge signal and the other output charge signal into one subdivided charge signal. And the other subdivided charge signal of the one output charge signal and the other subdivided charge signal of the other output charge signal are paired, respectively, and added by a charge signal adding device to produce two composite outputs. As an embodiment, which is configured to obtain a charge signal, and as an accompanying embodiment, the charge signal bisecting device further includes a mechanism including the second charge signal equalizing device, a routing device, and a charge signal adding device. A charge signal halving device configured to connect at least one of them in series and to use the combined output charge signal of each mechanism as the input charge signal of the next stage, and further, to divide one input charge signal by approximately two An analog memory group including a charge signal dividing device and a charge transfer element, at least one of which is an analog shift register having a charge signal adding function and an output signal of the charge signal dividing device. One charge transfer path for transferring at least one of the charge signals to the charge signal dividing device via the last analog memory in the analog memory group, and the charge transfer path from the last analog memory to the analog memory group. And another charge transfer path for transferring the charge signal to the first analog memory, and a charge signal bisecting device for processing the charge signal in the following order. 1. The input charge signal is bisected using the charge signal equalizing device into two charge signals. Processing 2. One of the two charge signals is saved to the analog shift register. Processing 3. The other charge signal of the two charge signals is again bisected using the charge signal equalizing device to obtain a subdivided charge signal.
Processing 4. Transferring the subdivided charge signals to the analog shift register respectively, and transferring the charge signals already saved on the analog shift register to the charge signal equalizing device again via the one charge transfer path, Divide into two to obtain a subdivided charge signal. Processing 5. The transfer of the re-divided charge signal is performed by the shift of the analog shift register and the transfer function of the another charge transfer path, and the re-divided charge signal is sequentially transferred onto the analog shift register to be added in the charge area. Performs the function and forms two new charge signals. Processing 6.
The newly formed charge signal is output by transfer from the analog shift register. Further, in the charge signal bisecting device, after transferring one of the two outputs of the process 5 to the charge signal equalizing device using the one charge transfer path, the process 3 proceeds to the process 5 It is an object of the present invention to provide a charge signal bisecting device that executes the above-described process 6 after at least once performing the above-described processes to form an output signal.

[0006]

Operation and embodiments will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a basic configuration of one embodiment of the present invention. In the figure, D1 indicates a first charge signal equalizing device, D2 indicates a second charge signal equalizing device, A1 and A2 indicate charge signal adding devices, and R1 and R2 indicate charge signal routing devices, respectively. . In the figure, an input charge signal Qi
Is first transferred to a first charge signal equalizing device D1 to be approximately equally divided into two output charge signals Q1 and Q2, and each of the output charge signals Q1 and Q2 is further divided by a second charge signal equalizing device D2. Into two charge signals Q11 and Q12, and the other output charge signal Q2 into two charge signals Q21 and Q22, respectively.

The first and second charge signal equalizing devices D
1 and D2 ideally divide the input charge equally in 1: 1. However, in reality, due to a manufacturing error or the like,
Exact bisecting is not possible.

Here, the first charge signal equalizing device D1
At (1 + a) :( 1-a), the second
Charge division ratio in the charge signal equalizing device D2 of (1+
b): Assuming (1-b), four charge signals Q1
1, Q12, Q21, and Q22 are theoretically expressed by equations 1) -4). Q11 = Qi (1 + a) (1 + b) / 4... 1) Q12 = Qi (1 + a) (1-b) / 4... 2) Q21 = Qi (1-a) (1 + b) / 4... 3) Q22 = Qi (1-a) (1-b) / 4... 4)

The above four charge signals Q11, Q12, Q
21 and Q22 are routed by the routing devices R1 and R2 and sequentially added by the adding devices A1 and A2.
That is, Q11 + Q22 and Q12 + Q21. Assuming that the combined output charge signals resulting from the respective additions are Q01 and Q02, they are as shown in equations 5) and 6). Q01 = Qi (1 + ab) / 2 5) Q02 = Qi (1-ab) / 2 6)

That is, as a result of this processing, the overall charge division ratio becomes (1 + ab) :( 1−ab).
Assuming that b = 0.1, ab = 0.01, which is an improvement over the original division ratio of the configured charge signal equalizing apparatus.

FIG. 2 shows an example in which a third charge signal equalizing device {charge division ratio (1 + c) :( 1-c)} is installed in the configuration shown in FIG. When the processes of the above equations 1) to 6) are repeated by the equalizing device, the output electric charge amounts to the equations 7) to 8), and it can be seen that the division accuracy is further improved. Q01 ′ = Qi (1 + abc) / 2 (7) Q02 ′ = Qi (1-abc) / 2 (8)

FIG. 3 shows an example of a structure in which a signal feedback path is provided in the example shown in FIGS. In the case of this example, the routing device and the adding means are arranged in a ring-shaped analog memory group S.
1-S3 is equivalently realized, the routing is a shift operation of the memory group, and the addition processing is performed in the memories S1 and S2.
Instead, data is stored in

FIG. 4 shows the general operation timing of the above-mentioned device. In the figure, the input charge is first transferred to the charge signal equalizing device D at the left end of the drawing. Thereafter, the charge signal equalizing device D is divided into two small parts d1 and d2 by a dividing operation, and only the small part d2 is stored in the memory S2.
And the contents of the memory S2 are held in the memory S3 by a shift operation.

During this time, the division operation of the charge signal equalizing device D is released, the signal of the small part d1 is redistributed to the charge signal equalization device D, and the preparation for the second division operation is completed (timing).

The second-order division operation is composed of operations in two sections indicated by P1 and P2. In the operation of P1, first, the signal remaining in the charge signal equalizing device D is again converted into small portions d1 and d2.
The data are accumulated in the memories S1 and S2, respectively, and the data of the small portion d2 of the primary division result already stored in the memory S3 is transferred to the charge signal equalizing device D again by the shift operation.

In the operation of P2, the contents of the charge signal dividing device D are again divided into small parts d1 and d2, and the small part d2 is stored in the memory S2, and the small part d is separated by one more shift operation.
1 is added to the memory S1 to form an output (triangle in the figure), and at the same time, two shift operations are executed in preparation for the next division operation.

The operations of P1 and P2 are repeated the required number of times to improve the division accuracy. In the last division operation, four shift operations shown at the right end of the figure are executed from the timing of the triangle mark, as indicated by T1 and T2. At the timing, two division results are output to the memory S4.

In this case, since the same device is multiplexed and used for the charge signal equalizing device, the error due to the division is constant and a
= B = c = a0, and the output charge amount when the second charge signal equalization processing P is generally repeated N times is expressed by the equation 9) -10). Q01 (N) = Qi (1 + a0 ^{(N + 1)} ) / 2 9) Q02 (N) = Qi (1-a0 ^{(N + 1)} ) / 2 10

In this example, the number of times the feedback path is used can be freely selected in operation, so that there is a feature that the feedback path can be adjusted by software according to required accuracy.

Table 1 shows the relationship between the number of secondary divisions and the progress of the division ratio when a0 = 0.2 in the example of FIG. As can be seen from the table, 20
Even with a poor charge signal equalizing device having a dividing error of as much as%, the error can be reduced to a sufficiently practical accuracy by repeating the division several times.

The results of improving the accuracy of the division ratio as shown in FIGS. 1 to 3 can be expressed as (1 + a ') :( 1-a'). If this is regarded as a new charge signal equalizing device, It is also possible to realize a bisection device with arbitrary precision by induction.

That is, taking the configuration shown in FIG. 3 as an example, based on the general operation timing chart shown in FIG. 4, the charge amount 1 is input from IN at the timing number 1 and the division ratio (6: 4) If the process of generating high-precision outputs (a, b) close to (5: 5) using the charge signal equalizing device D is expressed by the contents of each analog register, the progress is as shown in FIG. In this case, the change in the state indicated by the numeral in the square frame in FIG. 5 corresponds to that at the timing in FIG.

The one-time bisecting process is a combination of the partial processes αβγ shown in FIG. 4 in the order of γααα · β, and the number of times the process of α is executed is theoretically arbitrary. Accuracy can be improved.

[0024]

As is apparent from the above description, according to the present invention, a device for accurately dividing a charge signal into two can be economically realized even on a fine structure such as an integrated circuit.

As a result, the present invention can be applied to a wide range of signal processing devices using a charge signal as a medium, such as an AD converter for converting a charge signal into a digital signal and a DA converter for converting a digital signal into an analog signal based on a charge amount. Things.

[0026]

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a basic configuration of a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a basic configuration of a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a basic configuration of a third embodiment of the present invention.

FIG. 4 is a chart showing general operation timings of a third embodiment of the present invention.

FIG. 5 is a development explanatory diagram in which the third embodiment of the present invention is developed at general operation timing.

[Explanation of symbols]

 D1, D2 Charge signal equalizer A1, A2 Charge signal adder R1, R2 Charge signal routing device Qi Input charge signal Q1, Q2 Output charge signal S1, S2, S3 Analog memory group d1, d2 Small part P1, P2 Section

Claims (4)

(57) [Claims] And 1. A first and second charge signal equal device D1, D2 of dividing two substantially like the one of the input charge signal Qi, small
At least one routing device Ri and at least one charge signal adding device Ai, and one input charge signal Qi is substantially equal to two output charge signals Q1 and Q2 by the first charge signal dividing device D1. The output signal Q1 is divided into two charge signals Q11 and Q12 by the second charge signal equalizing device D2, and the other output charge signal Q
2 is independently divided into two charge signals Q21 and Q22, respectively, and one of the output charge signal Q1 and the other output charge signal Q2 is divided by the routing device Ri. charge signal Q22, and the other subdivision charge signal Q21 of the the other subdivision charge signal Q12 of one of the output charge signal Q1 the other output charge signal Q2 respectively a pair, by their charge signal summing device Ai Add the two combined output charge signals Q
01, Q02 charge signal bisecting apparatus characterized by being configured to so that give. 2. The charge signal halving device according to claim 1 ,
Further, the second charge signal equalizing device D2 and the routine
At least one or more mechanisms M composed of the charging device Ri and the charge signal adding device Ai are connected in series.
The charge signal bisecting device is configured so that the combined output charge signals Q01, Q02,. 3. An input charge signal Qi is approximately bisected.
A charge signal equalizing device D and analog memory groups S1, S2,
S3, at least one of which is a charge signal
An analog shift register having an arithmetic function, and two charge signals which are output signals of the charge signal dividing device D.
At least one of the signals Q1 and Q2 is the analog memory
The last analog memory S3 of the groups S1, S2, S3
One charge transferred to the charge signal equalizing device D via
Transfer path 1 and the analog memory from the last analog memory S3
Most significant analog memory of Molly group S1, S2, S3
Structure from a different charge transfer path 2 which for transferring charge signals to S1
And performs charge signal processing in the following order:
Charge signal bisecting device. Processing 1. Input charge signal Qi
Is divided into two equal parts by using the charge signal
The load signals are Q1 and Q2. Processing 2. Two charge signals Q
1, Q2, the charge signal Q2
Evacuate in the Vista. Processing 3. Two charge signals Q1, Q
2 using the charge signal equalizing device D
And divide it into two equal parts again to obtain subdivided charge signals Q11 and Q12.
You. Processing 4. The subdivision charge signals Q11 and Q12 are
While transferring the data to the analog shift register.
The electric charge saved on the analog shift register
The signal Q2 is again transmitted through the one charge transfer path 1
Transfer to charge signal equalizer D
Nos. Q21 and Q22. Processing 5. The analog shift
Register shift and transfer function of another charge transfer path 2
The transfer of the subdivision charge signals Q11 and Q12 is thereby performed.
At the same time, the subdivision charge signals Q21 and Q22 are sequentially
Next, by transferring to the analog shift register
Performs the add function in the charge domain and generates two new charge signals
Q'1 = Q11 + Q22; Q'2 = Q12 + Q21
To achieve. Processing 6. The newly formed charge signal Q′1,
Q'2 is transferred from the analog shift register
Power. 4. The charge signal halving device according to claim 3,
And one of the two outputs Q′1 and Q′2 of the process 5 is
The charge signal equalizing device using the one charge transfer path 1
After the transfer to the device D, the processes from the process 3 to the process 5 are performed.
After executing at least once, execute the above process 6 and output
A charge signal halving device that forms a signal.