CS252820B2 - Connection for digital signal processing - Google Patents

Abstract

A digital signal peak correction circuit combines input digital signals with their filtered and normalized representations to produce adjustably corrected digital signals. The digital filter produces relatively higher frequency components of the input digital signals which are adjustably normalized by a digital multiplier in accordance with a multiplication factor. The control circuit produces a multiplication factor of a value determined in accordance with the magnitude of the peak of the high frequency components of the input digital signals in relation to the value of the correcting control signal level.

Description

(54) Digital signal processing connections

The digital signal peak correction circuit combines the input digital signals with their filtered and standardized displays to produce adjustable corrected digital signals. The digital filter produces components of a relatively higher frequency of the input digital signals, which are adjustable by the digital multiplier in accordance with the multiplication factor. The control circuit generates a multiplication factor of a value determined in accordance with the peak size of the high frequency components of the input digital signals relative to the value of the correcting control signal level.

BACKGROUND OF THE INVENTION The present invention relates to a digital signal processing circuit, and more particularly to a peak correction circuit for a digital signal providing a correction adjustable in response to at least a portion of the signal to be corrected. The invention is suitable for processing digital television signals in a television receiver.

Peak correction is a signal processing in which the components of the higher frequency signal are emphasized or suppressed to adjust the overall frequency spectrum of the signals. This is useful where higher frequency signal components are undesirably attenuated by prior signal processing or equipment. For television signals, for example, attenuation of higher frequency luminance signals causes undesirable loss of horizontal detail in the reproduced picture. Such attenuation may be introduced by a radio frequency tuner and amplifiers, intermediate amplifiers or a device separating luminance chrominance signals.

A fixed peak correction arrangement is not appropriate in the television because it cannot respond to changes in the received signals or receiver performance and cannot be set to suit the viewer's preference, which not only varies between viewers, but which may vary for any viewer according to content of the program.

Therefore, it is desirable to provide an adjustable peak correction arrangement that can adjust the degree to which signals are corrected in response to viewer controllable settings and in response to changes in the state of the processed signals. When such a peak correction arrangement is used in television sets, they tend to emphasize the horizontal detail content of the reproduced images. The arrangement of an analog circuit providing such characteristics for television sets with analog signal processing is known.

However, in digital signal processing devices, the digital signal peak correction circuit corrects on signals which are digital numbers representing signal levels rather than directly at the signal levels as such. Thus, digital circuits must be used to produce a digital signal representative of the peak level to derive a multiplication coefficient signal under certain digital signal states and to produce peak corrected digital signals in response to the multiplication coefficient signal.

Known analog peak correction systems use a feedback arrangement including a bandpass filter to adjust the peak correction level. But with digital signal peak correction devices, the ability to weigh digital signals with predictability and accuracy makes it possible to avoid the feedback arrangement and the complexity associated with it. Moreover, the above-mentioned bandpass filter is eliminated.

These disadvantages are eliminated with the digital signal processing circuit according to the invention, which is characterized in that the output of the input first digital circuit is connected via a digital delay circuit to the first input of the output third digital sum circuit and to a digital filter consisting of a shift register connected through the weight circuits and the second digital summation circuit to the first digital subtractor, wherein the digital filter output is connected via a digital multiplier to the second input of the third summation circuit, while a control circuit is connected between the digital filter output and the second digital multiplier input.

The invention achieves a substantial improvement in the processing of digital signals, particularly in television receivers, by enabling adjustable signal peak correction.

Fig. 1 shows a block diagram of the circuit, Figures 2, 4 and 5 are graphs of transmission characteristics for understanding the circuit of Figures 1 and 3, 6, 7, 8 9, 10 and 10 schematically, at least in part in the form of a block diagram, of the wiring part according to FIG. 1.

In the drawings, the strong arrows represent paths for multi-bit parallel digital signals and the line arrows represent paths for single-bit or serial digital signals, for clock signals, or for control signals. An input ring to a logic element indicates that such an element responds to an inverted signal attached to such input.

Giant. 1 shows a portion of a digital signal processing section of a television in which luminance signals are processed digitally. Although the invention is generally applicable, it is described herein under _both digital _and luminance signal processor conditions in a television section, since the digital peak correction operation of the signal controllable in response to adjustable digital peak correction signals is preferably performed here first.

The input first digital summation circuit 10 is a source of broadband digital luminance signals Y _w , which adds vertical detail information included in comb-filtered digital color signals C _c to comb-filtered digital luminance signals Y _c . The magnitude of the digital luminance signals Y, as a function of frequency f, is shown in FIG. 2, where the broadband digital luminance signal Y is indicated accordingly.

The digital filter 12 in Fig. 1 receives broadband digital brightness signals Y ^ and produces low pass filtered digital brightness signals Y ^ including relatively lower frequency components of broadband digital brightness signals Y ^ and produces bandpass filtered digital brightness signals Υ _β , including their relatively higher frequency components. The low-pass filtered digital luminance signals Y ^ and the band-pass filtered digital luminance signals Υ _β are preferably roughly complementary in size to the frequency spectrum as shown by the curves a Υ _β in Figure 2.

An embodiment of the digital filter 12 shown in Fig. 3 comprises a multi-stage shift register 14 which produces delayed replicas of the wideband digital luminance signals Y _W at its various output taps in response to an input of wideband digital luminance signal Y ^, and the clock signal not shown. The delayed digital luminance signals generated at the shifts of the shift register 14 are weighted by digital weight circuits W1, W2 and W3, which are, for example, digital multipliers. The weight coefficient values of the weight circuits W1, W2 and W3 determine the frequency response of the digital filter 12, as is known to those skilled in the art.

The second digital summation circuit 16 adds the weighted delayed luminance signals to form the band-pass filtered digital luminance signals Υ _β . luminance signals Υ _β to create low-pass filtered digital luminance signals Y ^. In this way, the band-pass filtered digital luminance signals Υ _β and the low-pass filtered digital luminance signals are essentially complementary.

The digital low noise suppression circuit 20 of the digital signals of FIG. 1 produces digital brightness signals Y _BC and suppressed low impedance noise, wherein the low impedance noise is suppressed, for example, in response to low pass filtered digital brightness signals Y ^. When the low pass filter levels of filtered digital luminance signals Y ^ are relatively high, corresponding to a clear image, the low-amplitude noise reduction circuit 20 of the digital signals exhibits a relatively low-value suppression threshold for generating digital luminance signals Υ _{β (} ^ with low-amplitude noise suppressed) only the bandpass filter size of the filtered digital luminance signals Υ _β exceeds the size of the first threshold suppression level.When the low pass filter levels of the filtered digital luminance signals Y ^ are relatively low, corresponding to a dark image, the digital circuit 20 pushes the low amplitude noise of the digital signals. relatively high value suppression, and digital luminance signals Y _{BC are} produced with low-noise noise suppression only when their size exceeds the size of the second threshold suppression levels.

The low amplitude summation suppressor circuit 20 of the digital signals therefore suppresses more in darker scenes than in lighter scenes. This is desirable because relatively low-level, higher-frequency signals, often associated with unwanted noise signals, tend to produce easily perceived undesirable light spots on dark scenes removed by this circuit.

The digital multiplier 30 multiplies the digital luminance signals Y _pc with suppressed low amplitude noise received from the low amplitude noise suppression circuit 20 of the digital signals. This multiplication is controlled in response to a multiplication coefficient MC formed by the digital control circuit 40, whereby the digital multiplier 30 produces the multiplied digital brightness signals Y ^ having the characteristics shown in Fig. 2 by a group of curves designated Y _M. For example, the digital multiplier 30 is an 8 x 8-bit multiplier, but it may be a relatively simple shifting and adding multiplier where relatively few values of the multiplication factor MC will suffice.

The digital control circuit 40 creates a multiplier coefficient MC adjustable in response to the bandpass filtered filtered luminance signals Υ _β and a viewer adjustable MPC manual peak correction control signal. The multiplication factor MC is controlled in response to peak variables Υ βΚ0 _{bypass the} filtered digital luminance signals Υ _β in relation to the magnitude of the manual peak correction MPC control signal in accordance with a predetermined characteristic, such as that shown in Figure 4. peak and the Υ βρκ _{bandwidth of} filtered digital luminance signals Yg less than the manual peak correction MPC control signal, indicating a relatively lower high-frequency luminance content, generating a multiplier coefficient MC = 1 represented by the first line 60 and introducing a maximum correction • maximum emphasis is given to any content of high-frequency signals. When the peak magnitude bandpass filtered digital luminance signals Y _{R is} greater than twice the control signal MPC Manual correction peaks, indicating a relatively higher content of high frequency luminance produces the multiplier MC = 0, represented by the third line 64, does not introduce substantially no correction, that is, no emphasis is placed on the content of the radio frequency signals. Among these levels of the peak quantity Υ _{βρκ by the} bandpass filter of filtered digital luminance signals Υ _β , the multiplying factor MC is controlled between the unit and the zero represented by the second line 62 in accordance with the Y _p / MPC ratio. It should be noted that the first line 60 is in practice a staircase characteristic in which the number of steps is determined by the number of digital levels that the multiplier MC can acquire, which is limited by the number of bits of the digital signal of the multiplier MC.

In Fig. 1, broadband digital luminance signals Y ' are delayed in time by the digital delay circuit 22, which generates delayed digital luminance signals Y '. For example, the digital delay circuit 22 is a shift register having a number of degrees selected to provide a time delay substantially equal to that occurring when generating multiple digital luminance signals Y ^ in response to broadband digital luminance signals Y ^ across the signal path formed by the digital filter. 12, a 20 circuit for suppressing low amplitude noise of digital signals and a digital multiplier 30.

The third digital summing circuit 24 combines the delayed wideband digital luminance signal Y and _p multiplied digital luminance signal Y _{j in} a controlled nízkoampJitudového suppression of noise and generate the luminance signal Y ,. with tip correction. Giant. 2 further shows a curve groups size for frequency digital luminance signals Y _P corrected peaks, which are the sums of the relevant characteristics from characteristics of the multiplied digital luminance signal Y ^, and characteristics of the wideband digital luminance signals Y _are., Which represents the delayed digital luminance signal Y _p ,

The overall transmission function of the peak correction circuit in Fig. 1 may be expressed by the equation

Y _p = 1 + H (12). H (20). MC 1 Y _w (1) wherein H (12) is the transmission function of the digital filter 12, H (20) is the transmission function of the low-amplitude noise suppression circuit of digital signals and wherein the digital circuit 22 is selected as described above. If the reasoning is limited to that portion Yg of the broadband digital luminance signals Y1 that lies within the bandwidth of the digital filter 12, that is, the absolute value of H (12) is approximately equal to 1, and if the low noise suppression threshold the low-amplitude noise of digital signals is low enough to be neglected, that is, the absolute value of H (20) is approximately equal to 1, then the transfer function becomes

Y _p = El + Mc] y _b (1)

Since the ranges for example MC are between 0 and 1, Yp will be in the range between 1x to 2x Yg.

For example, consider that the digital luminance signals Y 'have digital values equivalent to decimal numbers between zero and about 80, as shown in Fig. 5, and that the manual peak correction MPC control signal is set to a level equivalent to decimal number 20. For Y values less than 20, the control circuit 40 forms a multiplication coefficient MC-1 in accordance with D with the first line 60 in FIG. 4 and Y '= 2Yg in accordance with equation (2). This range is shown as the fourth line 70 in FIG. 5. As the value of Yg toward 40 increases, the control circuit 40 reduces the peak correction in accordance with the second line 62 in FIG. 4 to form Y 'having the values shown in the fifth For values Yg greater than 40, the control circuit 40 produces a multiplication coefficient MC = 0 in accordance with the third line 64 in FIG. 4 so that Y 'having values such as shown in the sixth line 74 in FIG. ovr. 5.

Giant. 6 illustrates an exemplary embodiment of a digital control circuit 60 that produces a multiplier MC having the characteristics given by the first line 60, the second line 62 and the third line 64 described above with respect to FIGS. 1 and 4. The digital peak detector 42 detects the peak value Υ _βρκ bypass filtered digital luminance signals Yg. The digital game gain detector 44 responds to the peak value Υ _βρκ and the MPC control signal of the manual peak correction and causes the memory. The digital coefficient 48 generates the multiplication coefficients MC corresponding to the first line 60 and the third line 64 with the constant value in FIG. 4.

The digital gain ratio detector 46 responds to the peak value Υ _βρκ and the manual peak correction MPC control signal and causes the digital coefficient memory 48 to produce the multiplication coefficients MC corresponding to the inclined second line 62 in Fig. 4. Digital peak detector 42, digital gross gain detector 44 , the digital gain ratio detector 46 and the digital coefficient memory 48 are described in more detail below with reference to FIGS. 7 to 10.

Giant. 7 illustrates an exemplary embodiment of a digital peak detector 42 in which peak quantity Υ _βρκ is _detected by a calculation stored in bidirectional counter 424. The first digital comparator 420 generates an output signal that opens the first product circuit 422 provided the bandwidth size of the filtered digital luminance signal Β _β exceeds Peak Y _BPH · Otherwise, the first digital comparator

420 produces an output signal that closes the first product circuit 422. Opening the first product circuit 422 causes the clock signal 4f to be applied to the input U of the forward bidirectional counter 424 and causes an increment therein. The clock signal 4f _gc has a relatively high frequency, for example four times that of the subcarrier color signal f, such that the bidirectional counter 424 registers increments at a relatively high rate. The clock signal f ^ is applied to the reverse counting input D of the bidirectional counter 424 and causes an increase in the calculation therein. The clock signal f has a relatively low frequency, for example, the frequency of the TV horizontal sync pulses, so that the bidirectional counter 424 records decreases at a relatively low rate. Thus, the digital peak detector 42 produces a peak value signal Y _{Bp 4} which may increase rapidly but which decreases slowly.

Giant. 8 illustrates an exemplary embodiment of a digital gain detector 44 that cooperates with a digital coefficient memory 48 for generating zero and unit multiplication coefficients MC corresponding to the third line 64 and the first line 60 of FIG. 4, respectively. ^ and the manual peak correction MPC control signal and produces an adjustment signal S when the manual peak correction MPC control signal exceeds the peak quantity ^γ βρ ^ / i.e. for condition (Y ^ p ^ / MPC) 1. The generation of the set signal S indicates that it is required multiplier MC = 1.

The digital multiplier unit 42 increases the magnitude of the manual peak correction control signal twice, and outputs the third digital comparator 444. The third digital comparator 444 receives the resulting dual manual peak correction MPC signal and the peak value signal and produces a reset signal R when the peak magnitude Y__. ..

Dr j 'BPK exceeds twice the MPC control signal, i.e., for a state (Y ^ p / MPC)> 2. The generation of the reset signal R indicates that a multiplication coefficient MC = Q is required. Neither the reset signal R nor the set-up signal S is generated for a state 2> (Y ^ p ^ / MPC) 1 for which a value of multiplying coefficient MC between 0 to 1.

Giant. 9 illustrates an exemplary embodiment of a digital coefficient memory 48 that creates a multiplication coefficient MC. The eight divider digital counter 480 generates and stores a number that becomes a multiplication coefficient MC after it is transferred to the digital lock register 482 and stored there. Applying a set-up signal S from the digital gain detector 44 generates a multiplier coefficient MC < way. The setting signal S is applied to the setting input S_r of the eight-digit digital counter 480 for initializing and holding the number stored here at its maximum value, that is, all its bits are 1. The setting signal S is also applied via the second logic sum circuit 68JS to the digital interlock. a circuit 482 for storing a number consisting of only 1 of the eight-digit digital counter 480, thereby creating a multiplication coefficient MC-1,

Applying a reset signal R from the digital gain detector 44 produces a multiplication coefficient MC = 0 as follows. The reset signal R is applied via the first logic sum circuit 484 to the reset input RI of the eight-digit digital counter 480 to initiate and hold the number stored therein to its minimum value, i.e. all bits are zeros. The reset signal R is also applied via the second logic sum circuit 496 to the digital circuit 482 and the number consisting of 0 alone is stored in the memory of the eight digital divider 480, thereby producing a multiplication coefficient MC = 0.

The functions of the opening signal EN, the output pulse UP and the stop transmission signal T in relation to the digital coefficient memory 48 are described below with respect to the digital gain ratio detector 46. Thus, the digital peak detector 42, the digital gross gain detector 44, and the digital coefficient memory 48 cooperate to produce two fixed values of the multiplication coefficient MC corresponding to the two non-overlapping ranges of the ratio Y _{n T} / MPC.

Child ——

Giant. 10 depicts an exemplary embodiment of a digital gain ratio detector 46 that cooperates with a digital coefficient memory 48 to produce a multiplication coefficient MC value between 0 and 1. Assume condition 2> (Y _{BI> K} "MPC)> 1 and the signal is applied to the reset input RI of the first bistable flip-flop 462, which is thereby reset and produces an output signal for the first control switch 464 and the second control switch 466 to be in the positions shown, then the first control switch 464 applies the signal to the second digital reader 468 and the second control switch 466 provides a manual peak correction control signal MPC thereto. The digital second subtractor 468 generates a PS = PS-size difference signal at its output which is blocked on it in response to a 4f _sc clock signal _<

Ί

Since condition 2> (Y ^ p ^ / MPC)> 1 is satisfied, the difference signal PS is greater than 0 and causes the output signal to be generated by the fourth digital comparator 470, i.e. condition (Υ _ρΓΚ ~ ΜΡΟ> 0). The output signal from the fourth digital comparator 470 is to open the third product circuit 474 to pass the clock signal 4f _sc to produce an output pulse UP The output signal from the fourth digital comparator 470 is applied to the setting input S1 of the first bistable flip-flop 462. causes the first control switch 464 and the second control switch 466 to transmit, so that the difference signal PS from the output of the second digital reader 468 is applied to one of its inputs and the increment level MPC / 8 signal is applied to its second input. is the level of the manual peak correction MPC control signal divided by eight, while the division is easily achieved by moving bits connection control signal MPC Manual correction tips to increase the level of bit positions MPC / 8 bit having a lower weight.

The second digital subtractor 468 now generates a differential PS signal having a PS value of (MPY / 8) / which, if greater than 0, causes the fourth digital comparator DJSr-470 to continue opening of the third product circuit 474 thereby producing a second output pulse UP. The sequence of subtracting the increment level MPC / 8 from the most recent differential signal PS and generating the output pulse UP is repeated until the new differential signal PS becomes less than 0 or equal to 0.

The fifth digital comparator 472 produces an output signal when the difference signal PS is less than or equal to 0, which output signal is supplied as a stop / transmit signal T. The stop / transmit signal T is applied to reset the first bistable flip-flop 462 and thereby reverse. the first control switch 464 and the second control switch 466, such that the digital gain ratio detector 46 repeats the sequence just described.

The termination / transmission signal T is reduced at the beginning of the sequence of the digital gain ratio detector 46 only when the fifth digital comparator 472 does not detect, i.e., only when intermediate values of the multiplication factor MC are to be generated. It is noted that the set-up signal S is low to open the second product circuit 460. The decreasing terminating transfer signal T is applied in an inverted sense and adjusts the set-up input SI of the second bistable flip-flop 476, which is thereby set to produce the set-up output signal the coincidence on the second product circuit ktex generates an opening signal

EN. Clock signal. 4 'is applied to reset the reset input RI of the second bistable flip-flop 4/6, which is thereby reset and terminates the opening signal EN, which is therefore in this jk-ouk; high signal. As described below, the opening signal EN resets if the dig.

Paměf. The digital coefficient of FIG. 9 creates a multiplication coefficient MC in response to the operation of the digital gain detector 46 in the following manner. An instantaneous opening signal EN is applied over the first logic total circuit 484 and resets the reset input

RI and reset the digital divider 480 to an initial number consisting of all zeros. Thereafter, the UP pulses from the gain gain digital detector 46 are applied to the clock input Ck of the eight divider digital counter 480 and increment the stored number there by one number for each occurrence of the output pulse, thereby counting the desired multiplication coefficient value. eru u uk =.

The termination / transmission signal T generated by the digital gain ratio detector 46 at the end of its alignment sequence is applied through the second logic sum circuit 496 to transmit and store the number stored in the eight-digit digital counter 480 to the digital lock register 482 as a multiplication factor MC. Thus, the digital peak detector 42, the digital gain gain detector 44, the digital gain ratio detector 46, and the digital coefficient memory 43 cooperate to form intermediate values of the multiplication coefficient MCc according to the intermediate range of the Y / MPC ratio values.

Various modifications of the invention falling within the scope of the definition of the invention are contemplated. For example, an arrangement may be required to reduce the correction of the peaks of broadband digital Y signals. The peak correction reduction refers to a situation where some of the peak correction peak curves Y _p in Fig. 2 are below the broadband digital luminance waveform V '. In the arrangement of FIG. 1, the peak correction reduction is achieved by the negative values of the multiplication coefficient MC generated by the control circuit 40 for certain values of the manual peak correction PMC control signal. For this purpose, the digital counter 480 in FIG. 9 is a bi-directional counter open for reverse counting for certain values of the multiplication coefficient MC. A reduction in peak correction is also provided when the arrangement in Fig. 1 is modified such that the non-digital delay circuit 22 is applied to the low pass filtered digital luminance signals Y _L instead of the broadband digits luminance signals Y 1, in which case only positive multiplier values are required. coefficient MC containing values greater than 1. Alternatively, the digital multiplier 30 may include a weighting to allow multiplication by a factor greater than 1, as in an upshift operation to provide a factor of ₂ N, where N is the number of upshifts.

In addition, digital luminance signals Υ _{β <2} with suppressed low-amplitude noise can be applied to the control circuit 40 instead of the band-pass filtered digital luminance signals Υ _β . Still further, numbers of intermediate values of the multiplication coefficient MC other than the eight values of the multiplication coefficient MC other than the eight values described above can be generated by the embodiments of Figs. 9 and 10 simply by replacing the eight divider digital counter 480 with the divider N and correspondingly the MPC / 8 increment level at the second control switch 466 beyond the MPC / N increment level. As another exemplary embodiment, the digital filter 12 may be a high pass digital filter producing band-pass filtered digital luminance signals Υ _β , since the broadband digital luminance signals Y _w comprise frequency components within a limited frequency range.

Still further, the low amplitude noise suppression circuit 20 of the digital signals can be eliminated since its function is not necessary for the signal peak correction operation.

In addition, the time delay performed by the digital delay circuit 22 can be provided by the shift register 14 within the digital filter 12 by using signals generated at its branch and having suitably long delayed digital brightness signals Y.

Claims (4)

SUBJECT OF THE INVENTION A digital signal processing circuit, characterized in that the output of the input first digital summation circuit (10) is connected via a digital delay circuit (22) to the first input of the output third digital summation circuit (24) and to a digital filter (12). ), comprising a shift register (14) connected via the weight circuits (W1, W3, W3) and a second digital summation circuit (16) to the first digital subtractor (18), wherein the output of the digital filter (12) is via a digital multiplier ( 30) connected to a second input of the third summation circuit (24), while a control circuit (40) is connected between the output of the digital filter (12) and the second input of the digital multiplier (30). Wiring according to claim 1, characterized in that the control circuit (40) comprises a digital gross gain detector (44) connected to the digital peak detector (42), the setting output of the digital gross gain detector (44) being connected to the digital a gain coefficient detector (46) to a digital coefficient memory (48) with an eight divider digital counter (480). 3. The circuit according to claim 2, wherein the digital gross gain detector (44) comprises a first digital comparator (440) and a second digital comparator (444). 4. The circuit according to claim 1, characterized in that a circuit (20) for suppressing the low amplitude noise of the digital signals is connected between the digital filter (12) and the digital multiplier (30).