CS245872B1

CS245872B1 - Single error detection, localization and self-correction, as well as detection of all double-word errors

Info

Publication number: CS245872B1
Application number: CS848269A
Authority: CS
Inventors: Miroslav Vnuk
Original assignee: Miroslav Vnuk
Priority date: 1984-10-31
Filing date: 1984-10-31
Publication date: 1986-10-16
Also published as: CS826984A1

Abstract

Zapojenie na detekciu, lokalizáciu a samočinná opravu jednej chyby a tiež detekciu všetkých dvojchýb v slově představuje návrh zariadenia, ktoré samočinné vykonává kontrolu dát vyčítaných z parna ťových e- lementov, samočinné vykonává opravu všetkých jednochýb, detekuje všetky dvojnásobné chyby. Zapojenie je možné využiť vo všetkých číslicových systémoch s dížkou slova 16 in- formačných bitov, ktoré používajú pamSťo- vé elementy na zapamátanie informácie, najma v mini a mikropočítačoch, kalkulá- toroch, v číslicových telefónnych alebo meracích ústredniach a podobné.One error detection, localization and self-correction, as well as the detection of all double-error in the word, is a device design that automatically checks the data read from the parity links, automatically corrects all single errors, detects all double errors. The connection can be used in all 16 word information bits digital systems that use memory elements to store information, especially in mini and microcomputers, calculators, digital telephone or metering systems, and the like.

Description

245872245872

Vynález sa týká zapojenia na detekciu, lo-kalizáciu a samočinná opravu jednej chy-by a tiež detekciu všetkých dvojchýb v slo-vě zloženom zo 16 informačných bitov a 6bitov kontrolných v samoopravnom binár-nom kóde s minimálnou kódovou vzdiale-nosťou d = 4.BACKGROUND OF THE INVENTION The invention relates to a connection for detecting, locating, and automatically correcting one error, as well as detecting all biases in a compound composed of 16 information bits and 6 bits of control in a self-correcting binary code with a minimum code distance d = 4.

Doteraz používané zapojenia, ktoré umož-ňujú detekciu i opravu jednoehyby a detek-ciu dvojchyby založené na samoopravnombinárnom kóde s minimálnou kódovou vzdia-lenosťou d ~ 4, používajú viacstupňové za-pamatanie dát vyčítaných z pamáťovýchprvkov, čo sposobuje nárast obvodov a tiežčasové zdržanie,Wiring used to date to allow detection and correction of single-bend and double-error detection based on a self-correcting binary code with a minimum code distance of d-4, uses multi-stage memory data retrieved from memory elements, which increases circuitry and also time delays.

Vyššie uvedené nevýhody odstraňuje za-pojenie na detekciu, lokalizáciu a samočin-ná opravu jednej chyby a tiež detekciu všet-kých dvojchýb podlá vynálezu, ktorého pod-statou je to,, že výstup informačných bitovje připojený na vstup registra vstupných bi-tov, ktorého výstup je připojený na vnátor-ná zbernicu, na ktorá je připojený vstupprijímača informačných bitov, ktorého vý-stup je připojený na vstup generátora kon-trolných bitov a'na prvý vstup bloku opra-va jednoehyby, výstup generátora kontrol-ních bitov je připojený na druhý vstup ge-nerátora příznakových bitov a na druhývstup prepínača kontrolných bitov, výstupinformačných bitov z registra riadiacehotestovanie pamáťových elementov památa-jácich si kontrolně bity je připojený na dru-hý vstup prepínača výstupných bitov a naprvý vstup prepínača kontrolných bitov, kto-rého výstup je připojený na vnútorná zber-nicu, na ktorá je připojený tiež prvý vstupgenerátora příznakových bitov, ktorého vý-stup je připojený na vstup generátora signá-lov, jednoehyby a dvojchyby a tiež na, prvývstup dekódera jednoehyby, na ktorého dru-hý vstup je připojený výstup generátora sig-nálov jednoehyby a dvojchyby, výstup dekó-dera jednoehyby je připojený na druhý vstupbloku oprava jednoehyby, ktorého výstupje připojený na vstup registra výstupnýchbitov, ktorého výstup je připojený na vná-torná zbernicu a tiež na prvý vstup prepí-nača výstupných bitov, ktorého výstup jepřipojený na výstup výstupných informač-ných bitov.The above-mentioned drawbacks are eliminated by the device for detecting, locating and self-correcting one error, as well as by detecting all the biases of the invention, the essence of which is that the output of the information bits is connected to the input of the input binary register. the output is connected to an internal bus to which an information bit receiver input is connected, the output of which is connected to the input of the control bit generator and to the first input of the single-bit correction block, the output of the control bit generator is connected to the second input of the flag bit generator and the second bit of the check bit switch output the information bits from the register to control the execution of the memory bits of the control bits is connected to the second input of the output bit switch and the next input of the check bit switch that is output the internal collection to which also the first in the flag bit output generator, whose output is connected to the signal generator input, the single bend and the two faults, and also to the first one decoder decoder input, at which the second signal output of the signal generator and the double error output is connected to the output of the decoder. a single bend correction is connected to the second input, the output of which is connected to the register of output bits, the output of which is connected to the internal bus and also to the first input of the output bits, the output of which is connected to the output of the information bits.

Zapojenie na detekciu, lokalizáciu a sa-močinná opravu jednej chyby a tiež detek-ciu všetkých dvojchýb podlá vynálezu po-užité v zariadeniach, bráni spracovaniuchybnej informácie v případe výskytu jed-nochyby alebo dvojchyby, odpadá nutnosťzastavovat a opakovat výpočet skrz jedno-chybu, pretože táto je samočinné opravova-ná a tiež sá minimálně časové straty i ob-vodová náročnost v danom zapojení.Involvement in detecting, locating, and repairing a single error, as well as detecting all the biases of the invention used in devices, prevents processing of the information in the event of a single error or double error, eliminating the need to stop and repeat the one-mistake calculation because this is self-repairing and also has at least time losses and circuit demands in the circuit.

Zapojenie podl'a vynálezu umožňuje jed-noznačné detekovat jednochybu a dvojchy-bu v spracávanej informácii a samočinnéopravovat jednochybu bez znalosti povod-nej informácie. Jeho funkcia je založená napoužití samoopravného binárneho kódu s minimálnou kódovou vzdialenosťou d = 4.Zapojenie sa používá k ochraně binárnej in-formácie pr.i prenosoch, pri zázname a čí-taní informácie.The connection according to the invention makes it possible to unambiguously detect a single defect and twin buff in the processed information and to self-repair the single defect without knowledge of the flood information. Its function is based on the use of a self-correcting binary code with a minimum code distance of d = 4. The connection is used to protect the binary information for transmissions, recording and reading information.

Zapojenie na detekciu, lokalizáciu a sa-močinná opravu jednej chyby a tiež detek-ciu všetkých dvojchýb pódia vynálezu jeznázorněné blokovou schémou na pripoje-nom výkrese.Involvement for Detection, Localization and Urgent Correction of One Error and also Detection of All Bipods of the Invention Represented by Block Diagram on Attached Drawing.

Zapojenie na detekciu, lokalizáciu a sa-močinná opravu jednej chyby a tiež detek-ciu všetkých dvojchýb v slově s dlžkou 22bitov, kde 16 bitov představuje informačněbity a 6 bitov kontrolně bity v samooprav-nom binárnom kóde s minimálnou kódovouvzdialenosťou d = 4, je upravené tak, ževýstup 1 informačných bitov je připojenýna vstup 11 registra 10 vstupných bitov, kto-rého výstup 12 je připojený na vnátornázbernicu 110, na ktorá je připojený vstup21 prijímača 20 informačných bitov, ktoré-ho výstup 22 je připojený na vstup 31 ge-nerátora 30 kontrolných bitov a na prvývstup 81 bloku 80 oprava jednoehyby, vý-stup 32 generátora 30 kontrolných bitov jepřipojený na druhý vstup 52 generátora 50příznakových bitov a na druhý vstup 42prepínača 40 kontrolných bitov, výstup 2informačných bitov z registra riadiacehotestovania pamáťových elementov památa-jácich si kontrolně bity je připojený na dru-hý vstup 102 prepínača 100 výstupných bi-tov a na prvý vstup 41 prepínača 40 kon-trolných bitov, ktorého výstup 43 je připo-jený na vnátorná zbernicu 110, na' ktorá jepřipojený tiež prvý vstup 51 generátora 50příznakových bitov, ktorého výstup 53 jepřipojený na vstup 81 generátora 80 signá-lov jednoehyby a dvojchyby a tiež na prvývstup 71 dekódera 70 jednoehyby, na ktoré-ho druhý vstup 72 je připojený výstup 62generátora 60 signálov jednoehyby a dvoj-chyby, výstup 73 dekódera 70 jednoehybyje připojený na druhý vstup 82 bloku 80 o-prava jednoehyby, ktorého výstup 83 je při-pojený na vstup 91 registra 90 výstupnýchbitov, ktorého výstup 92 je připojený navnátorná zbernicu 110 a tiež na prvý vstup101 prepínača 100 výstupných bitov, ktoré-ho výstup 103 je připojený na výstup 3 vý-stupných informačných bitov.Involvement for Detection, Localization, and Urgent Correction of One Error and also Detection of All Two-to-One Errors in a 22bit Word, where 16 bits represent information bits and 6 bits of Control Bits in self-corrected binary code with minimum code distance d = 4 is modified such that the output 1 of the information bits is connected to the input 11 of the input bits 10, which output 12 is connected to the internal bus 110 to which the input 21 of the information bit receiver 20 is connected, which output 22 is connected to input 31 of the generator 30 control bits and on the first port 81 of the block 80, the single bend correction, the output 32 of the control bits generator 30 is connected to the second input 52 of the flag bit generator 50 and the second input 42 of the control bits switch 40, the output bits of the memory control register of the memory elements of the memory bits is connected to the second input 102 of the switch 100 and a first input 41 of a control bit switch 40, the output 43 of which is connected to an internal bus 110 to which also a first input 51 of the flag bit generator 50 is connected, the output 53 of which is connected to the input 81 of the signal generator 80 the single deflection and double deflection as well as the first inlet 71 of the single deflection decoder 70 to which the second inlet 72 is connected to the output of the single deflection signal generator 60, the output 73 of the single deflection decoder 70 is connected to the second input 82 of the single deflection block 80; the output 83 of which is connected to the input 91 of the output bits 90, whose output 92 is connected to the internal bus 110 and also to the first input 101 of the output bitswitch 100, which output 103 is connected to the output 3 of the output information bits.

Informácia určená k zakódovaniu je při-vedená na výstup 1 informačných bitov, od-kial' je přivedená na vstup 11 registra 10vstupných bitov, informačně bity z výstu-pu 12 registra 10 vstupných bitov sá při-vedené na vnátorná zbernicu 110, z ktorejinformačně bity postupujá jednak k pamá-ťovým elementem. a tiež na vstup 21 prijí-mača 20 informačných bitov, výstup 22 pri-jímača 20 informačných bitov je vedený n,aprvý vstup 81 bloku 80 oprava jednoehyby,ktorý sa při zakódovaní informácie neuplat-ňuje a tiež na vstup 31 generátora 30 kon-trolných bitov, v ktorom sa vygenerujň kon-trolně bity definované kontro,lnou maticouThe information to be encoded is inputted to the output 1 of the information bits when it is input to the input register register 10 of the input bits, the information bits of the register output 12 of the input bits inputted to the internal bus 110, of which information bits progressing to the memory elements. and also at the input bit 21 of the receiver 20, the output bit 22 of the information bit receiver 20 is routed n, and the first input 81 of the single bit correction block 80, which is not applied to the input 31 as well as the input 31 of the control generator 30 bits in which the control bits defined by the control matrix are generated

Claims

245872 and are routed to the output 32 of the control battle generator 30 from where they are routed to the second exit 52 of the flag bit generator 50 which is not applied to the encoding information as well as the second input 42 of the control bit switch to which the input 41 is output 2 of the information bits from the test control register, the output 43 of the check bit switch 40, if no testing is in progress, are brought to the input 42 by the control bits, the control bits from the output of the bits of the control bits 40 are fed to an internal bus 110 from which control bits pass through the memory element. When the information bit is decoded from the internal bus 110 to which it is received from the memory elements, the information bits 20 of the receiver 20 are inputted, the output 22 of the information bit receiver 20 is routed to the first input 81 of the block 80 of the correction one. but also to the input 31 of the control bit generator 30 in which the control bits defined by the control matrix are generated and output to the control bit generation output 32 from where they are fed to the second input 42 of the control bit switch 40 is not applied to the decoding and also to the second input 52 of the generator. 50 flag bits to which. the first inlet 51 is fed by control bits from the internal bus 110 to which the memory elements have received, after evaluating the control bits in the flag bit generator 50, flag bits are generated at its output 53 which are routed to the first port 71 of the decoder 70 and also the input 01 of the monochrome and double error signal generator 00 in which the error type information is generated and also the operation of the single fault decoder 70 in the occurrence of the error signal from the output 02 of the generator 00 of the single fault and double error signals, which is applied to the second input 72 of the single-fault decoder 70 in which the position of the erroneous bit that is defined by the signals from the output 73 of the single-decoder decoder 70 that is brought to the second inlet 82 of the single-correction correction block 80 is corrected, in which the correction is made the wrong bit at the right level and at the output of the block 83, the right one is getting the correct information bits at the occurrence of j errors and / or corrected information bits at the occurrence of a double error, and these are applied to input 91 of the output bits register 90 and from its output 92 the information bits are routed to the internal bus 110 and also to the first input 101 of the switch 100 for which the second input 102 is outputted by the information bits output from the control test register, to the output 103 of the output bits switch 100 in a state where no testing is performed, the correct information bits are reserved for the occurrence of a single error or non-corrected information bits at double error and output to 3 output information bits. It can be said that engaging in the detection, localization and self-repair of one error and also the detection of all double-errors in the language ensures parallel encoding of the pre-read information in the self-correcting code with the minimum code distance d = 4 so that the 16 information bits are attached 6 control bits, further control of the encoded information by comparing the received control bit values with the value of the non-generated control bits, detecting the location and correction of one error in any one of the 22 bits of the encoded word, detecting and signaling all double errors. The wiring can be used to protect the data written into! and read from the memory of the numerical system, for example, in contact with the memory or operating memory of the computer, the minicomputer, the microcomputer, the calculator, the digital telephone exchange, and the data transmission between the digital systems, -power units, between additional devices and the like. OBJECT Involvement for detection, localization, and repair of a single error, as well as the detection of all binary errors in a 22-bit word, where 16 bits represent information bits and 6 bits control bits in a self-corrected binary code with a minimum code distance of d = 4, characterized in that the output bit (1) of the information bits is connected to the input (11) of the register (10) of the input bits, the output (12) of which is connected to an internal bus (110) to which the input (21) of the receiver is connected (20) information battles, the output (22) of which is connected to the input (31) of the check bit generator (30) and to the first input (81) of the block (80). the control bit generator (30) is connected a second input (52) of the flag bit generator (50) and the second input (42) of the switch (40) of the control bits, output (2) of the information bits from the control register. testing memory elements memorable the control bits are connected to a second output port (102) of the output binary switch (100) and to the first input (41) of the check bit switch (40), the output (43) of which is connected to the internal bus (110), the first the flag bit generator (50) input (51), the 245872 output (53) of which is connected to the input (61) of the single fault and double error signal generator (60) and also to the first input (71) of the decoder (70) a fault, to which the second input (72) is connected to the output (62) of the single fault and double fault signal generator (60), the output (73) of the single fault decoder (70) is connected to the second input (82) of the block (80) a single error correction whose output (83) is connected to an input (91) of the output bit register (90) whose output (912) is connected to an internal bus (110) and also a first input (101) of the switch ( 100) output bits, the output (103) of which is output to output information bits (3). 1 sheet of drawings