CS244484B1 - Priority decoder connection - Google Patents

Abstract

The priority decoder consists of a permanent decoder memory, isolation and flip-flops  and Concurrent Members and is designed for parallel control communication of microcomputers or computers with the common bus to which they are simultaneously connected steam and A / C or A / A converters. The priority of the connected microcomputers can be be arbitrary and determined by the decoder memory. Priority decoder can be used for · microcomputers for cooperation with an auxiliary bus, where the priority decoder allows collaboration individual microcomputers with auxiliary bus according to a predetermined priority event. controlled and changeable from the parent computer.

Description

(54) Priority decoder connection

The priority decoder consists of nonvolatile memory, decoupling and flip-flop circuits, and sum members and is designed to control parallel communication of microcomputers or computers to the common bus, to which the parnet and A / C or A / A converters are connected at the same time.

The priority of the microcomputers involved can be arbitrary and is determined by the decoder memory.

Priority decoder can be used in connection of microcomputers for cooperation with auxiliary bus, where priority decoder allows cooperation of individual microcomputers with auxiliary bus according to predetermined priority, event. controlled and changeable from the host computer.

244464

The invention relates to the connection of a priority decoder consisting of permanent pernat, separating and flip-flops and summation elements intended in particular for controlling parallel communication of microcomputers or computers with a common sub-bus.

Even the involvement of sub-bus microcomputers, a method of parallel co-operation of several computers or sub-bus microcomputers to which memory and converters are connected at the same time and which has not yet been known from the available literature is being solved.

In the case of simultaneous application of several microcomputers for cooperation and an auxiliary bus, the priority of the operator is determined by a priority decoder, the language of which is also not known from the available literature and which is the subject of the present invention.

The decoder is designed for optimal control of parallel cooperation of microcomputers and its essence is that the priority memory of the priority decoder with the control input of the decoder priority is connected by its address inputs via separating circuits and the inputs of the priority decoder connected to the outputs of individual microcomputers.

The non-volatile memory outputs are connected to the setting inputs of the flip-flop circuits, the outputs of which are routed to the outputs of the priority decoder and to the individual inputs of the summation circuit, the output of which is coupled to the latching input of the non-volatile memory.

In parallel to the inputs of the primary decoder and the inputs of the decoupling circuits, monostable multivibrators are connected, the outputs of which are coupled to the inputs of the summation element.

The output of the summation element is connected in parallel to the reset inputs of the individual flip-flops.

The wiring of the priority decoder according to the invention is shown in the attached drawing. Any number of microcomputers can cooperate with a common bus, each being given a different priority. For example, microcomputer number 1 has the lowest priority, microcomputer number 2 has higher priority, and with increasing number the priority level increases.

Assuming that three microcomputers cooperate with the common bus, microcomputer # 3 has the highest priority, microcomputer # 1 has the lowest priority. If, for example, microcomputer Nos. 1 and 3 requests communication at the same time, the microcomputer No. 3 is preferred and only the microcomputer No. 1 is served.

If, however, the No. 1 microcomputer already cooperates with the common bus, and only then does the No. 3 microcomputer request communication, then the No. 3 microcomputer must wait until the No. 1 microcomputer completes the ongoing communication, which can generally be arbitrary.

Only after the completion of the microcomputer communication # 1, the strict decoder of the microcomputer communication # 3.

The priority of microcomputers can be arbitrary and is determined by the decoder memory. It is a memory of type ROH or PROU, where the decoder priority is fixed.

The priority decoder permanent memory with the decoder priority control input AS is connected to the priority decoder separator circuits Ol-Ok and the priority decoder input Kr1-KRk by its address inputs ΑΪ-Ak and the outputs of the individual microcomputers shown.

The non-volatile memory outputs m are connected by the β-adjusting inputs S of the Bi-Bk flip-flops. the outputs of which are connected to the outputs of the priority decoder KPi-KPk and to the inputs of the summation circuit S8i whose output is connected to the blocking input Sfi of the permanent memory fifi. In parallel to the inputs of the priority decoder KRl-KRk and the inputs of the Ql-Ok isolation circuits, monostable aultivibrators are connected whose outputs are connected to the inputs of the summation element ϋχ. The output of this element is connected in parallel by β reset inputs g of individual flip-flops B1-Bk.

A communication request is fed from the individual microcomputers to the inputs of the KR1-KRk priority decoder. The input signals are fed through the 01-Ok isolation circuits. to the address inputs ΑΙ-Ak of the permanent memory MI) of the decoder.

Permanent memory It is divided into so-called pages. By means of the non-volatile memory control input MD and the address separator circuit L1, these areas can be changed and thus the decoder priority.

Each area of non-volatile memory] (a priority decoder £ is given a certain priority, which can be changed, for example, from the host computer according to the nature of the controlled technological process from the non-volatile memory outputs MD are controlled by setting inputs fi flip flops B + - Bk in such a way that the signal corresponding to the voltage required to flip the adjacent flip-flop B1-Bk appears only on the corresponding output of the Do-Dk of the permanent memory MD.

The outputs of the flip-flop circuits B1-Bk are fed via the outputs of the priority decoder KP1-KPk to the communication circuits of the respective microcomputers, and to the individual inputs of the summation circuit fifi whose output k is connected to the blocking input CS of the permanent memory fifi.

If a communication enable signal is output from any of the flip-flop circuits B1-Bk, the non-volatile memory MD is blocked from the sum fifi circuit as long as the associated flip-flop B1-Bk is flipped over.

In parallel to the inputs of the priority decoder KR1-KRk and to the inputs of the decoupling circuits 01-Ok, monostable M1-Mk multivibrators are connected so that they output an impulse to terminate the communication request.

The output pulses from these monostable multi-vibrators M1-Mk are applied to the input of the sum element gl, which resets the flip-flop circuits B1-Bk. thereby restoring the decoder's ability to evaluate the next communication request.

244464

Claims (1)

I will invent the front Connection of a priority decoder consisting of non-volatile memory, decoupling flip-flops and summation elements, in particular for controlling parallel communication of microcomputers or computers with a common sub-bus, characterized by: At-Ak) connected via decoupling circuits (Ol-Ok) to the priority decoder inputs (KR1-KBk) associated with the outputs of the individual microcomputers, the permanent memory (ND) outputs (Do-Dk) are connected to the adjusting inputs (S; flip-flops) Bl-Bk), whose outputs (Q) are directed both to the outputs (KPI-KPk) of the priority decoder and to the inputs of the summation circuit (SO), the output of which is connected to the blocking input (CS) of the permanent memory (ND) monostable mules are connected to the inputs (KR1-KRk? of the priority decoder and to the inputs of the isolation circuits (Ol-Ok) tivibrators (Nt-Hk), the outputs of which are coupled to the inputs of the summation element (NI), the output of which is connected in parallel to the zeroing! inputs (R) of individual flip-flops (Bl-Bk).