CS244051B1 - Wiring for correction of position coordinates in electron lithograph - Google Patents

Abstract

The circuit for correcting position coordinates is created with a minimum number of arithmetic circuits. The essence is a circuit divided into a preparatory block and three stages of calculating the corrected coordinates. The preparatory block contains eight adders for the digital operation A. B, whose inputs A are connected to the first set of correction outputs of the data system and their inputs B to the second set of correction outputs of the data system. The first calculation stage is then formed by four arithmetic circuits for the operation A + B. C and the first two registers. The second stage is formed by the fifth and sixth arithmetic circuits and the third and fourth registers, while the third stage is formed by the ninth and tenth adders, whose outputs form the corrected coordinates x and y.

Description

The invention relates to the connection of positional coordinates with a minimum number of arithmetic circuits.

In a vector-type electron lithography, the electron exposing beam is shaped into a generally rectangular cross-section of variable dimensions and then deflected within the exposure field by an electrostatic or electromagnetic field. After the final positioning of the beam, exposure of one elementary stamp is performed, from which the entire exposed mask drawing of one technological layer of the integrated circuit is assembled. Very strict requirements are placed on the deflection of the exposing beam - the location of the reference point of the elementary stamp must be reproducibly adjustable and absolutely accurate with a deviation of approximately the entire range of deflection. In addition, it is necessary to adapt the deflection coordinate system with the same accuracy to the structure already created on the exposed substrate, which is captured in the reference marks, usually four within one exposure field. In the mode of direct exposure of masks to a silicon wafer, this previous structure may even be deformed due to the influence of technological operations already performed. The above requirements result from the need to achieve perfect alignment of adjacent exposure fields _and perfect overlap of individual technological layers, as well as alignment and overlap of parts of structures exposed by electron lithography with parts of structures or technological layers exposed in another way, e.g. photolithographically. The only non-exclusive way to achieve the required accuracy is digital deflection control using highly accurate 16-bit or more digital-to-analog converters.

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The design of a highly accurate digitally controlled electron beam deflection block brings a number of problems* which are further complicated by the requirement for extreme deflection speed and thus exposure productivity. However, even overcoming all these problems leads only to a partial result*, namely to obtaining reproducible adjustability and absolute accuracy of the output electrical quantity of the deflection block*, i.e. the voltage on the deflection plates* or the current in the deflection coils. The transformation of this electrical quantity into the geometric coordinates of the exposing beam in the exposure field is burdened by other disturbing factors. Some of them*, such as off-axis aberrations of the electron-optical system of the electron lithographer*, can to some extent^ be theoretically captured with the necessary accuracy, but it is difficult to theoretically capture them. The remaining factors*, such as external disturbing electromagnetic fields*, manufacturing tolerances of the parts of the electron-optical system and various drifts*, however, have a random and partly even average character. The same nature is also the additional deformations of the previously exposed structures*, i.e. the network of reference marks. All these circumstances imply the necessity of correcting the own coordinate system of the electron lithographer based on the measurement of the calibration standard. When measuring the calibration standard consisting of a reasonably dense network of marks, the electron lithographer is used in the scanning electron microscope mode^ the image of the calibration standard is automatically evaluated and the differences between the measured and nominal positions of the force points of the calibration standard are detected. These differences can be compiled into a two-dimensional calibration matrix* in which we can then find the correction of any position of the exposing beam by interpolation.

The calibration matrix of corrections of the electron beam positions at discrete points corresponding to the network of marks of the calibration standard ensures reproducible adjustability when performing recalibration sufficiently frequently with respect to the variability of disturbing factors, as well as absolute accuracy of these discrete coordinate values. However, the corrected coordinates at locations outside the calibration points must be determined by calculation. The calibration matrix itself must still be adjusted for each exposure field so that it captures the adaptation of the ideal Cartesian coordinates, represented by the calibration standard, to the previously exposed structure represented by the reference marks.

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The actual correction of the coordinates will be carried out according to the relations x* = x + Ρ _χ (χ, y) = x + (β _χ + _b x x + _ΟχΥ + ά _χ χγ) y* = y ⁺ Py(x> y) ^s y + <&y ^{+ +} cyx + d _y xy)

This range of correction polynomials containing four correction constants a to d corresponds to the square grid of calibration polynomial marks and also to the four reference marks in the exposure field. The correction constants are determined from the conditions of agreement of the coordinates with the positions of the marks in the corners of the given grid field of the calibration standard* or with the positions of the reference marks* so that in both cases we have at our disposal a solvable system of 8 equations, agreement of both coordinates for all four marks, for 8 unknowns a to d and a to d .

If the above equations express the correction of coordinates within the calibration grid field with correction constants corresponding to this field * then the equations of the same form * * * . -n* f * * \ x = x + p _x (x > y ) y = y + P _y (x > y ) express the correction of coordinates to the previous structure represented by the reference marks. The sequence of coordinate transformation x—>x*-> x** is given by the fact that the reference marks are measured with the already calibrated electron beam deflection.

It can be proven that in the first-order approximation, which corresponds in its accuracy to the used range of correction polynomials, in the direct transformation x->x**, it is possible to simply add up the co-ordinate constants in the correction polynomials. For the resulting coordinates x**, y** corrected to the calibration standard and to the previous structure, x** = x + _{Ρ χ} *(χ, y) = x + [\β _χ + β _χ ) + (b _x + b _x )x ⁺ + (c _{x + c*)y + (d x} + d*)xyj _y ** = _y + P _y '(x* y) = y + Qa _y + aý) + (b _y + bý)y + ^{+ (c} y ^{+ c} ý ^{)x + (d} y ^{+ d} ýM »

244 051 where x, y are the nominal coordinates of the elementary stamp in the exposed structure* the constants a to d and a to d are calculated for the given fields of the calibration standard and the constants a* to d^ and a to dý correspond to the reference marks of the exposure field.

The task of the electron lithography control system is therefore, based on occasional measurements of the calibration standard and on measurements of reference marks in each exposure field^ .if they are located in it, to perform in real time the conversion of the x, y coordinates from the exposure data set into the x**, y** coordinates set in the deflection steps. Due to the high frequency of elementary exposures, it is necessary to perform this conversion at the maximum achievable speed. Due to the complexity of the transformation equations, this represents a highly demanding task.

The calculation of the corrected coordinates can be provided programmatically in the control computer of the electron lithographer. However, even an optimized program in a computer with the maximum available operating speed cannot correct one pair of coordinates in a time of about 1/usec or less*, which is the achievable exposure time of an elementary stamp. The correction of coordinates would thus become a significant limiting factor for the productivity of the exposure. A specialized process can also be built to solve the correction relations (3), which may be satisfactory in terms of speed. However, this solution would involve the development and production of a large volume of unique hardware, which would be disadvantageous, among other things, in terms of reliability and service.

These previous shortcomings are solved by the circuit for correcting position coordinates in the electron lithography, consisting of ten adders for the digital operation AB, six arithmetic circuits for the digital operation A + B . C and four registers. The essence of the connection is that the first eight adders are connected by their inputs to the first set and by their inputs to the second set of correction outputs of the data system, while the outputs of the first and second adders are connected to the inputs of the first arithmetic circuit, the outputs of the third and fourth adders are connected to the inputs of the second arithmetic circuit, the outputs of the fifth and sixth adders are connected to the inputs of the third arithmetic circuit, the outputs of the seventh and eighth adders are connected to the inputs of the fourth arithmetic circuit, while the input of the x coordinates is connected to the inputs of the first and second arithmetic circuits and the first register, the output of which is connected to the input of the sixth arithmetic circuit and through the third register to the input of the ninth adder with the output of the corrected x coordinates, while the input of the y coordinates is connected to the inputs of the third and fourth arithmetic circuits and to the input of the second register, the output of which is connected to the input of the fifth arithmetic circuit and through the fourth register to the input of the tenth adder, while the outputs of the first and second arithmetic circuits are connected to the inputs of the fifth arithmetic circuit, the output of which is connected to the input of the ninth adder, while the outputs of the third and fourth arithmetic circuits are connected to the inputs of the sixth arithmetic circuit, the output of which is connected to the input of the tenth adder with the output of the corrected y coordinates.

The advantage of the circuit according to the invention is that, in addition to the registers, it consists of only two simple types of arithmetic circuits repeated several times, which increases the standardization of the hardware, and furthermore, that all the circuits are assembled into three stages of a sequential pipe-line process with the possibility of time sharing between these stages, so that it is possible to achieve a minimum execution time of the entire correction procedure equal to the time of the slowest operation, i.e. the delay in the arithmetic circuit for the operation A + B . C.

The circuit according to the invention will be explained in more detail in the attached drawing, in which Fig. 1 shows the entire device, divided into a preparation block and three stages of calculating corrected coordinates.

The preparatory block contains eight adders £, .£,£,£»£.> £» 1» to whose inputs A j* ^are connected the correction constants of the first set of correction outputs of the data system, to the inputs £ the correction constants of the second set of correction outputs of the data system. The first computing stage contains the first four arithmetic circuits 1.1 _Ť 12« 13^ 14 for the operation A + B . C and the first two registers 21. and 22. In this case, the input 17 of the x coordinate is connected to the input of the first register 21 and to the inputs C, of the first and second arithmetic circuits 21 and 22. The input 17 of the x coordinate is connected to the input of the second register 22 and to the inputs £ of the third and fourth arithmetic circuits 12 and 1,4 the input 1B of the y coordinate is connected. The inputs and B of the first and second arithmetic circuits 1 _[ 1 _| and 12 are connected in stages to the outputs of the first four adders £ from the preparatory block^, while the outputs of the next four adders 5$ X> £ are connected to the inputs £ and B of the third and fourth arithmetic circuits 13 and 14 in the first stage in turn. The second stage consists of the third and fourth registers 2J, and 2£ and the fifth and sixth arithmetic circuits 15 and .16, while the output of the first register 21 is connected to the input of the third register 23 and to the input G of the sixth arithmetic circuit 16. The input of the fourth register 24 and the input 2. of the fifth arithmetic circuit 15 is connected to the output of the second register 22. The outputs of the first and second arithmetic circuits 11 and 12 are connected to the inputs A and 2 of the fifth arithmetic circuit 15. The outputs of the third and fourth arithmetic circuits ua and 1A are connected to the inputs A and B of the sixth arithmetic circuit 1.6. The third stage is formed by the ninth and tenth adders 2, and ,10 _f to whose inputs A are connected the outputs of the third and fourth registers 23 and 24.. while to their inputs £ the outputs of the fifth and sixth arithmetic circuits 15 and £6 are connected. The outputs ££ and 20, the ninth and tenth adders £ and 10 in the third stage of the described circuit form the corrected output coordinates x and y.

During operation, the circuit works as follows: When exposing within the nth field of the calibration standard grid, the first inputs of the adders £ to 8 are fed in digital form with the corresponding correction constants β _χ to d _x and ay to d in a given order. When exposing between the reference marks, the correction constants β _χ to dy determined by measuring the positions of the reference marks are simultaneously present at the second inputs of the adders J, to 8 for the entire duration of the exposure of one exposure field. The resulting correction constants a + a*> ······ d _v + d* are therefore available at the outputs of the adders £ to Q of the preparation block. In the first stage of the correction processor xx jr . y the first step of processing the coordinates of the exposed elementary stamp is performed. In the first four arithmetic circuits UL to 14, the data (a* + ψ + Ct> _x + x (c _x + c') + (d* + <) X <a _y + ψ + ^(b y + b*) y ^(o y ^{+ e} ý' ^{+ <a} y ⁺ Φ 7 are calculated sequentially.

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During this calculation, the values jaj are held in the first and second registers 21 and 22. After this operation is completed, all these digital data are transferred to the second stage and the first stage is completely released. In the time-sharing mode, the processing of further coordinates from the input terminals 17 and 18 can begin immediately in the first block. In the second stage, the results of the first stage are processed for a longer time so that in the fifth arithmetic circuit 15 ^P x' ^(x * y) = [< ^a x + a') + < _{b x} + b')x] + βο _χ is calculated and in the arithmetic circuit 16 ^P ý' ^(x « y) = E<ay + Ý + (b _y * b')y] * [<c _y c _x ) + <a _x + a _x )x] _y ^c ý' ^{+ <d} y ^{+ a} ý ^)y l·

At the same time, the values of χ and χ are maintained in the third and fourth registers 23 and 24 of the second stage during the calculation. After transferring all these signals to the third stage, the second stage is released for further processing of the following intermediate results of the first stage, which can immediately start processing the third batch of coordinates from the input terminals 17 and 18. In the third stage, the final addition χ = χ + p**(x, y) y = y + Pý'<x> y) ' is performed and the corrected coordinates x** and y** are output to terminals 19 and 20.

At the moment of output, or rather after the completion of the arithmetic operations in the first and second stages, which are longer and determine the frequency of the strobe signals for transmission between the individual stages, the corrected coordinates are implemented in the electron beam deflection block and the fourth coordinates from the input terminals 17 and 18 simultaneously enter the correction block. The circuit according to the invention therefore delays the exposure data at the output relative to the input by three doses, with the time between two consecutive outputs of corrected data being equal to the duration of the longest operation, i.e. the delay of the arithmetic block for operation A + B . C.

The device according to the invention can be used for correction of digital coordinates in an electron lithography and in a measuring scanning electron microscope.

Claims (1)

Wiring for correction of coordinates in an electron beam lithograph, consisting of ten adders for digital operation AB, six arithmetic circuits for operation A + B, C and four registers, characterized in that the first eight adders (1 to 8connected $ * - inputs (A) with a first set and inputs (B) with a second set of data system correction outputs, the outputs of the first and second adders (1 and 2) being connected to the inputs (A and B) of the first arithmetic circuit (11), outputs of the third and fourth adders (3) and 4) are connected to inputs (A and B) of the second arithmetic circuit (12), outputs of the fifth and sixth adder (5 and 6) are connected to inputs (A and B) of the third arithmetic circuit (13), outputs of the seventh and eighth adder (7 and 8) are coupled to the inputs (A and B) of the fourth arithmetic circuit (14), while the x-coordinate input (17) is coupled to the inputs (C) of the first and second arithmetic circuit (11 and 12) and the first register (21). ), whose output is joints n with the input (C) of the sixth arithmetic circuit (16) and via the third register (23) with the input (A) of the ninth adder (9) with the output (19) of the corrected x coordinates, C) the third and fourth arithmetic circuits (13 and 14) and the input of the second register (22), the output of which is connected to the input (C) of the fifth arithmetic circuit (15) and through the fourth register (24) to the input (A) of the tenth adder (10), wherein the outputs of the first and second arithmetic circuits (11 and 12) are connected to the inputs (A and B) of the fifth arithmetic circuit (15), the output of which is connected to the input (B) of the ninth adder (9), and the fourth arithmetic circuit (13 and 14) are coupled to the inputs (A and B) of the sixth arithmetic circuit (16), the output of which is coupled to the input (B) of the tenth adder (10) with the output (20)