CS239155B1 - Testing instrument wiring diagram - Google Patents

Abstract

Involvement consists of a series of exciting members (1), which inputs (11) are connected to inputs (31) tested by PROM / ROM memory (3), whose outputs (33) are connected to input (21) of D-flip-flops (2). outputs (23) These D-flip-flops (2) are connected on control system, hourly input (22) D-flip-flops (2) is connected to the output (43) of the control logic (4) the second output (44) is coupled to the release input (12) of excitation members (1) a its input (41) is connected to the control system.

Description

The invention relates to the connection of a PROM / ROM content tester for storing all formats used which are mounted on and not detachable from a printed circuit board.

For devices where the contents of programmed PROM / ROM memories are not included in the documentation, deeper and more extensive maintenance cannot be performed. With the memory inserted in the sleeves, the contents of the memory can be detected by the programmers when removed. If the programmer were used to detect the contents of a fixed, usually soldered PROM / ROM memory on the electronics board, it would be necessary to separate the PROM / ROM memory, to fly out of thatch, which is associated with frequent damage, especially for densely mounted boards.

Even if the printed circuit board is damaged, the possibility of servicing the original manufacturers with guaranteed functionality is lost. In cases where the contents of the memory are not known, it is not possible by the own technicians to repair the equipment to an absolute depth, but repairs are required from the original manufacturers, which is associated with the disadvantage of higher financial costs and lower maintenance operability.

These disadvantages are overcome by the wiring of the test apparatus of the invention.

The invention consists in that the device consists of a series of actuators whose inputs are connected to the control system and the outputs are connected to the inputs of the test memory. The data outputs of the memories are connected to the input of D-circuits, whose outputs are connected to the control system. The clock input D of the flip-flops is connected to the output of the control logic, the second output of which is connected to the release inputs of the actuators. The control logic input is connected to the control system.

Said apparatus makes it possible to detect the contents of the PROM / ROM memories that are firmly embedded in the thatch electronics without the need to separate, remove from the thatch, for example, by flying away. This will enable the level of maintenance of the equipment to be increased, thereby reducing maintenance costs and making repairs more operational.

The connection according to the invention is shown in the attached drawing. The wiring consists of a series of actuators 1 whose inputs 11 are connected to the control system and the outputs 13 are connected to the inputs 31 of the tested PROM / ROM memory 3, the outputs 33 of which are connected to the input 21 of the D-flip-flops 2. The D-flip-flops 2 are connected to the control system, the clock input 22 of the D-flip-flops 2 is connected to the output 43 of the control logic 4, whose second output 44 is connected to the release input 2 of the actuators 1 and its input 41 is connected to the control system.

Each driver 1 allows to force all address inputs 31 to memory 3 for a short time (approx. 350 ns) given by the trip signal from control logic output 44 logic level 0 or 1 without damaging the connected TTL circuits, depending on the level at driver 11 input 11 .

The control system generates an address at the inputs 11 of the actuators 1, then activates at the input 41 of the control logic 4 a signal to initiate the process of reading the contents of the memories 3 at the specified address. On the data outputs 33 of the PROM / ROM memory 3, the contents of the set address are delayed by a trip time (approx. 70 ns).

By taking the signal from the output 43 of the control logic 4 connected to the clock inputs 22 of the D-flip-flops 2, the data are stored! and are available for download by the control system at outputs 23. After min. 500 ns, the control system reads the contents of the memories 3 at the specified address from the outputs 23 of the D-flip-flops 2. This completes the cycle of reading the contents of one memory line. Control. the system generates all address combinations sequentially to read the entire memory.

The device was used to determine the contents of memory in the peripheral controllers for an automated pipe factory production control system.

Claims (1)

SUBJECT A tester for detecting the contents of memories connected in a logic network, characterized in that it consists of a series of excitation members (1) whose inputs (11) are connected to the control system and the outputs (13) are connected to inputs (31) of the tested memory (3), the outlets (33) of which are connected to the inlet (21) of the D-flip-flops (2), OUT of the outputs (23) of these D-flip-flops (2) are connected to the control system, the clock input (22) of the D-flip-flops (2) is connected to the output (43) of the control logic (4), the second output (44) it is connected to the release input (12) of the actuators (1) and its input (41) is connected to the control system.