CS238958B1 - Make pulses digital generator wiring diagram for thyristor converters - Google Patents

Abstract

the solution concerns management and regulation and solves digital generator wiring pulses for thyristors. The phase angle reference signal is converted to a digital signal and limit it the limits in the converter, the signal signals of each the phases are formed in the shapers, sync in sync and the counter is processed along with the signal from the converter, to the instantaneous phase signal angle shifted by the setpoint. There is information about it in the effuser the length of the triggering pulses, and the maximum counter value to stop counting. Here, the signals are partially decoded and transmitted to the decoder in which it is created closing pulses. The invention is utilized in controlling the converter and electric drives

Description

The invention relates to the swiveling of a digital trigger generator for thyristor transducers.

Various wiring of analog and digital switching pulse generators for thyristor converters are known. The most convenient digital connections are in Imize A.A. Botovrina et al. numerical control systems for electric drives ”. These circuits usually work on the principle of delaying the pulse by a time value measured by a counter having specified initial conditions. The time delayed pulse is processed by the output logic circuits and amplifier pulse generators. The disadvantage of this arrangement is that it is difficult to distribute the pulses for the individual branches of the multiphase converters, because the higher order angle information of the multiphase system is not taken into account. This results in malfunctions of the inverter when reversing the phase sequence at the inverter input, causing difficulties in non-stationary devices. Another drawback is that the output pulse is formed by a separate pusher in the circuit, which cannot be formed as a digital circuit for coarse division. The use of a monostable circuit at this location results in the risk of false fault trigger pulses. An inaccurate length of the pulse thus obtained increases the possibility of inverter malfunction in the inverter operation range. This is because at a longer pulse length, the pulse can cause the thyristor branch to turn on while the opposite thyristar branch is still on. This results in a short circuit on the load side, also known as "burn-through".

These drawbacks are eliminated by the wiring of the digital generator of the triggering pulses for the thyristor converters according to

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The invention is characterized in that each phase input of the wiring is connected to the input of a corresponding molder. The output of each molder is connected to the signal input of the corresponding synchronizer. The group output of each synchronizer is connected to the group input of the corresponding summator. The stop output of each summator is connected to the stop input of the corresponding counter. The clock input of each counter is connected to the clock input of each synchronizer, to the clock pulse generator output, and to the clock input of the converter. The first limiter input of the converter is connected to the first limiting input of the wiring. · The second limiting input of the converter is connected to the second limiting input of the transmitter. · The converter output is connected to the control input of each counter. The input input of each counter is connected to the clock output of the corresponding synchronizer. The output of each counter is connected to the phase input of the corresponding summator. The phase output of each summator is coupled to the corresponding decoder input. Each positive output of the decoder is associated with a corresponding positive output of the decoder. • Each negative output of the decoder is associated with a corresponding negative output of the decoder.

An advantage of the arrangement according to the invention is that it can be used for single-phase and multiphase switching generators for thyristor converters. Eliminates tedious and unreliable multi-phase setup in drive control circuits · Phase angle of inverter switching and phase synchronization is firmly coded in the wiring and is stable, independent of climatic conditions and plant age · Time stability and phase angle limitation are particularly beneficial inverter inverter operation. The limiting circuits allow more complex reversing inverters to limit the phase angle while the inverter is running. Generating a trigger pulse in a digital manner assists reliable operation

- 3 238 95 inverter as an inverter. The wiring ensures that the inverter functions correctly even when the power supply phase sequence changes, which simplifies handling of non-stationary inverters. The sampling pattern of the wiring operation contributes to the stabilization of the controlled system and to the increase in vibration resistance. The wiring is made of commercially available components, is simple to manufacture and inexpensive. After the recovery, there is no maintenance of the equipment.

An example of a circuit according to the invention is shown in the block diagram of the attached drawing.

Individual wiring blocks can be characterized as follows. The converter 1 is formed from an analog-to-digital converter or a digital-to-digital converter. It is either a stand-alone converter or part of a microcomputer and contains circuits to limit the maximum and minimum values of the output digital signal. It is used to create a digital signal of the desired switching angle of thyristors. All formers 2.1 to 2.n are the same and their number corresponds to the number of phases. Each molder consists of comparators. Used to convert the sine wave voltage to a logic rectangular signal. All synchronizers 3.1 to 3.n are upright. They are made of D-type flip-flops, two-input and three-input gates. It is used to create a synchronized signal to enter the initial value of the phase signal and to generate a signal _F that carries information about higher orders of instantaneous phase shift. All counters 4.1 to 4.n are the same », They are integrated with an output signal preset. Creates a digital value of the instantaneous phase angle shifted by a specified value. All the summers 5.1 to 5.n are the same and consist of either integrated adders or Logic gates. It is used to create a signal to stop the counter in the end position, the width signal, the ignition pulse and to partially decode the output signal.

The decoder 6 is formed from diode transistor logic circuits. It is used to create a sequence of switching on pulses

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Generator 2 is made of crystal controlled oscillator and is used to generate clock pulses for synchronization of the whole circuit ·

The number n of the formers 2, the synchronizers 2 »of the counters 6 and the noise suppressors 6 is always the same and corresponds to the number of phases of the mains voltage. For single-phase voltage is n »1, for three-phase voltage is n» 3, for twelve-phase voltage is n * 12. Connection of individual blocks of digital generator of switching pulse for thyristor converters is done as follows. The wiring angle input 00 is coupled to the analog input 11 of the converter

1. Each phase input 03.1 to 03.n of the wiring is connected to the input 21.1 to 21n of the corresponding shaper 2.1 to 2.n. The output 22.1 to 22.n of each molder 2.1 to 2.n is connected to the signal input 31 »! to 31.n of the corresponding 3 * 1 to 3 »n synchronizers. The group output 34.1 to 34.n of each synchronizer 3.1 to 3 »n is coupled to the group input 52.1 to 52.n of the corresponding summator 5.1 to 5» n. The stop output 53.1 to 53.n of each summator 5.1 to 5.n is coupled to the stop input 44.1 to 44.n of the corresponding counter up to 4> n. The clock input 43.1 to 43.h of each counter 4.1 to 4.n is coupled to the clock input 32.1 to 32.n of each synchronizer 3.1 to 3.n, to the output 71 of the 2 clock pulse generator and to the clock input 14 of the converter 1. First limiting input 12 the converter 1 is connected to the first wiring input 01. The second wiring limiting input 02 is connected to the second limiting input 13 of the converter 1. The output 15 of the converter 1 is connected to the control input 42.1 to 42.n of each counter 11a to 11n. it is connected to the clock output 33.1 to 33.n of the corresponding synchronizers 3.1 to 3.n. The output 45.1 to 45 »n of each counter Iti to 4.n is connected to the phase input 51.1 to 51» n of the corresponding summator 5.1 to 5.n. The phase output 54.1 to 54.n of each sump 5.1 to 5.n is coupled to the corresponding input 60.1 to 60 »n of the decoder 6. Each

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- The output output 61.1 to 6n.l of the decoder 6 is coupled to the corresponding positive output 041.1 to 04n.l of the wiring. Each negative output 041o2 to 04n.2 of the wiring is associated with a corresponding negative output 61.2 to 6n of the 2 decoder 6. The wiring function is shown for one phase for simplicity. The wiring angle setpoint signal 00 is supplied to the wiring angle input 00. impulses. In the converter 1, this signal is converted into a digital signal adapted for downstream circuits. At the same time, a maximum allowable phase angle value is supplied to the first wiring input limiter input 01 and a minimum allowable phase angle value signal to the second wiring limiting input 02. Both of these signals limit the range of phase angle control. The first phase voltage input 03.1 receives the first phase voltage signal. In the first former 2.1, this signal, the progression of which is close to sinusoidal, is formed into a logical rectangular signal which carries information about the sign of the network voltage. This signal passes through the signal input 31 «, 1 to the first synchronizer 3 · 1ο In the first synchronizer 3.1 this signal is synchronized and the synchronized signal passes through its clock output as a pulse to input input 41o1 of the first counter 4.1» generates signals that carry higher instantaneous phase shift order information that passes to group input 52.1 of the first summation 5. 1.

The control input 42.1 of the first counter 4.1 receives a signal which carries information about the desired switching angle of the thyristors.

The first counter 4.1 generates a digital signal of the instantaneous phase angle shifted by the thyristor switching angle setpoint »» This signal is applied to the phase input 51.1 of the first summator 5.1 »In the first summator 5.1 this secsec with the signal that carries information phase, poates. In the first summation 5.1, iafSxetaasre are hard-coded by a maximum

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(ό the value of the counted pulses which corresponds to the phase angle and upon reaching the operation of the first counter 4.1 is stopped by a stop signal which the first summator 41 sends via its stop output 53ol to the stop input 44.1 of the first counter 4.1. The encoded information together with the higher order instantaneous phase shift information produces partially decoded signals transmitting the length and timing information of the trigger pulses, which pass through the phase output 54.1 of the first summator 5.1 to the first input 60.1 of the decoder β, · In the decoder 6, the partially decoded signal is processed by diode transistor logic circuits to make pulses that switch to the first positive output 61.1 of the decoder 1 or the first negative output 61.2 of the decoder j according to the polarity of the drive to be controlled. 6 and thence to the corresponding first positive wiring output 041.1 or to the first negative wiring output 0412. The transistors from the diode transistor logic circuits in the decoder 6 are used as power amplifiers to generate the trigger pulses. The synchronization of the whole connection is ensured by a 2-hour pulse generator.

The invention is utilized in automatic regulation in the control of converters, in electric drives.

Claims (1)

Wiring of a digital pulse generator for thyristor converters in which the wiring angle input is connected to the analog input of the converter, characterized in that each wiring phase input (03.1 to 03 _o n) is connected to the input (21.1 to 21.n) of the corresponding former (2.1 to 2.n), whose output (22.1 to 22.n) is connected to the signal input (31.1 to 31.n) of the corresponding synchronizer (3.1 to 3.n), whose group output (34.1 to 34.n) is connected to the group input (52 ₀ to 52.n) of the corresponding summator (5.1 to 5.n), whose stop output (53.1 to 53.n) is connected to the stop input (44ol to 44.n) of the corresponding counter (4.1 to 5.n) 4.n), whose clock input (43.1 to 43.n) is connected to the clock input (32.1 to 32.n) of each synchronizer (3.1 to 3.n), to the output (71) of the clock pulse generator (7) and to the clock the input (14) of the converter (1), the first limiting input (12) of which is a spo only with a first on-load limiting input (01) whose second limiting input (02) is connected to a second on-load limit (13) of the converter (1), the output (15) of which is connected to the control input (42.1 to 42.n) of each counter (4.1 to 4.n), whose input input (41.1 to 41.n) is connected to the clock output (33.1 to 33 · η) of the corresponding synchronizer (3d to 3.n), and the output (45.1 to 45.n) of each counter (4.1 to 4.n) is coupled to the phase input (51.1 to 51.n) of the corresponding summator (5.1 to 5.n), whose phase output (54.1 to 54.n) is coupled to the corresponding input (60.1 to 60n). n) a decoder (6) whose each positive output (61.1 to 6n.l) is connected to a corresponding positive output (041.1 to 04n.l) of the circuit, each negative output (041.2 to 04n.2) of which is connected to a corresponding negative output ( 61.2 to 6n.2) of the decoder (6).