CS236377B1 - Circuit wiring to reduce the effect of restoring dynamic memory memory information to the data transfer rate - Google Patents

Abstract

The solution relates to the field of computer technology and solves the problem of increasing computer performance. This problem is solved by, based on an external request for the renewal of stored information, under certain conditions, invoking the renewal of stored information more often than is absolutely necessary, but in such a way that the cycles of renewal of stored information and the working cycles of the operating memory do not coincide. The connection can be used in all computers using dynamic operating memories.

Description

The invention relates to circuitry for reducing the effect of recovering the memory information of the dynamic memory on transmission speed; give.

Known prior art connections for generating a memory information retrieval request utilize either monostable flip-flops or clock pulses to determine the interval between requests that generate the memory information retrieval request at fixed time intervals. This request often conflicts with a request for a memory duty cycle, so that a duty cycle is delayed, and thus an increase in the memory time of the memory.

This disadvantage is overcome by the circuitry for reducing the number of coincidences between the parquet information refresh requests and the duty cycle requests of the present invention, wherein the first output of the programmable counter is connected to the first input of the summation member, the second input is connected to the second output. Programmable Counter. The third input of the summation member is accompanied by an external request for a recovery information recovery cycle. The output of the summation member is associated with the first register entry of a request for a cycle of recovering the stored information, the second input of which is connected to the first input of the programmable counter and is connected to a clock clock. The output of the stored information recovery request register is coupled to a second programmable counter input and is routed to other circuits.

The circuitry for reducing the effect of recovering the stored information of the dynamic operating memory of the invention strongly reduces the coincidence of requests for the refreshed information recovery cycle and the memory duty cycle by providing a refresh cycle

- 2 236 recalls the stored information more frequently, but at a time when it is not possible to request a duty cycle. This enables immediate application of the memory duty cycle, thus increasing the data transfer rate with the memory and thus the performance of the entire system.

The attached figure shows one possible circuit connection according to the invention.

It consists of a programmable counter JL, an evaluation circuit 2, and a register 3 of requests to recover the stored information.

The clock input 120 of the programmable counter 11 and the clock input 320 of the request register of the refreshed information recovery cycle 3 are clocked from input 02. The first output 11 of the programmable counter 1 is connected to the first input 210 of the evaluation circuit 2 and the second output 12 of the programmable counter 1 connected to the second input 220 of the evaluation circuit 2, the third input 230 of which receives an external request from the input 01 for a recovery information recovery cycle. The output 21 of the evaluation circuit 2 is connected to the data first input 310 of the memory information recovery request register 3, the output 31 of which is connected to the reset first input 110 of the programmable counter 2 ^{and to the} output of the entire circuit 03.

The programmable counter JL counts the clock pulses and after the set time has elapsed, it outputs a signal to the evaluation circuit 2 at the first output 11, which evaluates it and loads it into the register 3 of the information recovery cycle. . The second output 12 of the programmable counter 1 specifies a condition in which an external request for a refreshed information recovery cycle from the external request input 01 is applied. This external request causes the memory information to be refreshed before the time set in the programmable counter JL has expired, so as to avoid coincidence of the memory information refresh request and the memory duty cycle request.

The wiring according to the invention can be advantageously used in all computers using dynamic operating memories.

Claims (1)

Circuit for reducing the effect of recovering the memory information of the dynamic memory on the data rate, characterized in that the first output (11) of the programmable counter (1) is connected to the first input (210) of the evaluation circuit (2), the second output (12) of the programmable the counter (1) is connected to a second input (220) of the evaluation circuit (2), the third input (230) of which is connected to the input (01) of the external request for refreshing the stored information, with a first input (310) of the stored information recovery register (3), the output (31) of which is coupled to the output (03) of the entire circuit, and the first input (110) of the programmable counter (1) connected to a second clock input (320) of the register (3) of the request for recovering the stored information and at the same time to the input (02) of the clock pulses.