CS233797B1 - Connected to create multi-level source synchronization pulses - Google Patents

Abstract

The invention relates to the implementation of a multi-level power supply; with pulse regulation. The circuit allows for the creation of suitable synchronization pulses for the excitation of the control thyristors of the secondary levels of a multi-level power supply, in which the B26QD integrated circuit is used to stabilize the main level. / The synchronization pulses are created in advance of the power pulses of the converter, which allows for the elimination of the turn-on time of the control thyristors of the secondary sections. The circuit can be used in the implementation of a multi-level power supply, where it allows for the reduction of the current and voltage stress on the magnet elements.

Description

SUMMARY OF THE INVENTION The invention relates to a circuit for generating synchronization pulses of a multi-level pulse control power supply in which a special control circuit type B260D is used to control the main level.

In the implementation of a multi-level power supply with a common converter, thyristors can be used to control secondary voltage levels. Thyristors have a relatively long turn-on time. This time can be eliminated when the drive pulse is applied in advance of the drive power pulses. However, if the main power level feedback circuit is implemented using the B260D integrated circuit, suitable synchronization pulses are not available in advance.

This problem solves the circuitry for generating synchronization pulses of a multi-level power supply according to the invention, wherein the IC driver output is coupled to the main gravity driver input, wherein the astabular multivibrator output is coupled to the IC integrated sync input. connected to the input of the delay circuit, the output of which is coupled, and the second input of the NAND gate, the first input of which is coupled to the drive output of the integrated circuit, while the output t of the NAND gate is coupled to the input of the secondary level control circuit.

The circuitry of the present invention generates pulses suitable for synchronizing the secondary levels of a multi-level power source and well in advance of the main level power pulses.

This virtually eliminates the switch-on time of the secondary level control thyristors, which allows to reduce the current 1 voltage stress of the drive elements.

The principle of the invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of the circuit according to the invention and FIG. 2 shows the respective pulse waveforms.

Fig. 1 shows an example of a circuit for generating synchronization pulses of a multi-level source and one main and one secondary level, where the drive output 115 of the integrated circuit 1 is connected to the input 51 of the main level drive circuit 6. The output 21 of the astable multivibrator 8 is connected to the synchronization input 109 of the integrated circuit χ and the input JX of the delay circuit J. Its output 32 is connected to the second input 64 of the gate.

NAND whose first input £ χ is coupled to the drive output 15 of the integrated circuit χ. The gate output £ 2 of the NAND gate is connected to the input £ l of the secondary level control circuit £

The main level excitation circuit 6 generates excitation pulses for the switching element of the multi-level source converter. The secondary level control circuit 6 performs additional control by a thyristor switched synchronously with the operation of the inverter.

Integrated circuit X is a circuit type B260D, which contains basic circuits for the control and protection of power supply and pulse control. Its operating frequency is determined by the astable multivibrator 8 via the 10? Synchronization input. Descending edge of astable;

• The logic zero level at the second input £ 2 of the gate NAND sets its output £ 1 to the logic one level. This allows the secondary level control circuit 6 to start actuating the thyristor control.

At the moment when the output 21 of the multivibrator 2 goes to logic 1 level, with a certain delay, given the intrinsic stroke of the integrated circuit χ, the main level control pulse on the driver output 115 of the integrated circuit X starts to generate a control pulse. The delay circuit 2 delays the leading edge of the astable multibribron 2 until the logic zero level is already sufficiently overlapped at the gate input £ 1. Thus, the positive synchronization pulse at gate NAND output 22 continues until the main level control pulse at the excitation output 115 of integrated circuit 1 is complete. Then, the first gate NAND input 41 goes to logic level 1 and its output 43 to logic zero level.

The operation of the entire circuit is also evident from the pulse waveforms of Figure 2, where the waveforms at the indicated circuit points of Figure 1 are indicated. The synchronization pulses generated at the NAND gate output 43 can be used to control any number of secondary levels of the multi-level source.

The circuit according to the invention is suitable for realizing a multi-level power supply and pulse control, where the B260D circuit is used to control the main level and thyristors are used in the secondary levels.

Claims (1)

A circuit for generating synchronization pulses of a multi-level source, wherein the IC output is coupled to the main level driver input, wherein the astable multivibrator output is coupled to the IC integrated sync, characterized in that the astable multivibrator output (21) is further connected to the input (31) of the delay circuit (3), the output (32) of which is connected to the second input (42) of the NAND gate (4), the first input (41) of which is connected to the drive output (115) of the integrated circuit (i) wherein the output (43) of the NAND gate (4) is connected to the input (6i) of the secondary level control circuit (6).