CS225501B1 - Control unit of programmable logical circuit - Google Patents

Description

The invention solves a control unit of a programmable logic circuit.

and

Sequential logic circuits are designed according to classical theory on a case-by-case basis by means of a flowchart, minimizing the number of internal states and then assembling from basic gates

NOR, NAND and flip-flops: D-circuits, JK-circuits, RS-circuits. The sequence logic circuit thus determined fulfills the function specified by the flowchart for which it was designed. The disadvantage of these circuits is to redesign the whole circuit if the circuit diagram of the circuit changes.

This disadvantage does not have the so-called programmable logic circuits, whose properties can be changed by appropriately occupying the program memory. The peripheral arrangement of such a circuit remains the same. It is therefore possible to manufacture these circuits in series and then program their memory to determine their properties.

The complexity of the programmable circuit and its individual blocks depends on the number of inputs, outputs, and internal states that can be realized by such a circuit. Furthermore, the complexity of the circuit depends on the design of the control unit, which should be designed so that the shortest program words can be used and the instructions selected for easy implementation.

This problem is solved by the programmable logic control unit according to the invention. It consists in that it consists of a first decoder whose instruction outputs are connected to inputs of a controller having a one-bit register and a comparator register with a control logic and the output of that controller is connected to the first input of the second decoder.

22S SOI

The control unit according to the invention is part of a programmable logic circuit based on a single bit processor. This circuit does not replace a microcomputer controlled by a classical microprocessor, but it will serve very well for simpler logic control tasks. The control unit is easy to implement from available components.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates the wiring of a control unit; and FIG. 2 shows a block diagram of a programmable logic circuit.

The control unit of the programmable logic circuit of FIG. 1 is formed by a first decoder 1, the output of which is connected to the inputs of a controller 3 comprising a single-bit register A and a comparator register B with control logic. The output of the controller 3 is connected to the first input of the second decoder 2.

The programmable logic circuit based on the single-bit processor of FIG. 2 is made up of the control unit 4 of FIG. The conditional jump signal output of the second decoder 2 of the control unit 4 is connected to the control input of the instruction counter 6. The first input and the first output of the logic variable controller 3 are connected to the logic variable memory 7 - RAM, the second input of the logical variable controller 3 is connected to the input multiplexer 8 and the second output of the logical variable is connected to the output decoder 9. interconnected via addressing and control wires.

The control unit according to the invention operates with a 12-bit program word. The first four bits are used to decode the instruction, and the last bit determines whether to make a conditional jump or one of the other instructions. This decoding is performed by the second decoder 2 according to the information from the output of the controller 3. The other instructions are decoded in the first decoder 1. The decoded instructions are fed by eight wires to the controller 3. The controller 3 comprises a single bit register A and a comparator register B with control logic it processes the signals from the inputs of the logic variable controller 3 and outputs the output instructions to the outputs of the logic variable controller 3. The 11-bit word is intended to be loaded into the counter 6

225 501 instructions for implementing the conditional jump and addressing the input multiplexer 8, the output decoder 9 and the logic variable memory 7 - SAM.

The following table explains the instructions, their coding and the program word arrangement of the control unit according to the invention:

Number * instr Program word The meaning of the instruction , 0123456789 10 11 Symbolic 1. Conditional jump address 0 With A = B, the address jump in bits 0-10 is made and the contents of register £ are reset 2. Address of the parotid cell in RAL1 0 0 0 AND A — RAM The information from register A is transferred to memory FRAME 3. r 0 0 AND From — RAM Negated information from register A is transferred to RAM 4. The address of the steam cell in RAM 0 0 AND AND RAM — A Information from RAM is transferred to the reg 5. AND 0 AND AND ± £ ΑΪ »ί —A Negated information from reg. A. is transferred to reg. A 6. Multi- plexor 0 AND AND AND X · —A The input information is transferred to the reg 7. AND AND AND AND XA Negovaná inf. from input it is transferred to register A 8. Address stopního decoder 0 AND 0 AND A —Y The information from Reg. A is transferred to the output 9. AND AND 0 AND A — Y The negated information from register A is output 10. AND AND AND Ί AND Λ AND AND 0 AND AND AND 0 — A Registry A is reset 11. AND AND AND AND AND AND AND AND AND AND AND AND I —A I — B Logical 1 is introduced into both register A and comparative register B.

225 501

The screening unit according to the invention can serve to realize a programmable sequential logic circuit having a max.

255 different input signals, max. 256 output signals, max.

256 internal states and max. 2048 program instructions. Said programmable circuit is further usable as a logic processor for realization of sequential logic circuits needed especially for connection of functional units of measuring systems as well as a final automata for control of industrial processes.

Claims (1)

A programmable logic control unit, characterized in that it consists of a first decoder (1) whose instruction outputs are connected to inputs of a controller (5) provided with a one-bit register (A) and a comparator register (B) with control logic, the controller (5) is connected to the first input of the second decoder (2).