CS217036B1 - Wiring a Circuit for Digital Control of Screen Shift Deflection at Slow Frame Decay - Google Patents

Abstract

The invention relates to a sensor system that allows for better visualization of the image during slow imaging using multiple two-dimensional interlacing. The circuit consists of a binary counter with a length of 2.1 bits connected to two digital-to-analog converters. The essence of the circuit is that the counter, starting with the lowest-weighted inputs, is connected to the outputs of the first and second converters with the highest-weighted inputs, the lowest inputs of which are connected to the highest-weighted outputs of the counter, and the output of the converters is connected to the vertical and horizontal inputs of the screen. The circuit is intended for various raster imaging systems with digital control, where it is necessary to select slow beam deflection from the signal point of view, e.g. scanning electron microscopes, etc.

Description

VAŠINA PETR RNDr., FRANK LUDĚK RNDr, BRNO (^ Connection of circuit for digital control of screen beam deflection during slow frame decomposition)

BACKGROUND OF THE INVENTION The present invention relates to a sensor system which makes it possible to better visualize an image during slow scanning by means of multiple two-dimensional interleaving.

The connection consists of a binary counter with a length of 2.1 bits connected with two digital-to-analog converters.

The essence of the connection is that the controller, starting from the lowest and the lowest weights, is connected and the highest and the first and the second converter outputs are connected, the lowest inputs of which are connected to the highest outputs of the reader and the converter output is connected to the vertical and horizontal inputs of the screen.

The wiring is designed for public scanning imaging systems and digital control, where it is necessary to select a slow beam deflection, eg scanning electron microscopes, etc.

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BACKGROUND OF THE INVENTION The present invention relates to circuitry for digital control of screen beam deflection in normal frame decomposition and a scanning system to allow for better visualization of images at slow frame decomposition using multiple two-dimensional interleaving.

In a wide variety of imaging systems, especially in the case of low video signal levels, very slow frame decays and frames of seconds to tens of seconds are used. Another reason for slowing down the degradation may be the transmission of video information through a slow communication channel. In these cases, the visibility of the image requires the use of a widescreen or image memory for convenient viewing. However, both solutions are very costly. In doing so, we often settle for a rough overview of the state of the image - for example, in a physical device of an image generating image signal, it is sufficient to have only a small number of pixels available to set up and only a dense pixel network can be selected. Therefore, deflection circuits with at least two decomposition standards are required for this purpose. The introduction of more video standards increases the complexity of the circuit, and as the bias rate changes, the dynamic properties of the system also change, causing further difficulties.

These disadvantages are eliminated by the circuitry of the digital control of the deflection of the monitor screen at a slow frame decomposition consisting of a binary counter having a length of bits and two digital-to-analog converters, each of which has a bit length based on the fact that inputs of the first converter are connected with the lowest ¹ outputs of the counter, whose higher ¹ outputs are connected with the highest ¹ inputs of the second converter, the highest output of odd numbers starting with the first highest counter output is connected with the lowest inputs of the second converter and the highest outputs even numbers starting with the second highest output are associated with the lowest input weights of the first converter, while the output of the first and second converters are connected with the horizontal and vertical inputs of the screen.

the digital deflection circuit has the following main advantages: the deflection circuit produces a sequence for observing approximately equivalent circumferences with a factor of one, and by composing nt of these sub-images in some suitable medium, such as a photographic layer, we get a complete image with a sufficiently dense mesh ; the circuit is quite simple and can be controlled as a microcomputer, shifting the program counter to process the previous sample of the video signal, tsk only by a frequency source that can have a single frequency, so that the dynamic performance of the system is minimized.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is illustrated in more detail by the accompanying drawing, in which FIG. 1 shows the basic connection and FIG. 2 shows a practical example for producing a 4 x 4 interleaving of a 256 x 256 pixel image.

the basic circuit in Fig. 1 consists of a binary counter C with a length of 2.1 bits, where Islog ₂ N, where K is the number of lines of the picture and the number of picture lines at the same time.

Another part of the basic connection are two digital to analog converters P1.P2 containing * inputs, divided into two groups o and inputs, where i «= log ₂ (N / n), where p

n is the number of point interleavings of the image in both directions, and n is the number of sub-images. In practice, the 256x256, 512x512, 1024 x 1024, 2048 x 2048 and 4096x4096 pixel standards are suitable.

To improve observation of the obstruction at the ratio of the luminance signal generated, a more uniform coverage of the screen can be achieved by creating eubs and spot scans of 2x2, x 4 »8 x 8, 16 x 16, 32 x 32. In these examples, the deflection voltage is generated by 8,9,10 , 11 resp. 12 bit digital to analog converters connected to counter by 16,18,20,22 resp. 24 bit. If we choose the standard 256 x 256 points and 4x4 point interleaving, then we use 8-bit converters and a 16-bit counter for deflection. The converter inputs are divided into a group of 6 bits with a higher weight and a group of the two lowest bits.

Jal; As can be seen from FIG. 1, the basic circuitry is indicated in flow modification to be equally usable with a counter having a length over the entire range of bits. The counter C to the input terminal CJS mátéýy twelve marked and indicated dotted next ⁿ outputs, wherein the weighting nejnižřích ¹ outputs Qo, Qx is connected to ΰχ_χ © and weight inputs Djei nejvyěšími ^{1, d} i ₊ II by treatment ®I ® ^F-1 converter Pl. Then more by weight yyšších * O * Q 'and ^Q »L ^{Z <21-} 2 ^and is connected to counter C and the highest ^weight-1 inputs D ^, p ^ .Z _{second převodníltu} pg. h _epro that the weight-nejvyěší outputs of odd numbers, starting beer nejvyřřím output Qgl-L '^ 21-3 to Qgi + l £ 3 * Counters epo3® ® by weight of ⁿ lowest input DQ ϋχ to Οχ_χ_χ second transducer P2, while the weight-nejvyěší even number outputs, starting with the second highest output ^Q 2I-2 * QgI-4 ^to ®2i ^B P ° 3 ^{en 8 I_i of the} lowest weighted inputs Do, D _x to Dj.2. _{x of the} first transducer Pl. The output V1 and V2 of the first and second transducers P1 and P2 are connected to the horizontal and vertical inputs X and Y of the screen. The example of connection in Fig. 2 consists of a 16-bit counter C, whose clock input 1 is supplied with a clock frequency determining the deflection rate, and two 8-bit digital analogue converters P1, P2, whose outputs produce sawtooth deflection waveforms for both six output Q Q Q _x, Q 0 · ^? »Q4» Qg 3 "is connected to the six inputs to solve D _g, Dg, D ^, Dg, the first converter Pl. while six other higher outputs ®10®ll '^ * ^e connected to the six inputs of the higher D _2, D ^, D ^, Dg, Dg, D ^, the second transducer P2 and thirteenth ®12 counter output C is connected to a second input Dl of the first P1 converter. The fourteenth output i and of counter C is connected to the second input ΰ _{χ of the} second converter P2. the fifteenth output Q _X 4 of the counter C is connected to the beer input Dq of the first converter P1 and finally the sixteenth output Q _X g of the counter C is connected to the first input ϋθ of the second converter P2.

During operation, the device operates as follows: The output voltage at the outputs of transducers P1 and P2 is given by the combination of logic levels at their inputs D _Q to D? and takes 256 different values, which indicate the row number and possibly the columns at the P2 converter and the point number in the row at the P1 converter. h «start operation, all the outputs% - ^z * 15 ^to the counter C in a low logic level, indicating that the voltage at the output of the converter Pl. P2 corresponds to the first point of the first line. Upon the arrival of the first clock pulse at the counter C input, the output status changes to a phial, Q _x to Q _X g> 0, causing a voltage drop at the output of the first transducer P1 to a value corresponding to point 5 of the first line. The second clock pulse increases the counter state to <2 _χ = 1 until Q _x g °>, which corresponds to point 9 of the first line. This ee further repeats until the arrival of the 63rd clock pulse when the output voltage of the first converter P1 corresponds to the 253rd point of the first line.

The 64th clock pulse changes the counter state so that βθ = 1 and the other counter C outputs are zero, which corresponds to the 1st point of the fifth line. In this way, the first subframe is sequentially created up to a counter state Q to _Q 1 · 1 · 1, Q ₁₂ → 15, ^which does not ^occur after 4 J 95 clock pulses;

the 253rd line of the image corresponds to this state. Thus portraying a network řidří four times in both directions, a complete picture of the 64 lines of 64 pixels, after following the imaging pulse ^Q 12 ^el vřechny and other counters 0 outputs are zero. In this state, another sub-picture is drawn containing the 3..7 .. to 255 points. After 4096 clock pulses, the counter status changes accordingly. that Q ^ y1 * other outputs - 0 and thus a sub-picture composed of the 1st, 5th to 253rd points from lines 3..7 .. to 255 is rendered. All 16 different states and a total of 16 slightly offset images are created, which together form a complete image with 256 lines of 256 points.

Wiring to improve image observability at very slow frame decomposition is useful in all digital imaging scanning imaging systems where slow beam deflection is required, such as in some electron microscopy scanning applications, in Auger electron spectroscopy imaging mode and in all longer spectroscopic methods with two-dimensional imaging of the sample.

Claims (1)

SUBJECT OF THE INVENTION Digital image deflection control circuitry for slow frame decomposition consisting of a binary counter * b-bit length e consisting of two digital-to-analog converters, each of which has a bit length, characterized by having a maximum of ¹ inputs ( ^D I 1 1 · ^D l_i + l ^D x_j) P ^ or converter (P1) is connected and weighted by ¹ lowest outputs (Q0 »Q1 to counter (C), whose weighted ¹ outputs (QitQ _{i + 1)} is connected to weighted ¹ inputs ^D IP of the second of the converter (P2) whereby the most significant weights of odd numbers start from the first highest output (Qgl-1 »^ 21-3 ^to ®2i + 1 ^ of the dial (C) is connected to the lowest inputs (D _Q , D ^ to the second converter) ) and the most massive output of even numbers starting with the second most intense output ($ 21-2 '$ 21-4 to Qg ^) is associated with ^{lei of the} lowest weight inputs ( ^d q » ^d ^ up to the first converter, while the output (V I and V2) of the first and second converters (P1 and P2) are connected by the ε horizontal and vertical input (X and Y) of the screen.