KR950002319B1 - Picture display device - Google Patents

Abstract

The circuit for displaying the digital image according to the weighting value of the image signal with time division method includes an A/D converter (5) converting the analog image signal to the digital one, a pair of shift registers (21,22) inputting the image signal in series as shifting it and outputting them in parallel alternatively, a pair of field memories (24,25) storing the outputs into the sub-field regions according to each weighting value, a pair of address controllers (26,27) writing and reading the data to/from the corresponding field memory, and a switching circuit (23) switching the reading/writing pass of the data.

Description

Image data processing device for flat panel display

1 is a block diagram of an image data processing apparatus of a conventional flat display device.

2 is a block diagram showing another embodiment of an image data processing apparatus of a conventional flat display device.

3 is a block diagram showing a preferred embodiment of a planar image data processing apparatus according to the present invention.

4 is a waveform diagram of each part of FIG.

5 is a memory map of the RAM of FIG.

* Explanation of symbols for main parts of the drawings

1: antenna 2: tuner

3: image intermediate frequency circuit 4: image detection circuit

5: A / D conversion circuit 7: Synchronous separation circuit

8: generating circuit 11: hot wire driving circuit

12 display device 13 ring counter

14: planetary drive circuit 20, 21: shift register group

24: selector 23: switching circuit

24, 25: field memory 26: address selector

27: address generator 28: latch selector

29: first latch circuit 30: first latch circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a flat display device image data processing device, and more particularly, to a flat display device image data processing device for time division display by weight of a digital image signal in order to give a gray level to a television image.

Recently, in order to overcome the limitations of the CRT due to the trend toward the enlarged display of TV screens, the development of a large flat panel display device is being conducted. Japanese Patent Laid-Open Publication No. 62-1470 discloses a technique for controlling flat-panel display in which the scanning method is used as a linear sequential scan in order to give a gray scale to a display image, and the division of display periods within the one-line period is controlled. have.

In the Japanese patent, since the image data processing configuration of the conventional flat image display device is very complicated and requires a large number of components, the miniaturization of the data processing circuit configuration is difficult and the connection with the flat display device is difficult due to the installation of a plurality of transmission lines. Pointing out that, a data processing circuit configuration using a random access memory is proposed.

That is, the Japanese patent stores m sampled digital signals of m bits in a random access memory, and sequentially reads m bits having the same weight among the stored data by weight and transmits them serially to the driving unit of the flat panel display device. It was configured to apply to a flat panel display device in parallel. Therefore, the configuration of the image data processing circuit can be simplified and the transmission line can be greatly reduced. However, since the Japanese patent method reads data stored in a random access memory in units of m bits of the same weight, substantially parallel conversion of image data is performed in the memory and memory access time is required at a very high speed. It is difficult to employ an access memory. This is because parallel to serial conversion is very difficult in RAM and the data that can be converted is extremely limited. In addition, since the gray scale display is possible for each horizontal line by adopting the linear sequential scanning method, gray scale display is possible, but the whole display duty ratio is the inverse of the vertical resolution, which has a disadvantage in that the luminance is very low.

A more detailed description of the prior art will be described later.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flat display device image data processing device capable of processing image data using only conventional general-purpose elements in order to solve the problems of the prior art as described above.

In order to achieve the above object, the present invention provides an image data processing apparatus of a flat panel display device, comprising: a synchronous detector for detecting a synchronous signal from an analog video signal; A timing signal generator for inputting the synchronization path to generate a plurality of timing signals; An analog digital converter (5) for converting the analog video signal into digital video data in response to the first timing signal (T1); In response to the second to fourth timing signals T2-T4, as long as the image data is serially input to one another and the plurality of digital image data shifted to the other are output in parallel, A pair of serial input-parallel output shift registers 21 and 22; A pair of field memories (24, 25) for storing a plurality of data supplied from a shift register section for outputting data in parallel in response to the fifth timing signal (T5) in subfield areas corresponding to each weight; In response to the sixth timing signal T6, data supplied from one of the pair of serial input-parallel output shift register units is written into a corresponding one field memory, and the data written to the other field memory is sub-written. Address control units 26 and 27 for reading in units of fields; In response to the first timing signal T1, a path is switched so that data is alternately written from one of the shift registers to a corresponding one field memory, and data read from the other field memory is first latched. It characterized in that it comprises a switch circuit section 23 for switching the passage to be supplied to the circuit section (29).

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, the prior art will be described in detail in order to help the understanding of the present invention.

Referring to FIG. 1, a signal from the antenna 1 is supplied to the tuner 2 so that a desired channel is received and the received signal is supplied to an image intermediate frequency circuit 3 to become an image intermediate frequency signal. Is supplied to the video detection circuit 4, and the video signal S is taken out. This video signal S is supplied to the 8-bit A / D conversion circuit 5, for example. The conversion circuit 5 converts the parallel binary signal D1 of 8 bits (LSD, 2D, 3D, ..., MSD) in response to the gray scale, and the digital signal D1 is transferred to the latch circuit 6. Supplied. The video signal S is supplied to the synchronization separating circuit 7 so that the vertical synchronization signal and the horizontal synchronization signal are separated, and this synchronization signal is supplied to the timing signal generation circuit 8. In the generation circuit 8, a timing signal T1 of 256 times the horizontal frequency is formed, and the timing signal T1 is supplied to the conversion circuit 5 and the latch circuit 6, and this timing signal T1. In synchronism with this, the digital signal D1 is read out. This digital signal D1 is supplied to the shift register 9. The shift register 9 has registers arranged in a matrix of eight rows and 256 columns. At the same time as the digital signal D1 from the latch circuit 6 is supplied, the timing signal T1 is supplied so that the digital signal D1 is sequentially shifted in the direction of the arrow a at the timing of the timing signal T1 for each bit. Then, the video signal for one horizontal period is written. In the generating circuit 8, the horizontal synchronizing signal immediately after the horizontal period in which the timing signal T1 is generated and the two subsequent horizontal periods 2H are divided into 255 equal parts and the first, third, seventh, and fifteenths thereof. The digital signal T2 corresponding to the second, thirty-first, 63rd, and 127th is formed. The timing signal T2 is supplied to the shift register 9, and the signal written therein is sequentially shifted in the direction of the arrow b in the drawing as the timing of the timing signal T2, and is 256 bits for each bit of the digital signal D1. The readout is sequentially performed from the LSD side as the parallel signal D2.

At the same time as the digital signal D2 is supplied to the latch circuit 10, the timing signal T2 is supplied to sequentially latch the digital signal D2 at the timing of the timing signal T2. The latched digital signal D2 is supplied to the drive circuit 11, and the digital signal D2 is converted into an appropriate voltage and supplied to each of the heating wires of the display device 12. In the generation circuit 8, a timing signal T3 corresponding to the horizontal synchronizing signal immediately after the termination of the timing signal T1 is formed, and the timing signal T3 is supplied to the ring counter 13 of 120 bits. An output signal which sequentially shifts every two horizontal periods is formed at 120 output terminals, and this output signal is supplied to the drive circuit 14, converted to an appropriate voltage, and supplied to each destination line of the display device 12.

Therefore, in this apparatus, the digital signal D2 corresponding to each LSD of the digital signal D1 for one horizontal period is displayed in the first 1/255 (= 2H / 255) period in the horizontal period corresponding to an arbitrary destination. Then, display corresponding to 2D is performed in the period of 4H / 255, and corresponds to 3D to 7D and MSD in the following 8H / 255, 16H / 255, 32H / 255, 64H / 255, 128H / 255, 256H / 255 intervals. Is performed.

However, in this apparatus, since a large number of elements are required for the configuration of the shift register 9, it is difficult to form in 1C of one package. In addition, this requires more than 256 transmission lines when connecting the substrate on which the display device 12 and the latch circuit 10 and the like are mounted and the separate substrate having the shift register 9. It is difficult to provide many such transmission lines.

Referring to FIG. 2, a planar image display apparatus is shown which enables the in-phase display with a simple configuration in order to solve the problems of the apparatus of FIG. In the same figure, the digital signal D1 corresponding to the video signal S from the latch circuit 6 is supplied to the selector circuit 15. In the generation circuit 8, the timing signal T1 is multiplied by eight in one horizontal period, and the transfer signal is counted. The control signals Q1 to Q3 of three bits varying from 000 to 111 in one week period of the timing signal T1. The control signals Q1 to Q3 are supplied to the selector circuit 15 so that the digital signal D1 from the latch circuit 6 is sequentially taken out for each bit, thereby becoming a serial number (digital signal) D3. This digital signal D3 is supplied to the data input terminal of the random access circuit 16. The RAM 16 has one address composed of eight bits, and this address is designated as 256 addresses. In the generation circuit 8, the timing signals T1 are counted in the same horizontal period to form 8-bit control signals Q4 to Q11 that vary from (00000000) to (11111111). These control signals Q4 to Q11 are formed. The control signals Q4 to Q11 are supplied to the address correct terminal of the RAM16. The control signals Q1 to Q3 are also supplied to the column designation terminal of the RAM16. In the generation circuit 8, a timing signal T4 having a high potential in the same horizontal period is formed, and this timing signal T4 is supplied to the write and read control terminals of the RAM16, and this timing signal T4. In the period of high potential, the RAM16 enters the write mode.

In RAM16, the digital signals D1 for one horizontal period are written to addresses 0 to 255 corresponding to the 0 to 7 columns of each address and the bits of the LSD to MSD of the digital signal D1. In addition, the timing signal T4 becomes low potential and the RAM16 goes into the read mode in one horizontal period in the above-described inverse. At the same time, in the generation circuit 8, a timing signal T5 delayed 1/255 (= 2 / 55H) of the Q2 horizontal substrate from the timing signal T2 is formed, and this timing signal T5 is counted to control signals. Q1 to Q3 are formed. The timing signal T6 obtained by dividing this period by 256 equally in the period of 2H / 255 is formed following the horizontal synchronization signal immediately after the timing signal T1 ends and the last (eighth) timing signal T5. The signal T6 is counted to form the control signals Q4 to Q11. As these signals are supplied to the RAM16, following the horizontal synchronizing signal, they are read out as a column signal and a serial signal (digital signal) D4 corresponding to the LSD of each address in the period of the timing signal T6. Following the timing signal T5, the period of each timing signal T6 is 2D, 3D,... The column signal corresponding to the MSD is read out as the digital signal D4. The digital signal D4 is supplied to the serial input terminal of the shift register 17 in one row and 256 columns, and the timing signal T6 is supplied to the digital signal D4 at the timing of the timing signal T6. 17). The 256-bit signal is written to the shift register 17, and the digital signal D2 is read out to the parallel output terminal of the shift register 17. At the same time as the digital signal D2 is supplied to the latch circuit 10, the timing signal T5 is supplied, and the digital signal D2 is sequentially latched at the timing T5. The configuration is the same as that of the first degree.

Accordingly, the apparatus of FIG. 2 has a digital signal D2 corresponding to each LSD of the digital signal D1 for one horizontal period in the first 1/255 (= 2H / 255) period within the two horizontal periods corresponding to any destination. The display is followed by a time-modulated display corresponding to the weight of each bit. The lines displayed every two horizontal periods are sequentially changed to display an image for one field. In this case, the shift register 17 can use 32-bit conventional ICs which are serially input and parallel-output, for example, it is possible to constitute 256 packages of 8 bits. Furthermore, the digital signal D4 supplied from the RAM 16 to the shift register 17 is transmitted to one transmission line.

However, in the above-described apparatuses of FIGS. 1 and 2, the display of one field is completed by time division display by the weight of the digital signal for each horizontal period by the linear sequential scanning method, so the luminance is very low since the total display duty ratio becomes the inverse of the vertical resolution. . In the apparatus of FIG. 2, the digital signal is converted into a serial digital signal for each weight in parallel in the RAM. In reality, however, the data stored in RAM is very difficult to convert parallel data into serial data, and the data that can be converted are extremely limited. Therefore, fast access operation is required. For this reason, it is difficult to increase the duty ratio at which pixels emit light on the display panel, which makes it difficult to improve the luminance.

Referring to FIG. 3, in a preferred embodiment of the present invention, a flat image display apparatus in which luminance is improved by time-dividing by subfield units in a simple configuration and displaying one field is shown.

In the same figure, the digital signal D1 corresponding to the video signal S is supplied to a pair of shift register groups 20 and 21. One shift register group consists of eight shift registers for serially inputting 8-bit digital signals in parallel. These sixteen shift registers are sequentially selected by the selector 22 to write the digital signal D1. The selector 20 receives the timing signal T2 from the generation circuit 8. This timing signal T2 is synchronized with the rising edge of the timing signal T1. The generation circuit 8 also generates timing signals T3 and T4 and supplies them to the shifting input terminals of the shift register groups 20 and 21, respectively. The timing signals T3 and T4 are alternately formed in eight pulse units of the timing signal T1 as shown in FIG. Accordingly, while the digital signal D1 is written to the first shift register group 20, the digital signal D1 simultaneously written to the second shift register group 21 is read out while being sequentially shifted from the MSD to the LSD. . Therefore, the first and second shifting register groups 20 and 21 are repeatedly written and read alternately with each other. The digital signals D2 read out from the shift registers 20 and 21 consist of eight bit signals for each weight from their MSD to LSD in units of eight digital signals D1.

The digital signal D2 is supplied to the pair of field memories 24 and 25 via the switch circuit 23. The switching circuit 23 receives the timing signal T1 from the generation circuit 8 and performs switching control. The field memories 24 and 25 are divided into eight subfield areas as shown in FIG. 5, and these eight subfield areas correspond to the respective weights of the 8-bit digital signal D1. The digital signal D2 through the switching circuit 23 is sequentially stored in the corresponding subfield area. The digital signal D2 is stored in the first field memory 24 and the digital signal D2 stored in the second field memory 25 is read out through another channel of the switching circuit 23 in subfield units. do. Therefore, the pair of field memories 24 and 25 alternately write and read the digital signals D2 in units of fields. These field memories 24 and 25 are supplied with the timing signal T5 from the generation circuit 8 to their write / read control terminals. This timing signal T5 is a signal obtained by dividing the vertical synchronization signal by 1/2. The field memories 24 and 25 receive the address signals generated by the address generator 27 through the address selector 26, respectively. That is, the write address is MSD, 7D, 6D,... Addresses are sequentially assigned in units of subfields of 2D, LSD, and read addresses are sequentially assigned from the MSD subfield area to the LSD subfield area. The address generator 27 receives a timing signal T6 from the generation circuit 8.

The 8-bit digital signal D3 read out in units of subfields through the switching circuit 23 is supplied to the first latch circuit 29 in units of 8 bits to form parallel data of 256 rows. The first latch circuit 29 is sequentially selected by the latch selector 28 which counts the timing signal T7 supplied from the generation circuit 8 and generates a latch selection signal, thereby sequentially latching 8-bit data. The digital signals of one row and 256 columns latched in the first latch circuit 29 are transmitted to the second latch circuit 31. The second latch circuit 31 holds the digital signals of one row and 256 columns latched by the timing signal T9 from the generation circuit 8.

Therefore, in the present invention, the image signal for one field of eight gradations is displayed in the time width corresponding to the weight assigned to each subfield in units of eight subfields.

As described above, in the present invention, by time-division display in units of subfields, the luminance can be greatly improved as compared with the conventional method, and it is possible to use a general-purpose RAM.

Claims (1)

An image data processing apparatus of a flat panel display device, comprising: a synchronization detector for detecting a synchronization signal from an analog video signal; A timing signal generator for inputting the synchronization signal to generate a plurality of timing signals; An analog digital converter (5) for converting the analog video signal into digital video data in response to the first timing signal (T1); In response to the second to fourth timing signals T2-T4, as long as the image data is serially input to one another and the plurality of digital image data shifted to the other are output in parallel, A pair of serial input-parallel output shift registers 21 and 22; A pair of field memories 24 and 25 for storing a plurality of data supplied from a shift register for outputting data in parallel in response to the fifth timing signal T5 in subfield areas corresponding to each weight; In response to the sixth timing signal T6, data supplied from one of the pair of serial input-parallel output shift register units is written into a corresponding one field memory, and the data written to the other field memory is sub-written. Address control units 26 and 27 for reading in units of fields; In response to the first timing signal T1, a path is switched so that data is alternately written from one of the shift registers to a corresponding one field memory, and data read from the other field memory is first latched. And a switch circuit section (23) for switching a passage to be supplied to the circuit section (29).

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