GB2044051A - Resistive Interpolation of Extra Elements and Lines Between Stored Data - Google Patents

Abstract

Particularly in a computer generated display, to generate for example alternate 512 line interlaced fields of a 1024 line frame from 512 lines non-interlaced of stored data, with twice as many elements per line in the display, for an even field line numbered 2m, memory rows m-1 , m, m+1 are read out via gates 13, 14, 15 simultaneously at twice memory frequency into three 5-bit shift registers 18, 19, 20, alternate bits being stored as zero due to doubled frequency. For an odd field line 2m+1, memory rows m, m+1 are read via gates 13, 14 into registers 18, 19. Resistive networks 23, 22 with conductance weights nG as shown provide even field output at 26 and odd at 25, selected by a field- synchronized switch not shown. <IMAGE>

Description

SPECIFICATION Resistive Interpolation Network This invention is concerned with a circuit for generating from input data, at a first frequency, output data at a second frequency, and is particularly concerned with a circuit for generating video signals for the cells of a picture matrix from signals supplied from a smaller number of cells in a memory.

In certain situations where an operator must observe a computer-generated TV display at close quarters (e.g. less than one metre, say) it has been found that the normal 625-line CCIR TV standard is unacceptable, as the line structure appears too coarse. It is therefore desirable in such situations to employ a TV standard having more lines and it has been found that a system in which the visible part of the raster scan consists of 1024 lines is suitable in more ways than one. Such a system can display picture formed from a cell matrix of 1024 rows by 1024xA columns, where A=the aspect ratio of the display.

In many applications it is possible to store the picture in a memory matrix having only half as many rows and half as many columns as the displayed picture. This is advantageous because the size of the memory is only one quarter of what it would have been, and consequently there can be savings in basic memory cost, volume, power supplies and possibly also cooling requirements.

A further advantage is that the allowable memory cycle time is increased.

In order to generate a picture matrix having an apparent resolution of 2 rows2 c columns from a memory cell matrix of only rxc, it is necessary to generate additional video data by interpolation.

Imagine, for instance, a display matrix of I 024x 1024 cells in which only cells which are both in even-numbered columns and on evennumbered rows are represented directly in the memory matrix. The dimensions of the latter are therefore 512 x 512. Video data for the display cells on odd-numbered rows or columns may be generated by a logical decision process based on the data stored in the surrounding memory cells.

The rules for this decision process may be stored in a read-only memory or logic array.

The use of a read-only memory or logic array may present problems when it is desired to generate a 1024-line TV signal at a rate of 25 complete pictures per second. This is because the elements in each row of the displayed matrix have to be generated at high speed (i.e. about one element every 22 nanoseconds).

It is an object of the present invention to obviate or mitigate this problem by using a simpler interpolation technique based on weighted addition of memory cell data in a purely resistive network, and that is the subject of this patent application.

The present invention is a method of generating from input data, at a first frequency, output data at a second frequency, the method comprising supplying said data at the first frequency to at least two shift registers clocked at the second frequency and combining the signals at several outputs of the shift registers by means of a resistive network to form said output data.

The present invention is also a circuit for generating from input data, at a first frequency, output data at a second frequency, the circuit comprising means arranged in operation to supply said data at the first frequency to at least two shift registers having clock inputs, and an output line connected by means of a resistive network to at least several outputs of each shift register, whereby the data on said output line is at the second frequency determined by the shift register clock frequency.

The-present invention further provides a method of generating video signals for the cells of a picture matrix from data signals supplied from a smaller number of cells in a memory, the method comprising gating, at a first frequency, data from at least two outputs of a memory into at least two respective shift registers, clocking said shift registers at a second frequency, and combining, by means of a resistive network, the output signals at several outputs of at least two of said shift registers into said video signals.

The present invention further provides a circuit for generating video signals for the cells of a picture matrix from data signals supplied from a smaller number of cells in a memory, the circuit comprising at least first and second gates each having a clock input and a data input connectible with said memory, a respective shift register for each said gate and having a data input connected to the output of its respective gate, several outputs and a video clock input, and a resistive network connecting the outputs of at least two of the shift registers to a common output, whereby the video signals appearing at the common output at the frequency of the video clock comprise at least first and second signal trains each at the frequency of the memory clock and each consisting of a different combination of the data signals supplied to at least the first and second gates.

An embodiment of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a diagram of a circuit according to the present invention; Fig. 2 illustrates the output intensity patterns produced from various memory patterns by the circuit of Fig. 1; and Fig. 3 illustrates various video output signals produced from various memory patterns by the circuit of Fig. 1.

The circuit of Fig. 1 is interposed between a memory having a 512 x 512 matrix and a display matrix of 1 024x 1024 cells.

The memory is organised in such a way that it is always possible to read out in serial form the content of three adjacent rows simultaneously.

The output therefore takes the form of a 3-bit word comprising data from three cells arranged one above the other in the memory. All bits of the word are updated simultaneously at a rate compatible with the row scanning speed. This rate might typically be between 10 MB/s and 40 MB/s.

As in this embodiment the system employs dual interlacing of lines-i.e. a system has a field scanning frequency which is twice the complete picture frequency-if the memory is currently outputting the contents of, say, rows 3, 4 and 5, then on the next scan it must output rows 4, 5 and 6, and then rows 5, 6 and 7, and so on.

Suppose that the lines of the displayed picture are numbered 0 to 1023 from top to bottom, and the rows of the memory are numbered from 0 to 511. Now suppose that row 0 of the memory corresponds to line 0 of the displayed picture. It follows that row 1 will correspond to line 2, and row 2 to line 4, and so on. Now, because interlacing is employed, all the even-numbered lines will be drawn on the monitor during one field, and then all the odd-numbered lines will be drawn during the next field. For convenience, let these fields be referred to as the "even field" and the "odd field", respectively.

During an even field, whilst drawing, say, line 8, the memory will be made to output rows 3, 4 and 5. Line 8 corresponds to row 4 and therefore every even-numbered cell along the line will correspond in position directly to a memory cell, whilst the odd-numbered cells must be generated by some means of interpolation, making use of data not only from row 4 of the memory, but also from rows 3 and 5. The next line in the field will be line 10, and to generate this line it will be necessary to call on data from rows 4, 5 and 6 of the memory-and so on.

During an odd field all the video generated will be based on interpolation because all the lines effectively lie between the rows in the memory matrix. Thus to generate line 7, say, it is necessary to call on data from rows 3 and 4. The next line will be line 9, which will require data from rows 4 and 5.

Referring now to Fig. 1, serial data from the memory on lines 10, 11 and 12 is gated through respective gates 1 3, 14, 1 5 by the memory clock signal M on line 1 6 and then passes to three respective 5-bit shift registers 1 8, 1 9, 20. Since the shift registers are clocked by a video clock signal v, whose frequency is twice that of XMT the data actually shifted into them will consist of alternate logic 0's and memory data bits. That is to say, logic O's are inserted between all the serial memory bits.Therefore at any one time the shift registers will output either three adjacent memory bits at QAV QCT QE and logic 0's at 0, and 0D or two adjacent memory bits at QB and QD and logic 0's at QA QCT 0E The output voltages from the shift registers are combined together by two interpolation networks 22 and 23 as shown to provide the odd field video output on line 25 and the even field video output on line 26. Means must be provided to switch from one network to the other at the end of each TV field. This could be done, for example, by means of an electronic SPDT analogue switch connected to the two output nodes.Alternatively, the two output nodes could be joined together and digital devices be used to disable the inputs of the unused network. Such disabling could take the form of either open-circuiting the unused inputs (e.g. by the use of tristate devices) or forcing them all to the same logic level (e.g. by AND or OR gates, or by using separate shift registers for each network and disabling the unused shift registers in some way).

An important feature of this embodiment of the invention is the fact that an optimised set of values has been worked out for the relative conductances of the resistors as indicated in fig.

1. The use of this set of values results in perfect matching of vertical interpolation properties with horizontal interpolation properties.

In considering the interpolation properties assume that a logic 1 voltage has always the same value, regardless of where it is generated, and regardless of resistive loading. Assume simiiarly that a logic 0 voltage always has the same value. (Although not shown in the circuit, additional measures could easily be taken to adjust or clamp the logic voltages if necessary to validate this assumption).

Assume further that neither output node is significantly loaded (e.g. by a resistance to earth).

Then, when all the shift registers are full of logic O's, the voltage at both output nodes will be equal to the logic 0 voltage. Therefore let the logic 0 voltage be the reference voltage, and let the output voltage of each node always be expressed relative to this logic 0 reference.

It can be shown by simple application of the theory of nodal network analysis that when the shift registers are not all full of logic O's, the output voltage will rise toward the logic 1 voltage by an amount proportional to the sum of all the conductances now connected to a logic 1 voltage.

Expressed more succinctly, EG(1) VOVn G(x) where V0=the voltage at the output node, relative to the logic 0 voltage, V1=the logic 1 voltage, EG(1)=the sum of all the conductances connected between the output node and a logic 1 potential, EG(x)=the sum of all conductances connected between the output node and either a logic 0 or a logic 1 potential.

Examination of the circuit will show that the relative value of G(x) is always 32 G for either node. It is also not difficult to see that if a solid area of logic 1's in the memory is being scanned, so that all three shift registers are outputting as many logic 1 's as possible (i.e. from either QAT QCT and QE or from Q6 and QD)S then G(1)=16 G for either node. Thus the maximum value for V0 is given as: 16G VO=V, 32 G =iVt Fig. 2 shows the relative intensities of the picture cells resulting from various patterns of logic 1's stored in the memory.Note the equal horizontal and vertical interpolation effects by comparing the vertical line (a) with the horizontal line (b), or by comparing the sequences of numbers through the vertical and horizontal axes of the single point (c) or the 450 line (e).

A major advantage resulting from the resistive interpolation technique is the minimisation of picture-frequency flicker-i.e. flicker which appears at half the field frequency. The minimisation of this is achieved because in all circumstances the total light output is the same during both fields for all the patterns shown in Fig.

2. This may be checked for each pattern by adding together all the numbers along the even lines and then comparing the resuit with the sum of all the numbers along the odd lines. For example, in the case of the single point (c), the sums obtained for the five lines involved are, from top to bottom, 1+2+1 = 4 1+4+6+4+1 = 16 2+6+8+6+2 =24 1+4+6+4+1 = 16 1+2+1 = 4 Sum of odd lines =32 Sum of even lines = 32 In the above it is assumed of course that the total light output over a small number of cells is proportional to the integrated video signal voltage. It should always bea a simple matter to deliberately distort the video signal so as to make this assumption valid, should picture-frequency flicker be a major consideration.

Fig. 3 shows the video waveforms associated with various dot patterns in the memory. The waveforms illustrate that in most cases the use of the resistive interpolation network does not seriously degrade picture resolution, which is fundamentally determined by the size of the memory. The one exception is with the dot pattern shown at (e), which is smoothed out to a constant level on all lines. However, this is not serious and could in fact be advantageous should a pseudo-random erasure technique, as described in our copending patent application No.

34154/78 (Serial No.2,029,149), be employed.

While the embodiment has been described with reference to data provided from a store, it is of course generally applicable to data from any source at a suitable speed and may be used to reconstruct, for example, a TV picture from data transmitted via a transmission line. This allows a greatly reduced amount of data to be transmitted with consequent economies.

Claims (4)

Claims

1. A method of generating from input data, at a first frequency, output data at a second frequency, the method comprising supplying said data at the first frequency to at least two shift registers clocked at the second frequency and combining the signals at several outputs of the shift registers by means of a resistive network to form said output data.

2. A circuit for generating from input data, at a first frequency, output data at a second frequency, the circuit comprising means arranged in operation to supply said data at the first frequency to at least two shift registers having clock inputs, and an output line connected by means of a resistive network to at least several outputs of each shift register, whereby the data on said output line is at the second frequency determined by the shift register clock frequency.

3. A method of generating video signals for the cells of a picture matrix from data signals supplied from a smaller number of cells in a memory, the method comprising gating, at a first frequency, data from at least two outputs of a memory into at least two respective shift registers, clocking said shift registers at a second frequency, and combining, by means of a resistive network, the output signals at several outputs of at least two of said shift registers into said video signals.

4. A circuit for generating video signals for the cells of a picture matrix from data signals supplied from a smaller number of cells in a memory, the circuit comprising at least first and second gates each having a clock input and a data input connectible with said memory, a respective shift register for each said gate and having a data input connected to the output of its respective gate, several outputs and a video clock input, and a resistive network connecting the outputs of at least two of the shift registers to a common output, whereby the video signals appearing at the common output at the frequency of the video clock comprise at least first and second signal trains each at the frequency of the memory clock and each consisting of a different combination of the data signals supplied to at least the first and second gates.