CS210327B1 - Unit of the multipurpose bistable memory trigger circuits - Google Patents

Description

BACKGROUND OF THE INVENTION The present invention relates to a multipurpose bistable memory flip-flop unit, in particular for the assembly of logic systems, e.g.

Until now, memory circuits have been solved by assembling and interconnecting discrete components of logic elements or relays. E.g. connecting two logical sum or product members such that the output of one logical member is coupled to the input of the other logic member, whose output provides feedback to the input of the first logical member. Other inputs of the logic elements are then used to control the memories. In the case of a relay memory circuit, the relay coil is controlled by one make contact and a second break contact is connected in parallel to the relay coil, which has a relay coil make contact in series.

A disadvantage of the memory circuits used hitherto is that the memories are assembled by external interconnection of discrete components of logic elements or relays in a single purpose according to the desired use, so that the function of the connected circuit is constant. A further disadvantage is that a unit composed of discrete components connected as a single function memory occupies a considerable modular volume in a logic system of the same design. The designing of logic systems and their detailed redrawing using single-purpose hinged circuits is then time-consuming.

These disadvantages are overcome by the multipurpose bistable flip-flop circuit of the present invention, which consists of two input inverters, two product blocks, a product gate, two output inverters, four input and three output terminals according to the invention. the recording input of the first inverter whose output is connected in parallel to the recording input of the product gate and to the recording input of the first product block. The output of the first product block is connected to the first output memory terminal, to the feedback input of the second product block, and to the memory input of the product gate, the output of which is connected to the third output memory terminal via the first output inverter.

The input input terminal is then connected to the input input of the first product block whose feedback input is connected in parallel to the output of the second product block and to the memory input of the second output inverter whose output is connected to the second output memory terminal. The second input control terminal is connected to the lubrication input of the second input inverter whose output is connected to the lubrication input of the product gate and to the lubrication input of the second product block whose reset input is connected to the input reset terminal.

The multipurpose bistable memory flip-flop unit of the invention is illustrated schematically by way of example in a block diagram in the accompanying drawing.

As can be seen from the block diagram, the unit according to the invention consists of first and second input inverters 1, 2 and first and second output inverters J, 4 formed by NAND logic members of the first integrated circuit, first and second product block 2t. circuit and product gate 2 type NAND. Further, the unit consists of first and second input control terminals A, B, input adjusting terminal C, input reset terminal D, and first, second and third output memory terminals X, Y, Z, for connecting it to a logic automation system.

The unit according to the invention is then connected so that the first input terminal A is connected to the recording input and the first inverter 1, the output of which is connected in parallel to the recording input f of the gateway 1 and to the recording input e of the first product block 2. connected to the first output memory terminal X, to the feedback input h of the second product block 6, and to the memory input g of the product gate 2 · The output of the product gate 2 3 ^{e is} connected to the combination input m output memory terminal Z.

The input input terminal C is connected to the input input c of the first product block 2i whose feedback input k is connected in parallel to the output of the second product block 6 and to the memory input 1 of the second output inverter A whose output is connected to the second output memory terminal Y. the control terminal B is connected to the lubrication input b of the second input inverter 2, the output of which is connected both to the lubrication input i of the product gate 2 and to the lubrication input j of the second product block o.

To explain the function and use of the unit of the invention in a logic automation system, it is useful to use Boolean algebra logic relations and state tables. Input variables A, B, C, D are applied to the first and second input control terminals A, B, input adjusting terminal C, and input reset terminal D of the unit, output X and internal variable X are output to the first output memory terminal X and third output, memory terminal X,

The output variables Y, Z are output.

The following are the dependencies between the input variables A, B, C, D, the internal variable X and the output variables X, Y, Z in Boolean algebra, where in accordance with technical practice the character v expresses a logical sum, - expresses the negation of the variable. All of the following formulas are expressed in a minimized form so that they can be stated

X = A viv BÍDÍX X = BIB ^a (AvČvY) Z = A <B ⁴ X (1) (2) (3

The status table is then as follows:

AND (B) C D X Y OF L L L L H L H L L L H H H H L L H L L L L L L H H M M X L H L L H L L L H L H H L L L H H L L L L L H H H L L L H L L L H L L H L L H H H L H L H L H L L H L H H H H L ti ii L L H L L H H L H H L L H H H L H L Ij H H II H H L L

The headers of Table (I) list the input variables A, B, C, D, the internal variable X and the output variables X, Y, Z. All combinations of the input variables A, B, C, D correspond to the states of the output variables X, Y , Z, event .. internal variables X. The designation L then corresponds to the logical level O, the designation H corresponds to the logical level “1”. The designation M denotes the original state, which depends on the previous information, ie the memory state. From this, it can be seen which memory functions can generally be realized by the unit according to the invention. As an example of practical use of the unit according to the invention, four typical variants are given below, which can be expanded further.

The first application of the unit according to the invention is the KS-type steam with a predominant record over lubrication, controlled by signals in positive logic, eg electronic equivalent of the self-holding relay circuit, etc. For this variant it is necessary to connect the unused input setting terminal C and level C = H, D = H, which corresponds to the expression in Boolean algebra.

X = A in B & X

The status table of this memory function is then as follows:

A B X L L M L H L H L H H H H

To reset the memory, the individual inputs are connected as follows:

the first input control terminal A = L, the second input control terminal B - L, the input adjustment terminal C = II, the output reset terminal D = L, then the first output memory terminal X is L, ie resetting is performed by applying an L signal on input reset. To adjust the memory, connect each input as follows: first input control terminal A = L, second input control terminal B = L, input adjustment terminal C = L, input reset terminal D = H, then at the first output memory terminal X is H, ie the setting is done by applying an L signal to the input setting terminal C.

The second variant of the use of the unit according to the invention is the RS type memory with predominant erasing over the record, controlled by signals in positive logic, eg the equivalent of the memory circuit with Sieny NOR, etc. For this variant it is necessary to connect the unused input level C = D, D = H, which corresponds to the expression in Boolean algebra.

X - B & (A in Y)

The status table of this memory function is then as follows:

AND B ' Y L L M L H L H L H H H L

To reset and adjust said memory, the first input control terminal A, the second input control terminal B, the input adjustment terminal C, the input reset terminal D are connected in the same manner as in the first variant of use of the unit according to the invention.

The third variant of the unit according to the invention is a combination sequential circuit which reacts to the disappearance of the recording signal, controlled by signals in positive logic, eg a circuit which responds to the displacement of the position sensor by the conveyed material, etc. For this variant it is necessary to connect an unused input C terminal and the input zero terminal D to C = H, D = H, which corresponds to the expression in Boolean algebra.

Z = A <£ Β & X (7)

X = Á in B 4 x (7) where X is an internal variable and Z is an output variable.

The status table of this memory function is then as follows:

AND (B) OF X L L X M L H L L H L L H H H L H

To reset and adjust said memory, the first input control terminal A, the second control terminal B, the input adjustment terminal C, and the output reset terminal D are connected in the same manner as in the first variant of use of the unit according to the invention.

2,0327

A fourth variant of the use according to the invention is the RS-type memory with the predominant loss of record over lubrication, controlled by signals in negative logic, eg control circuit, integrated circuits by mechanical switch, etc. For this variant it is necessary to connect unused first input control terminal A and second input control terminal B to level A = B,

B = L, which corresponds to the expression in Boolean algebra

X = Č in D <8 X (8)

The status table of this memory function is then as follows:

C D X L L H L H H H L L H H M

To reset the memory, connect each input as follows: first input control terminal A = L, second input control terminal B = H, input adjustment terminal C = H and input reset terminal D = H, then on the first output memory terminal X is L, that is, resetting is carried out by applying a signal H to the second input control terminal B. To set the memory, the individual inputs are connected as follows: first input control terminal A = H, second input control terminal B = L, input adjustment terminal C = M and input reset terminal D = H, then at the first output memory terminal X is H, ie the setting is made by applying the signal H to the first input control terminal A.

Another possibility of using the unit according to the invention is in the case of inverted input signals, for example in the second variant the inverted input signals can be applied to input adjusting terminal C and input reset terminal D instead of the first input control terminal A and the second control terminal B. it is also possible to use input signals where one is in positive logic and the other in negative and vice versa, etc. The unit according to the invention can advantageously be used as a shaping flip-flop by external connection of the first input control terminal A to the input reset terminal D, on the first output memory terminal X and the unused first input control terminal B and input adjusting terminal C are connected at B = L, C = H.

The unit according to the invention can then advantageously be used for the realization of logical automation systems, for example in various types of rolling mill, such as billet, return, belt and lines for heat and other technological processing of rolled material and the like, without changing the essence of the invention.

Claims (1)

SUBJECT OF THE INVENTION Multipurpose bistable memory flip-flop unit consisting of two input inverters, two product blocks, a product gate, two output inverters, four input and three output terminals, characterized in that the first input control terminal (A) is connected to the recording input (a ) of a first input inverter (1), the output of which is connected in parallel to the recording input (f) of the product gate (7) and to the recording input (e) of the first product block (5) whose output is connected to the first output memory terminal (X) to the feedback input (h) of the second product block (6) and to the memory input (g) of the product gate (7), the output of which is connected to the third output memory terminal (Z) via the first output inverter (3); The input (c) of the first product block (5), whose feedback input (k) is parallel to the connected to the output of the second product block (6) and to the feedback input (1) of the second output inverter (4), the output of which is connected to the second output memory terminal (Y), the second input control terminal (B) being connected to the lubrication input b) a second input inverter (2) whose output is connected to the lubrication input (i) of the product gate (7) and to the lubrication input (j) of the second product block (6), whose reset input (d) is connected to the input iwlow terminal (>)).