CN88206283U

CN88206283U - Multi-function data collecting converter

Info

Publication number: CN88206283U
Application number: CN 88206283
Authority: CN
Inventors: 冯龙龄
Original assignee: Beijing Institute of Technology BIT
Current assignee: Beijing Institute of Technology BIT
Priority date: 1988-06-01
Filing date: 1988-06-01
Publication date: 1988-12-21

Abstract

The utility model discloses a multi-function data collecting converter belonging to the data acquisition technology. The multi-function data collecting converter is provided with a multifunctional data acquisition and conversion board, and the multi-function data collecting converter uses a high-speed A/D converter composed of a successive comparison shift register, a comparator and other elements to replace a special high-speed A/D converter of majority of the existing data acquisition boards. The multi-function data collecting converter has the advantages of low cost, compact structure, small size and multi functions, integrates a high-speed S/H circuit, a high-speed D/An and sequence control assisting circuit on the multifunctional data acquisition and conversion board, and independently completes the sample holding of a signal, extracting time associated information, self-testing and other tasks in multi-mode. The multi-function data collecting converter is provided with a conventional data input port, a conventional data output port and various microcomputer interfaces, and the conventional data input port and the conventional data output port are provided with a locking wire, a buffering wire and a connecting wire.

Description

Multi-function data collecting converter

The utility model belongs to data acquisition technology.

There are some undesirable part mostly more or less in domestic existing A/D, D/A converter at present.Distinct issues have: circuit is imperfect, and the A/D that the user has bought, D/A device or circuit often can not directly use, and also need design correspondent control circuits or special purpose interface and could work, and this will increase added burden to the user; Function and working method are single, and a certain circuit is only limited to certain specific model and purposes, or have only single working method, are not easy to change do its and use; Price comparison height, especially high speed device, the A/D chip of the slewing rate ten microsecond orders of magnitude, every just needs hundreds of and even thousands of units.

The purpose of this utility model is to provide a kind of multi-functional data acquisition, change-over panel, takes into account above-mentioned various aspects better.This circuit sampling speed height, about 100ns of sampling time and pulsewidth are adjustable.Be respectively 1 μ s and 0.5 μ s the switching time of A/D, the fast 8bitA/D of D/A slewing rate and D/A.Sequential control circuit is complete.Except that power supply, do not need other adjunct circuits to get final product operate as normal, with analog quantity input, the running of the analog quantity way of output of band time correlation sampling or carry out self check.Bus buffer parallel data grabbing card and data reading and writing interconnection independently with band data interlock carry out the data transmission by 16 line plug receptacles and outside, are convenient to and various microcomputer interfaces.Can be by the collection of external synchronization signal control data, A/D conversion.The time delay that lags behind is adjustable.The signal that this function can be used for temporal correlation is had relatively high expectations carries out data acquisition process.As extract amplitude envelope line of pulse train etc.The line construction compactness, size is little.The entire circuit package size is not more than 200 * 54mm ²Has higher performance.Entire circuit system is low by general-purpose device assembling price, cost even be lower than the A/D chip of equal performance.

Principle of compositionality of the present utility model can be as follows by description of drawings:

Accompanying drawing 1 is the functional-block diagram of the technical program.Among the figure, by plug receptacle J ₁The simulating signal of input arrives by comparing the high-speed a/d converter that shift register (4), D/A converter (5), high-speed comparator (6) and reference power source (7) and clock generator (8) are formed one by one through buffer amplifier (1), sampling/maintenance (hereinafter to be referred as S/H) switch (2), buffer amplifier (3).Here analog signal conversion becomes corresponding digital signal, through data interlock impact damper (9), by plug receptacle J ₃And line output.The circuit that in A/D converter available data is provided improves, change direct die analog signal time output radix-minus-one complement data under the former design into positive code data, because the size of the data value of radix-minus-one complement output is big or small opposite with the amplitude of analog input fully, can look into and the post-processed of data is brought great inconvenience to the sight of A/D transformation result.Therefore, the circuit that prior art is provided improves, and changes radix-minus-one complement output into positive sign indicating number output.

The data acquisition external synchronization signal is by plug receptacle J ₃Input is earlier through the door (10) of prescribing a time limit.In the phase in limited time of the door (10) that begins after a synchronizing signal is by door (10), other pulse inputs that occur again can not be by door (10).Therefore the impulse disturbances in eliminating during this period of time effectively.Time-delay door (11) can be regulated the retardation time of data acquisition to synchronizing pulse by multiturn potentiometer.It and sampling pulse take place and impact damper (12) fit adjustment, to obtain best sample effect.The width of the sampling switch driving pulse that sampling pulse generator (12) produces is regulated by another multiturn potentiometer.After sampling process was finished, fixed A/D starting impulse generator with lock sent the enabling signal that pulsewidth is indefinite to A/D converter.The startup pulsewidth of random variation can guarantee to include in the starting period A/D rising edge clock, is unlikely to prolong the starting period of A/D again, to guarantee the finishing A/D conversion in the 1 μ s.Narration about lock door sees the feature description part for details.The main body of door and pulse producer (10), (11), (12), (13) constitutes with the monostable integrated circuit of two different models respectively.

" A/D finishes " signal that shift register (4) produces sends data interlock signal and time-limited locking signal to data interlock impact damper (9) and A/D starting impulse generator (13) respectively after suitable inverting buffer, then through J ₃To outside output " A/D finishes " cue.

The data of data interlock impact damper (9) and (14) read control and the data write control signal also respectively from plug receptacle J ₃Different port input.

Each interconnection and control line are all linked and are patched a J in the plate ₅The place is to obtain different data acquisition modes by suitable connection.

Via plug receptacle J ₃Input or convert corresponding simulating signal through data interlock impact damper (14) locking, buffering back by D/A converter (15) by impact damper (9) output data, cushion after by plug receptacle J through buffer amplifier (16) ₂Outside plate, export.This circuit has used the D/A converter spare of slewing rate as 150ns.Therefore the rate of change of the D/A of this circuit simulation output is limited by the writing speed of microcomputer only.

The power supply of circuit is by plug receptacle J ₄Input.

Of the present utility model being characterised in that improved A/D change-over circuit of the prior art (LINEAR DATABOOK 84, P8-125, NATIONAL SEMICON-DUCTOR CORPORATION).Change intrinsic radix-minus-one complement data output into positive sign indicating number.Relative section circuit after the improvement as shown in Figure 2.Improvement is as follows:

The Iout＜PIN4〉that the IN2＜PIN4〉that the Iout＜PIN2〉of former D/A converter (5) is connect comparer (6) changes (5) into connects the IN2＜PIN4〉of (6), Iout ground wire.

The D＜PIN 7〉that the output 1＜PIN 11〉of former (6) is connect one by one output 2＜PIN 9〉that the D＜PIN7〉of shift register (4) relatively changes (6) into and (4) joins.Keep the backfeed loop of the output 1＜PIN 11〉of former (6) to IN1＜PIN 3 〉.

After improving like this, when the binary data of D/A converter (5) was input as " 11111111 ", it was the analog output voltage maximum of D/A that Iout goes up the pressure drop that produces at resistance (17).The output voltage of the simulation output of this D/A and amplifier (3) is located summation at point (18).If output signal (3) is greater than the output of (5), comparative result is for just.The output2 of comparer (6) is to the D end output high level that compares shift register (4) one by one, otherwise output low level.Level on the D has determined still to be " 0 " at that bit of comparer " 1 " just.(4) begin by turn to (5) output data to be compared from most significant digit.Simulating signal with (3) output after (5) conversion compares, and all decides until 8 bits, and the A/D conversion promptly comes to an end.When the analog output signal in (3) was full scale value, the result of A/D conversion was a decimal number 255.When (3) were output as zero, A/D result was " 0 ", had promptly realized positive sign indicating number output.

Another characteristics of the present utility model are to utilize a monostable circuit to design fixed A/D starting impulse generator (13) with lock.Relevant physical circuit is seen accompanying drawing 3.Owing to used the Compulsory Removal input end CLR of (13), just the length that the temporarily steady time (pulsewidth of corresponding A/D enabling signal) of (13) can be provided with is a bit can comprise the just edge of an A/D clock in guaranteeing during this period of time in circuit.In case started A/D, CLR is a step-down, and temporarily steady state is finished in advance.The startup of A/D just can not be long like this.Effect in the R.C integrating network of just inserting along trigger end B place of (13) is: when the Q of sampling pulse generator (12) end is input as high level (corresponding sampling period), Q charges to C through R.Before sampling pulse finishes, C is charged to the TTL high level.Trigger the temporarily steady process of (13) at the negative edge of Q.Other various situations do not satisfy the trigger condition of monostable circuit.So guaranteed correct pulse sequence.

Advantage of the present utility model and effect are:

With common D/A converter, compare shift register one by one, the high-speed a/d converter that devices such as comparer are formed has substituted the specialized high-speed A/D device in present most data acquisition board, has reduced cost; Collection high speed S/H circuit, high-speed a/d, auxiliary circuits such as high-speed d/a and sequential control be in a plate, compact conformation, volume is little, telotism can work alone in many ways, finishes tasks such as the extraction of sampling maintenance such as simulating signal, time related information and self check; It is with lock fixed to have, and the conventional data of buffering and interconnection is exported, input port is convenient to and various types of microcomputer interfaces.

Accompanying drawing 4 is embodiment of the present utility model, its main component parameter in the figure notes:

Claims

1, a kind of multifunctional data acquiring converter, form by buffer amplifier (1), (3), sampling/maintained switch (2), high-speed a/d converter (4,5,6,7,8), data interlock impact damper (9), (14), sequential control door (10,11,12,13), D/A converter (15), amplification impact damper (16) etc., it is characterized in that:

(1) high-speed a/d converter is by relatively shift register (4), D/A converter (5), high-speed comparator (6) and reference power source (7), clock generator (8) are formed one by one.

(2) utilize a monostable circuit to design fixed A/D starting impulse generator (13) with lock; R, the C integrating network just inserted in (13) along trigger end B place, when the Q of sampling pulse generator (12) end was output as high level, Q charged to C through R, before sampling pulse finishes C is charged to the TTL high level, negative edge at Q triggers (13), to guarantee correct pulse sequence.

2, by the described multifunctional data acquiring converter of claim 1, it is characterized in that: the Iout termination ground wire of the D/A converter in the said high-speed a/d converter (5), the IN of Iout termination (6) ₂End, thus radix-minus-one complement output of the prior art is changed into positive sign indicating number output.

3, by the described multifunctional data acquiring converter of claim 1, it is characterized in that: the output2 end of high-speed comparator (6) joins with the D end that compares shift register (4) one by one, and the Output1 that keeps (6) holds IN ₁The backfeed loop of end.