CN2227357Y

CN2227357Y - Intelligent memory oscillograph and logic analysis card

Info

Publication number: CN2227357Y
Application number: CN93220042U
Authority: CN
Inventors: 王�忠; 骆宜光
Original assignee: Individual
Current assignee: Individual
Priority date: 1993-07-24
Filing date: 1993-07-24
Publication date: 1996-05-15
Anticipated expiration: 2003-07-24

Abstract

The utility model relates to an intelligent memory oscillograph and logic analysis card, comprising an analog circuit, a digital circuit, and an interface circuit. In the analog circuit, the tested analog signal is amplified and translated; the tested analog signal and the basic voltage signal are sent to a triggering comparator; then, a triggering signal is produced and is sent to the inner part of the digital circuit; in the digital circuit, after the translated analog signal is converted by an A/D converter, the translated analog signal and the address signal together are sent to the stochastic memory; at last the analog signal is processed by the software. The utility model can realize the digital memory oscillography for the analog signal and the logic analysis for the digital signal on the common computer. The utility model can also realize the post-processing for the signal.

Description

Intelligence storage oscillography and Logic Analysis Card

The utility model belongs to electronic measurement technique, and particularly appliance computer is realized various electric signal are carried out accurate qualitative and quantitative analysis.

For a long time, analog oscilloscope is the main tool of electric signal measurement always, it can be presented at abstract various electric signal and non-electric charge quantity signalling on the screen of oscillatron intuitively, so that electric signal is carried out accurate qualitative and quantitative analysis, but there is following problem: under the slow scanning situation, scintillation is arranged, particularly for the inswept too quickly screen of single signal apace, be difficult to measured signal is analyzed, promptly it is only applicable to observe periodic signal, can't carry out record to waveform.Development along with digital circuit, large scale integrated circuit and microprocessing, digital-storage oscillograph has appearred, it has overcome the problem that analog oscilloscope exists basically, still exist cost an arm and a leg, operate loaded down with trivial details, be difficult to problem such as grasp, can not be generalizable, particularly its post-processing function to signal is not strong, also dumb, and do not possess functions such as logic analysis, therefore can not accomplish a tractor serves several purposes (referring to " modern digital storage oscilloscope principle and application " Electronic Industry Press in May, 1989 version)

The purpose of this utility model, be to utilize the active computer resource, provide a kind of function many, cheap, intelligence storage oscillography and Logic Analysis Card easy and simple to handle, so that on common computing machine, realize the function of numeral storage number ripple device and logic analyser, and can carry out the aftertreatment of various ways, particularly spectrum analysis and mains by harmonics monitoring to institute's image data.

The purpose of this utility model is achieved in that the store function that utilizes computing machine itself and the I/O mouth of expansion, the utility model adopts advanced program control technology and high speed analog-to-digital conversion technology, design a kind of circuit card, can directly link to each other, and be equipped with support software and realize measurement and analysis electric signal with the expansion I/O mouth of computing machine.For numeral storage oscillography part, the utility model is by amplification or the decay of mimic channel realization to the voltage amplitude height of tested electric signals, and the isolation of extraneous input signal and subsequent conditioning circuit; Simultaneously, produce a trigger pip by mimic channel and be sent to digital circuit.Digital circuit is mainly finished the analog to digital conversion of tested electric signals and high speed static random storage buffer memory, and relevant collection to signal, process control, analysis, demonstration, storage or the like are mainly finished by support software.When carrying out logic analysis, mainly utilize digital circuit that the data of measured number signal are directly sent into the high speed static random memory, produce when trigger pip is equated with the signal that presets by measured number simultaneously, realize triggering, signal is carried out the process of logic analysis and finish by support software.In the process of electric signal being carried out numeral storage oscillography and logic analysis, the duty of each chip and initialize data in digital circuit and the mimic channel utilize software to finish the input and output of data by interface circuit.Can realize spectrum analysis and mains by harmonics monitoring by Control Software to electric signal.

Because the utility model has adopted advanced program control technology and high speed analog-to-digital conversion technology, has realized demonstration, storage, analysis to tested electric signals, and following beneficial effect is arranged.

1. use efficient, simple and direct flexibly, as long as the circuit card that the utility model is provided is directly inserted in the expansion slot of microcomputer, remaining test process can be finished by keyboard; 2. the waveform that measures can forever be preserved by computing machine, and the waveform of measuring-signal and the waveform of storage can be analyzed comparison; 3. the signal post-processing increased functionality can be carried out spectrum analysis, mains by harmonics monitoring to signal; 4. has logic analysis function to signal; 5. the utility model is cheap, more than buying a digital-storage oscillograph considerably cheaper.

The utility model will be further described below in conjunction with drawings and Examples.

Fig. 1 is the schematic diagram of the utility model artificial circuit part.

Fig. 2 is the circuit theory diagrams of program control DC level generator A3 in this practical artificial circuit part

Fig. 3 is the schematic diagram of the utility model digital circuit and logic analysis part.

Fig. 4 is the utility model numeral oscillography course of work flow chart

Fig. 5 is the utility model logic analysis course of work flow chart

Fig. 6 is the circuit theory diagrams of the data switch DK1 in the utility model digital circuit and the logic analysis part

Fig. 7 is the circuit theory diagrams of the data switch DK2 in the utility model digital circuit and the logic analysis part

Fig. 8 is the circuit theory diagrams of programmable frequency divider D4 in the utility model mimic channel

Fig. 9 is the interface circuit schematic diagram that the utility model is connected with the computing machine expansion I/O

The course of work of numeral storage oscillography is at first described.Among Fig. 1, the simulating signal of input is a circuit-under-test number, when tested electric signals during by voltage follower A1, because voltage follower has the character that high input impedance and electric current are put, has just realized the isolation of extraneous input signal and subsequent conditioning circuit; Then, signal is through gain-programmed amplifier A2, as required signal amplified or decays; Because among Fig. 3, digital-to-analog converter D1 only accepts the signal of level at 0～5V, and A2 through the signal level of gain-programmed amplifier A2 output-12V～+ 12V between, so will carry out the current potential translation to signal.The utility model adopts the program control DC level generator of being made up of digital-to-analog converter and voltage amplifier, the signal that produces direct current voltage and gain-programmed amplifier A2 output is together sent into current potential translation totalizer A4, makes the measured signal of output one level between 0～5V after the two voltage additions; Produce reference voltage by program control triggering reference level generator A5 simultaneously, send into trigger comparator A6 together, produce trigger pip with gain-programmed amplifier A2 output signal.

Among Fig. 3, analog/digital converter is realized the analog to digital conversion to the simulating signal of exporting among Fig. 1, and its data temporarily are deposited with among the high speed static random memory D2, finish sampling to measured signal among Fig. 1, the principle of its sampling process is as follows: the signal of clock generator D5 closes DK2 to programmable frequency divider D4 through normally closed data switch, square wave by programmed control programmable frequency divider D4 output appropriate frequency, be sent to address generator D3 and analog/digital converter D1, export a secondary data and store in D2 weekly by the phase under D4 output signal control for analog/digital converter D1, D3 is a cycle counter, before DK2 disconnects, D1 constantly send data to go into D2, D2 is recycled and refreshes, when the trigger pip of being come by Fig. 1 arrives, DK1 connects D6 and begins counting, after the full designated length of meter, D6 sends a positive pulse and gives DK2, DK2 is turn-offed, at this moment, D1, D3, D6 all quits work, sampling process is finished, wherein, the position of signal data in D2 at place, trigger point is relevant with D6, for example, if the counting step that D2 sets is 512 bytes, and the max cap. among the D2 is 2KB, then current among the D2 be address (being the address of DK2 when disconnecting) backward the data of 1.5kB be the data before trigger pip arrives, the data of 512 bytes are data after trigger pip arrives backward again.In this way, both obtained the later data in trigger point, the data before the trigger point of having got back have so just realized " the trigger the back " function in the storage oscilloscope.

The process of logic analysis as shown in Figure 3, measured signal is passed through latch D9 under the clock signal control of programmable frequency divider D4 output, simultaneously signal is sent into high speed static random memory D2 and digital comparator D7, in addition, preset the signal that word register D8 presets and also send into digital comparator D7, when the signal that presets as measured data signal and D8 equates, produce trigger pip, realize triggering.The later course of work is basic identical with the aforementioned numeral storage oscillography course of work substantially.

Program circuit by programmed control numeral storage oscillography at first is provided with initial state as shown in Figure 4, starts computer operation, then, the enlargement ratio and the translation current potential of analog channel are set, secondly, set gradually triggering level, triggering mode and buffering section length, open DK2, judge whether DK2 turn-offs, as turn-offing, then sampling finishes, and data are read in calculator memory and show numeral storage oscillography end-of-job.

The program circuit of analyzing by programmed logic as shown in Figure 5, initial state at first is set, start computer operation, set gradually to trigger and preset word, triggering mode, buffer length, then, open DK2, judge whether DK2 turn-offs, as turn-offing, sampling finishes, and data are read in calculator memory show the logic analysis end-of-job.

Among Fig. 2, the production process of DC level is as follows: obtain computer interface circuit D under the programmed control by A-D converter ₀～D ₇Data, output aanalogvoltage after conversion obtains program control DC voltage after voltage amplifier amplifies.

Among Fig. 6, data switch DK1 is made up of d type flip flop, by interface circuit output trigger reset signal 30CH with put that 1 signal 308H is sent to its reset terminal respectively and when putting 1 end, LR be low level, buffer capacity counter D6 quits work; When trigger pip LAT arrives, LR become high level, D6 starts working, and realizes the effect of data switch.

Among Fig. 7, data switch DK2 is made up of data selector and d type flip flop.Count signal 256B, 512B, 1KB, 2KB by buffer capacity counter D6 generation, send into the data input pin of data selector, the buffer capacity that interface circuit produces selects signal N4, N5 control data selector switch to select count signal, when count signal one of them when selected, export a positive pulse by data selector and trigger d type flip flop and export a high level CLKE, programmable frequency divider D4 is quit work.Wherein import d type flip flop reset signal 314H, put 1 signal 310H and export by interface circuit.So just realized the effect of DK2 data switch.

For the ease of understanding, below sketch the course of work of programmable frequency divider D4.Shown in Figure 8, programmable frequency divider D4 is made up of crystal oscillator, 74CS161 frequency divider, CD4536 programmable frequency divider and data selector, import the 74LS161 frequency divider by the oscillator signal that crystal oscillator produces, the 74LS161 frequency divider produces two divided-frequency, four frequency divisions, eight fractional frequency signal input digit selector switchs, 16 fractional frequency signals and interface circuit output K ₄～K ₇Import program control frequency device CD4536 simultaneously, produce 2 ^16+xFractional frequency signal is input data selector also, and X is K ₄～K ₇Value, produce K by interface circuit in addition ₀～k ₃Select fractional frequency signal input data switch; When DK2 data switch input CLKE signal was low level, output effectively; Export the CLK clock signal this moment; When DK2 data switch input CLKE signal was high level, it was invalid to export, not clocking.

About with the interface circuit of computer interface as shown in Figure 9, by being connected, can produce above-mentioned digital circuit or the required data of mimic channel on request by the concrete design of program with the expansion mouth of PC.This interface circuit has mainly comprised 8255 chips, buffering driver, 12 address decoders and utmost point gating base address controller.A among Fig. 9 ₀～A ₉Be address wire, the address date that produces is sent to 8255 chips, port address code translator, plate gating base address controller, D respectively ₀～D ₇Be data, data-signal sent into 8255 chips, by the N of 8255 chips generation by data line ₀～N ₇Be sent to data switch DK2 etc. respectively, K ₀～K ₇Be input in the programmable frequency divider, the signal that the port address code translator produces is sent to 8255 chips respectively, and DK1, data switch DK2 etc. by above connection, have finished the data input and output between computing machine and the utility model.

Claims

1. an intelligence is stored oscillography and Logic Analysis Card, comprises by circuit board, and mimic channel, digital circuit and interface circuit that discrete electronic component and integrated circuit (IC) chip are formed is characterized in that:

(a) in the mimic channel, input gain-programmed amplifier A2 behind the tested analog passband signal superpotential follower A1, signal through gain-programmed amplifier amplification or decay is always gone into current potential translation totalizer A4 simultaneously with the DC voltage that program control DC level generator A3 produces, the simulating signal between 0～5V of current potential translation totalizer output; Simultaneously, reference voltage signal that program control triggering reference level generator A5 produces and journey are visited the signal of gain amplifier A2 output and are sent into trigger comparator A6, and trigger comparator A6 exports trigger pip 1;

(b) in the digital circuit, the simulating signal of current potential translation totalizer output is sent into the data-signal input high speed static RAM D2 that analog/digital converter D1 produces in the above-mentioned mimic channel, trigger pip 1 input data switch DK1, the count signal input DK2 that the level signal input buffering capacity counter D6 of data switch DK1 output produces, the clock signal that the level signal of DK2 output and clock generator produce is sent simultaneously in programmable frequency divider D4, the clock signal that programmable frequency divider D4 produces is input to buffer capacity counter D6 respectively, address generator D3, analog to digital converter D1, the address signal input high speed static RAM that address generator D3 produces; When tested electric signal is digital signal, direct input latch D9, the data-signal that latch D9 produces is sent into high speed static RAM D2 and digital comparator D7 respectively, the signal that while pre-register Dp presets is also sent into digital comparator D7, produce trigger pip 2 input data switch DK1, the clock signal input latch D9 that programmable frequency divider D4 produces by digital comparator D7.

2. numeral storage oscillography according to claim 1 and Logic Analysis Card is characterized in that program control DC level generator A3 is made up of D/A converter and voltage amplifier, the data-signal D that interface circuit produces ₀～D ₇The input D/A converter, the analog input signal voltage amplifier through D/A converter produces after voltage amplifier amplifies, produces programmable current voltage.

3. numeral storage oscillography according to claim 1 and Logic Analysis Card, it is characterized in that described data switch DK1, constitute by d type flip flop, by the reset signal of interface circuit output with put 1 signal and import its reset terminal respectively and put 1 end, trigger pip LAT imports its CLK end, by Q end output high level and low level signal.

4. numeral storage oscillography according to claim 1 and Logic Analysis Card, it is characterized in that described data switch DK2 is made up of data selector and d type flip flop, the selection signal that count signal that the buffer capacity counter produces and interface circuit produce is input data selector simultaneously, the CLK end of the pulse signal input d type flip flop of data selector Z end output, the reset signal of interface circuit output and reset terminal and the zero setting end of putting 1 signal input d type flip flop are by the level signal control programmable frequency divider work of Q end output.