CN88103487A - Frame and phase place be synchronous device fast - Google Patents
Frame and phase place be synchronous device fast Download PDFInfo
- Publication number
- CN88103487A CN88103487A CN88103487.8A CN88103487A CN88103487A CN 88103487 A CN88103487 A CN 88103487A CN 88103487 A CN88103487 A CN 88103487A CN 88103487 A CN88103487 A CN 88103487A
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- CN
- China
- Prior art keywords
- unique word
- character
- frame
- value
- phase place
- Prior art date
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0058—Detection of the synchronisation error by features other than the received signal transition detection of error based on equalizer tap values
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
- H04J3/0608—Detectors therefor, e.g. correlators, state machines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
- Radar Systems Or Details Thereof (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Communication Control (AREA)
Abstract
The unique word RK that receives had both contained frame clock RT, contained character clock ZT again.Unique word is subjected to the distortion of particular form in transmission channel, if the unique word of this distortion is taken a sample by the sampling clock that contains phase error, then phase error can be determined from sample value.Yet, in when, in transmission channel distortion taking place, vibration and back vibration before the character before and after the unique word can produce, their superpositions make the value of unique word complicated on unique word.According to basic idea of the present invention, the value of vibration before the moment of taking a sample and back vibration is calculated, and from the sample value that records, deducted it, thereby only stay the distortion effects of unique word as corrected value.
Description
The present invention relates to the receiving terminal frame and phase place realizes synchronous a kind of device.One of this class device has given open in DE-OS32 27 151.
In this class device of prior art, the character stream that receives is with the sampling clock sample at rates, and sample value is carried out digitlization by an A/D converter, thereby the original distortion of numerical character stream will be included in the digitized sample value.Produce cross-correlation function from the digital samples sequence with being stored in the known unique word of receiving terminal as frame alignment word by a digital correlator.When unique word occurring in the character stream that receives, cross-correlation function has maximum.According to these maximums, can derive the frame clock.Adopt this time discrete (sampling clock) though handle each single sample value that can only obtain cross-correlation function, yet, according to the sample value of two cross-correlation functions before and after the maximum sample value, can determine whether these two sample values are symmetrical with respect to maximum sample value in time.Thus, can derive and adjust the control information that the sampling clock phase place is used, and adjust the sampling clock phase place by this control information.
In such prior art device, the phase place of sampling clock can only be adjusted at leisure.Because the distortion of character stream still is retained in the sample value, so, the back oscillationg component that preceding oscillationg component that the character after the unique word comes and the character before the unique word come included in order to the sample value that derives control information.In this prior art device, this constituents is to come filtering by the equalization in several frame periods.
The adjustment that the objective of the invention is to make the sampling clock phase place more fast.
Basic idea of the present invention is as follows:
The unique word that receives promptly contains the frame clock, also contains character clock.On transmission channel, unique word is subjected to the distortion of particular form.If this have the special solely word of distortion to be taken a sample by the sampling clock that contains phase error, then phase error can be determined from sample value.Yet when in transmission channel distortion taking place, preceding vibration that the character before and after the unique word causes and back vibration on unique word, make the valuation of unique word complicated superposition.In prior art, smoothly fall this preceding vibration and back vibration by the equalization in several frames.According to basic idea of the present invention, calculate the value that vibration and back are vibrated before sampling moment, from the sample value that records, deduct it as corrected value, and only stay the distortion effects of unique word.So, from first detected unique word, just can derive to, in readjusting the control information that the sampling clock phase place is suitable for.Yet its advantage is: the corrected value that draws is not to be used for proofreading and correct sample value self, but is used for proofreading and correct the value of being derived by sample value.
Derive the character that the value of preceding vibration and back vibration can bear from the transmission coefficient of transmission channel again.Transmission coefficient or predefined, or from the equalizing coefficient of adaptive equalizer, draw.
Now, consult the following drawings embodiments of the invention be described:
Fig. 1 is the rough block diagram of device of the present invention;
Fig. 2 and Fig. 3 are the more detailed block diagrams of device shown in Figure 1;
Fig. 4 is the block diagram of the adaptive equalizer of prior art.
Consult Fig. 1, device of the present invention can be divided into three squares.First square 10 changes the character stream e that receives into binary data series Di by means of character sampling clock ZT.In addition, from first square 10, derive frame clock RT and error signal △ K '.Error signal △ K ' has determined the instantaneous phase deviation of character sampling clock ZT and actual characters clock.By means of frame clock RT, second square 20 can be from this error signal △ K ' the control information △ P of derivation adjustment usefulness.Second square is realized controlled function, and design example is as preventing phase jitter or vibration.Third party's piece 30 produces character sampling clock ZT, and the phase place of ZT is proofreaied and correct with control information △ P by adjusting.
In the present embodiment, signal processing is digital.The character stream e that receives is that the digitlization 8 bit sample value sequences of character sampling clock ZT are formed by repetition rate.Control information △ K ' also is made up of 8 bit words, but every frame evaluation once, and promptly its repetition rate is frame clock RT.Adjust with control information △ P and form by 4 bit words.
Fig. 2 shows first square 10 of Fig. 1 in more detail.From the character stream e that receives, draw binary data Di by adaptive equalizer E.
The configuration example of adaptive equalizer E is shown in Fig. 4.This structure is that in the art professional is familiar with, and repeats no more here.Each character in the character stream that is transmitted is distorted in transmission channel, and its form is for producing a large amount of preceding vibrations and back vibration.The interval of preceding vibration and back vibration equals character length, so the preceding vibration of kinds of characters will mutually direct superposition with the back vibration.In equalizer E, the preceding vibration M of each character and back vibration N are that the weighted volumes of C-1～C-M and C1～CN is come evaluation by coefficient respectively.The subscript of each coefficient is understood by the distance between the preceding vibration of this coefficient weighting or back vibration and the relevant character.Character itself comes evaluation by coefficient CO, and will adjudicate valve and be arranged on the CO/2.Secondly, importantly need consider a plurality of before vibration and back vibration, whether only need to consider the back vibration have that equalizing coefficient CK presets or adaptive.
According to those required equalizing coefficients of character stream e that equilibrium fully receives well, therefrom can draw each transmission coefficient of transmission channel.Represented good approaching because can suppose the equalizing coefficient of those practical applications, so can derive the good approximation value of transmission coefficient in the transmission channel with them.
Include an evaluation unit AE in first square 10.Include a transversal filter TF that transmission channel is simulated in this unit.Matrix calculator MR among the evaluation unit AE determines the filter factor CK of transversal filter TF according to equalizing coefficient CK
*Transform to filter factor CK from equalizing coefficient CK
*Be to calculate according to the formula of table 1.The calculator that is suitable for doing this conversion belongs to the prior art scope.
So the output signal of transversal filter TF is identical with signal on the equalizer E input basically, but it does not have the sampling phase error to the deviation that causes.Yet the time-delay among equalizer E and the transversal filter TF has caused the time-delay for receiving character stream e.For can with actual reception to character stream e and transversal filter TF in the character stream that simulates make comparisons, allow the character stream e that receives in time delay part VG, be subjected to suitable time-delay.
Therefore, two signals that can make comparisons on the output of time delay part VG and transversal filter TF, have been provided.Is correlator KR after the time delay part VG, it carries out correlation computations to character stream and known unique word RK.In summing circuit SR subsequently, on duty to various kinds with coefficient 1/ α, and from product, deduct sample value after two sampling clock period T of time-delay.The difference of gained is exactly corrected value △ K, and it is made up of useful component and interference component two parts.Useful component depends on the phase error of character sampling clock ZT, and it is used for proofreading and correct the phase place of ZT, and interference component is that the back vibration by the preceding vibration of the character after the unique word and the character before the unique word causes.
The back of transversal filter TF has similar in appearance to the correlator KD of said structure and summing circuit SD, produces corrected value △ K ".Because the signal that simulates in this branch road is no sampling phase error, thereby corrected value △ K " in do not have useful component, have only interference component.By adder A2, from the corrected value △ K that contains useful component and interference component, deduct the corrected value △ K that only contains interference component ", draw control information △ K '.
The road output of correlator KR also is added to the input of a frame detecting circuit RE.Frame detecting circuit RE produces frame clock RT, and this is that next step processing binary data Di and error of calculation information △ K ' are needed.
Whole first square 10 shown in Figure 2 is by the repetition rate work of character sampling clock ZT.Yet applicable control information △ K ' can only try to achieve from repetition rate is the unique word of frame clock RT.
Further understanding for the corrected value calculation can be consulted above-mentioned DE-OS 3,227 151; For the explanation of coefficient 1/ α, the reader can consult DE-OS33 33 714.
At the corrected value △ K that determines by evaluation unit AE " in, two other interference components contained.First interference component derives from the imperfect simulation of transversal filter TF to transmission channel.The source of second interference component is because the disturbing effect of preceding vibration and back vibration enters △ K with no phase error state ", and enter into the phase error that has of △ K.
The imperfect simulation of transmission channel is because the limited length of transversal filter TF is because filter factor CK on the other hand on the one hand
*Include error.Such among the embodiment as described, if filter factor CK
*Do not preset, but from the equalizing coefficient CK of adaptive equalizer E, lead, then the phase error of the non-adaptive state of equalizer and sampling clock all will cause the error of filter factor.All these errors all can both influence the data before and after the unique word, influence unique word itself again.At least, the filter factor error must be compensated the influence of unique word.
This compensation is to realize in the own process of calculating the unique word influence.Therefore, need determine the corrected value △ K that produces when unique word is by transversal filter TF, correlator KD and summing circuit SD in further relevant moment of evaluation " in this composition.This is a single constant corrected value KW, and it only depends on unique word and filter factor CK
*For unique word is the utmost point vantage of N bit Barker code, and corrected value is KW=-N(C1
*/ α-C
* -1); When 11 bit Barker codes, KW=-11(Cl/ α-C
* -1).At this moment, unique word is made up of the sequence (inverted sequence on time or polarity) of 11100010010 sequences or equivalence with it.Barker code has such characteristic, and its auto-correlation function equals N under situation about conforming to, and equals bare maximum 1 in other cases.In the embodiment of Fig. 2, corrected value KW calculates in matrix calculator MR, by adder Al with KW and corrected value △ K " addition.
The influence of other interference volume can be ignored.
Control information △ K ' is treated to adjustment control information △ P, that is the internal circuit of second square 20, be irrelevant with the mode that derives control information △ K '.
Fig. 3 shows the detailed block diagram of the preferred embodiment of second square 20.
In forming the path of adjusting with control information △ P, control information △ K ' pass through a main branch road, and also the function as the time passes through branch roads some times.In main branch road, signal is multiplied by the inverse of coefficient D at first by multiplier 221, by two adders 222 and 223, turns to integer again in sampling unit 225 then, and in amplitude limiter 227 amplitude limit to the value of 4 bits (for example from-8 to+7).The output of amplitude limiter 227 is exactly the control information △ P that adjusts usefulness.The output of adder 223 also is temporarily stored in the memory 224, feeds back to the in-phase input end of adder 223 behind the frame period Tr that delays time.The output that rounds unit 225 is temporarily stored in the memory 226, feeds back to the inverting input of adder 223 behind the frame period Tr that delays time.
Tell one road signal between adder 222 and 223, it is fed to memory 231 by switch 233 in 128 frame periods originally.Behind a frame period Tr, be returned to an input of adder 222 by multiplier 232.In multiplier 232, multiply by coefficient C.
After 32 frame periods originally, the signal that goes out along separate routes between the adder 222 and 223 is through adder 241 and its closure after 32 frame periods of switch 251() deliver to another branch road, contain multiplier 252, adder 253, memory 254 and another multiplier 255 in this branch road.The output one tunnel of multiplier 255 is returned to adder 241, and switch 233 is delivered to by adder 243 in another road.After 128 frame periods originally, switch 233 allows the output signal of adder 243 advance.A feedback line is also arranged in the above-mentioned branch road, is the input that outputs to adder 253 from memory 254.In multiplier 252, multiply by coefficient E, in multiplier 255, multiply by coefficient 1/16.
The output that is adder 241 of branch road arrives second input of adder 243 behind multiplier 242 again.In multiplier 242, multiply by coefficient 1/ α.
Whole second square 20 is the repetition rate work of clock RT frame by frame.So, arbitrary at described signal path through the fixed point place, each frame clock cycle of new digital value occurs once.In order promptly to influence the transient oscillation of this control in an advantageous manner, influence its stable situation again, switch different branch roads by switch 233 respectively with 251, and coefficient C, D and E press table 2 and change.
Table 2
N 0...15 16...31 32...127 128...
E - - 1 1/32
Switching between each stage includes the binary counter 211 that includes 7 grades by counting circuit 21 controls in the counting circuit, the the 4th, the 5th and the 7th grade tap of counter 211 provides signal N
4, N
5And N
7, in order to control above-mentioned switch and to change multiplication coefficient.Counting N 〉=16 o'clock N
4=1, N 〉=32 o'clock N
5=1, N during N=128
7=1.When the counter meter is completely counted (N=128), because signal N
7Be added to and a door input of 213 the counting stop by inverter 212.Be added with frame clock RT with another input of door 213, export the input end of clock of receiving counter 211 with door 213.Certainly, must guarantee counter reset when synchronous losing.
Third party's piece 30 among Fig. 1 is corresponding to the unit 7,8,9 among Fig. 2 in the top DE-OS that repeatedly mentions 32 27 151.4, and can form by the structure described in the document.
The structure of first square 10 also can be different from the embodiment shown in Fig. 2.Especially, the function of transversal filter TF can realize by a calculator, the function that this calculator also can realization matrix calculator MR.
In addition, the function of above-mentioned two branch roads can be closed And, thereby can reduce a correlator (KR or KD) and a relevant summing circuit (SR or SD).So the function of adder A2 can be to reach in signal path.Unique computing of finishing at output is to add corrected value KW.
If at the input of transversal filter TF or realizing that the data Di related with unique word put " O " by means of the frame clock on the input of calculator of transversal filter function, corrected value KW=O then; Its calculating subsequently and its addition in adder A1 just can have been saved.
The work available algorithm of correlator and summing circuit is explained, so their function can be finished by calculator.Calculator even also can be used for adaptive equalizer E.
According to the transmission rate of the character stream e that receives, and according to operational calculator, has variation separately between the realization in calculator that adopts and various function (function).In this case, must consider that each other function should realize with frame clock rate RT, and other functions should realize with character sampling clock rate ZT.
Claims (2)
1, at a kind of device of receiving terminal sampling clock phase place that is used for frame synchronization and makes receiving terminal and the character stream phase place synchronised that receives by transmission channel, includes the unique word that occurs with specific time interval in the character stream; This device comprises: a digital correlator, in order to form a cross-correlation function the unique word that stores from character stream and the receiving terminal that receives with the sampling of sampling clock repetition rate; A frame detecting circuit, in order to determine the frame clock according to the peaked position of cross-correlation function, this maximum is with the interval reproduction in frame period; A phase locking circuit supplies to adjust the control information that the sampling clock phase place is used in order to derive near the cross-correlation function value the detected maximum that repeats, and adjusts described phase place with this; Informating part in order to the regeneration character, it is characterized in that, has an evaluation unit (AE), it determines corrected value according to the character of regeneration and the transmission coefficient of transmission channel, and proofread and correct the value that is used to derive control information (△ P) with this, its feature is that also these corrected values have been considered the preceding vibration of the character before and after the unique word (RK) and the influence that the back vibration is caused.
2, device according to claim 1 also comprises the adaptive equalizer of a character stream that receives in order to equilibrium it is characterized in that the transmission coefficient of transmission channel is to derive from the equalizing coefficient that this equalizer (E) self adaptation is determined.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19873719659 DE3719659A1 (en) | 1987-06-12 | 1987-06-12 | DEVICE FOR FAST FRAME AND PHASE SYNCHRONIZATION |
| DEP3719659.6 | 1987-06-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN88103487A true CN88103487A (en) | 1988-12-28 |
| CN1009410B CN1009410B (en) | 1990-08-29 |
Family
ID=6329580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN88103487A Expired CN1009410B (en) | 1987-06-12 | 1988-06-11 | Facility for fast frame and phase synchronization |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US4878229A (en) |
| EP (1) | EP0294713B1 (en) |
| JP (1) | JPH0691521B2 (en) |
| KR (1) | KR960007403B1 (en) |
| CN (1) | CN1009410B (en) |
| AT (1) | ATE95356T1 (en) |
| AU (1) | AU592935B2 (en) |
| CA (1) | CA1299680C (en) |
| DE (2) | DE3719659A1 (en) |
| ES (1) | ES2046238T3 (en) |
| MX (1) | MX169964B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1957557B (en) * | 2004-05-20 | 2011-04-20 | 松下电器产业株式会社 | Signal detection device, signal detection circuit, signal detection method |
| CN101594180B (en) * | 2009-06-30 | 2012-12-19 | 北京华力创通科技股份有限公司 | Method and device for achieving bit synchronization and frame synchronization of text of receiver |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2531272B2 (en) * | 1988-08-11 | 1996-09-04 | 日本電気株式会社 | Frame synchronization control method |
| DE3832946A1 (en) * | 1988-09-28 | 1990-04-05 | Siemens Ag | Method for encoding digital time-division multiplex signals |
| ATE110507T1 (en) * | 1988-09-29 | 1994-09-15 | Siemens Ag | CIRCUIT ARRANGEMENT FOR EQUALIZING DIGITAL SIGNALS RECEIVED IN ANALOG FORM. |
| US5539751A (en) * | 1992-03-31 | 1996-07-23 | The Commonwealth Of Australia Of C/-The Secretary Of Defence | Demultiplexer synchronizer |
| AU668149B2 (en) * | 1992-03-31 | 1996-04-26 | Commonwealth Of Australia, The | Demultiplexer synchroniser |
| US6324225B1 (en) * | 1997-12-22 | 2001-11-27 | Stmicroelectronics, Inc. | Timing recovery for data sampling of a detector |
| US6363129B1 (en) * | 1998-11-09 | 2002-03-26 | Broadcom Corporation | Timing recovery system for a multi-pair gigabit transceiver |
| US6804317B2 (en) * | 2002-01-04 | 2004-10-12 | Intel Corporation | Digital frame determination method and apparatus |
| US7349507B2 (en) * | 2003-06-09 | 2008-03-25 | Intel Corporation | Extending PPM tolerance using a tracking data recovery algorithm in a data recovery circuit |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2478914B1 (en) * | 1980-03-19 | 1986-01-31 | Ibm France | METHOD AND DEVICE FOR INITIAL ADJUSTMENT OF THE CLOCK OF A SYNCHRONOUS DATA RECEIVER |
| JPS5840386A (en) * | 1981-06-30 | 1983-03-09 | ユニオン・カ−バイド・コ−ポレ−シヨン | Manufacture of low sulfur high quality coke from high sulfur decant oil |
| DE3201934A1 (en) * | 1982-01-22 | 1983-08-04 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | SYSTEM FOR TRANSMITTING DIGITAL INFORMATION SIGNALS |
| DE3227151C2 (en) * | 1982-07-21 | 1986-04-17 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Device for the reception-side phase synchronization of the sampling clock to the phase position of the characters of a received time-division multiplex character stream |
| DE3333714A1 (en) * | 1983-09-17 | 1985-04-04 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | CIRCUIT ARRANGEMENT FOR FRAME AND PHASE SYNCHRONIZATION OF A RECEIVING SAMPLE CLOCK |
| JPH0681167B2 (en) * | 1984-07-28 | 1994-10-12 | 富士通株式会社 | Receiver for digital wireless communication |
| US4627080A (en) * | 1984-11-23 | 1986-12-02 | At&T Bell Laboratories | Adaptive timing circuit |
-
1987
- 1987-06-12 DE DE19873719659 patent/DE3719659A1/en not_active Withdrawn
-
1988
- 1988-05-30 AU AU16757/88A patent/AU592935B2/en not_active Ceased
- 1988-06-01 MX MX011733A patent/MX169964B/en unknown
- 1988-06-03 ES ES198888108867T patent/ES2046238T3/en not_active Expired - Lifetime
- 1988-06-03 DE DE88108867T patent/DE3884465D1/en not_active Expired - Lifetime
- 1988-06-03 EP EP88108867A patent/EP0294713B1/en not_active Expired - Lifetime
- 1988-06-03 AT AT88108867T patent/ATE95356T1/en not_active IP Right Cessation
- 1988-06-03 CA CA000568668A patent/CA1299680C/en not_active Expired - Lifetime
- 1988-06-07 US US07/203,672 patent/US4878229A/en not_active Expired - Lifetime
- 1988-06-10 JP JP14185988A patent/JPH0691521B2/en not_active Expired - Lifetime
- 1988-06-11 KR KR1019880007063A patent/KR960007403B1/en not_active IP Right Cessation
- 1988-06-11 CN CN88103487A patent/CN1009410B/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1957557B (en) * | 2004-05-20 | 2011-04-20 | 松下电器产业株式会社 | Signal detection device, signal detection circuit, signal detection method |
| CN101594180B (en) * | 2009-06-30 | 2012-12-19 | 北京华力创通科技股份有限公司 | Method and device for achieving bit synchronization and frame synchronization of text of receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63318840A (en) | 1988-12-27 |
| KR890001320A (en) | 1989-03-20 |
| DE3884465D1 (en) | 1993-11-04 |
| MX169964B (en) | 1993-08-03 |
| KR960007403B1 (en) | 1996-05-31 |
| DE3719659A1 (en) | 1988-12-29 |
| AU592935B2 (en) | 1990-01-25 |
| ES2046238T3 (en) | 1994-02-01 |
| ATE95356T1 (en) | 1993-10-15 |
| JPH0691521B2 (en) | 1994-11-14 |
| CA1299680C (en) | 1992-04-28 |
| EP0294713B1 (en) | 1993-09-29 |
| US4878229A (en) | 1989-10-31 |
| CN1009410B (en) | 1990-08-29 |
| EP0294713A3 (en) | 1990-05-09 |
| AU1675788A (en) | 1988-12-15 |
| EP0294713A2 (en) | 1988-12-14 |
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