CN87106379A

CN87106379A - Modulator-demodulator and data communication system

Info

Publication number: CN87106379A
Application number: CN87106379.4A
Authority: CN
Inventors: 斯科特·安东尼·罗兹
Original assignee: TransCom Australia Ltd
Current assignee: Transcom Communication System Co Ltd
Priority date: 1986-08-22
Filing date: 1987-08-22
Publication date: 1988-03-30
Also published as: US5020077A; GB2219177B; KR880702022A; JPH01500954A; ZA876211B; WO1988001458A1; ZW16087A1; IL83602A0; IN169876B; CN1010540B; GB2219177A; HK121894A; GB8906557D0; KR960013301B1; IL83602A; CA1307323C; NZ221479A

Abstract

A kind of modulator-demodulator (18) and data communication system (10) of in high frequency (HF) medium, working of being used in particular for.Modulator-demodulator (18) comprises that an audio frequency cycle timer (52) is to detect the circulation from the data of the signal that receives, one bandwidth window (62) is to indicate uncertain circulation UD, so that make this circulation UD not influence the decoding decision, the byte that one bit rate timer (57) is formed by a plurality of described circulations with prediction end, one bit rate synchronizer is synchronous in the position mode of setting up modulator-demodulator (18) with the signal that receives, and a joint word synchronizer is synchronous to set up byte mode.

Description

The present invention relates to a kind of modulator-demodulator and data communication system, particularly emphasis is a kind of for what use in high frequency (HF) transmission medium, though it also is suitable for working in the higher-frequency medium very much.

Usually, the data communication in the direction-free medium resemble the air is to carry out with quite high speed and quite high frequency on quite short distance.The form of the data communication channel that uses in air certainly will limit the distance that can pass through, is generally line-of-sight distance as in microwave link and so on the time.With than the LF communication channel, such as, for example, very high frequency(VHF) (VHF) can reach long communication distance.

Generally, the modulator-demodulator of prior art has been designed in VHF or hyperfrequency (UHF) or microwave frequency or has resembled on the medium of the whole guiding phone and the coaxial cable work.The modulator-demodulator of this prior art mainly is designed to the transmission speed that reaches good.The electric state of the electromagnetic medium that modulator-demodulator adopted of prior art and characteristic are constant substantially.

By comparison, the communication on the HF medium is owing to constantly change and insecure electric state and characteristic thereby be complicated.These complex situations comprise burst noise, flutter fading, frequency drift, delay distortion or multipath, and usually with other more generic media compare and have bigger noise level.This noise comprises the uncorrelated random noise that is mainly produced by the stratospheric interference of propagating wave, receiver input thermal process and intermediate frequency thermal process.This noise is similar with band limit " in vain " coloured noise.Noise also comprises the related random noise that is produced by the interference of atmosphere, adjacent channel cross-talk, ignition noise or the like.The characteristics of this noise are that strong burst mode takes place, and show as the weak point that is superimposed upon on the signal and the form of strong periodic noise.

Common modem apparatus generally is can not the composition of HF medium be compensated, and therefore common modulator-demodulator is managed to be revised to make being applicable to that HF is unsuccessful.

The attraction of the modulator-demodulator of HF medium design is that data can transmit, and with respect to other media considerable expense interests be arranged in the base with at a distance or between the terminal of automobile on long distance (surpassing 10,000 kms).

Another attraction of HF medium is lower with the more not crowded band of communicating by letter of installation cost.

Yet the problem of the data of Chuan Songing is the recovery of the data that transmit and the problem of maintaining secrecy of this data up to now.

The invention provides and a kind ofly can on quite long distance, transmit employed modulator-demodulator of data and data communication system on the high frequency channel.

According to an aspect of the present invention, provide a kind of modulator-demodulator for data communication system.

A kind of modulator-demodulator of data communications equipment, described modulator-demodulator are arranged to be connected such as between transceiver such the band limit audio logic source and main frame, and modulator-demodulator is characterised in that it comprises:

A) data receiver, it has:

A) band pass filter, it has the input of being arranged to be connected to band limit audio logic source;

B) squaring circuit, be connected to an output of band pass filter, to produce a square-wave signal substantially that comprises a plurality of circulations with quick zero crossings, described all circulations are with all logical bit of the formation of the state variation between logic-high value and logic low value data, and all logical bit of described data form all logic bytes of data;

C) an audio frequency cycle timer is connected to an output of squaring circuit, and is arranged to draw the counting of delaying time between the expression continuous zero crossings in the same direction;

D) bandwidth window is configured to the counting of reception from the audio frequency cycle timer, and filters all countings;

E) a bit rate timer is configured to drawing another counting, and sends an interrupt signal to predict data bit when and have from the logic high to the logic low and the state variation from the logic low to the logic high a kind of conversely;

F) a bit rate synchronizer, described state variation in response to data bit, and be configured as that the predicted time that takes place when described state variation changes with virtual condition and change the bit rate timer when inconsistent, so that set up mode (bit-wise) synchronous communication;

G) a byte of sync device is in response to a specific bit string, to set up the byte mode synchronous communication;

H) error detector element is configured to the mistake in detection institute's rheme and the described byte, and with these detected mistakes of error code sign; And

B) a data transmission machine, it has:

A) generating apparatus is with described all circulations of institute's rheme of producing data; With

B) low-pass filter device connects to receive all circulations from generating apparatus, so that high fdrequency component is filtered out from all circulations that produce, produces a band limit audio logic signal.

According to another aspect of the present invention, provide a data communication system, it is characterized in that it comprises a transmitter-receiver, a computer installation and is connected between the two a modulator-demodulator, this modulator-demodulator is characterised in that it comprises:

Such band that a kind of modulator-demodulator of data communications equipment, described modulator-demodulator are arranged to be connected such as transceiver is limit between audio logic source and the main frame, and this modulator-demodulator is characterised in that it comprises:

A) data receiver, it has:

B) squaring circuit, be connected to an output of band pass filter, to produce a square-wave signal substantially that comprises a plurality of circulations that have quick zero crossings, described all circulations are with all logical bit of the formation of the state variation between logic-high value and logic low value data, and described data logical bit forms the logic byte of data;

C) an audio frequency cycle timer is connected to the output of squaring circuit, and is configured to the counting of delaying time between the expression continuous zero crossings in the same direction to draw;

E) a bit rate timer is configured to draw another counting and to send an interrupt signal to predict data bit when and have from the logic high to the logic low and the state variation from the logic low to the logic high a kind of conversely;

F) a bit rate synchronizer, it is in response to the described state variation of data bit, and the predicted time that is configured to take place when described state variation changes with virtual condition and can change the bit rate timer when inconsistent, so that set up a mode synchronous communication;

B) a data transmission machine, it has:

B) low-pass filter device by connecting to receive all circulations from generating apparatus, so that high fdrequency component is filtered out, produces a band limit audio logic signal from all circulations that produce.

Hereinafter will narrate the present invention with reference to Single Side Band High Frequency (SSB HF) communication and channel especially, though be appreciated that the application that other also can be arranged.

Now by example narrate the present invention with reference to accompanying drawing, wherein:

Fig. 1 is the block diagram of a kind of data communication system according to an aspect of the present invention, and this system comprises a kind of modulator-demodulator according to another aspect of the present invention;

Fig. 2 is the typical structure of the data communication system of Fig. 1;

Fig. 3 is the preferable data protocol for the modulator-demodulator use of Fig. 1;

Fig. 4 is the block diagram of data receiver of the modulator-demodulator of Fig. 1;

Fig. 5 is the schematic diagram of audio storage storehouse of the data receiver of Fig. 4;

Fig. 6 is the digital audio software bandwidth window of data receiver of Fig. 4 and the schematic diagram of clock extracting apparatus.

Fig. 7 is the bit rate synchronizer of data receiver of Fig. 4 and the schematic diagram of logical data decoder;

Fig. 8 is the schematic diagram of receiver frequency offset error means for correcting of the data receiver of Fig. 4;

Fig. 9 is the synchronous curve chart of bit rate of the bit rate synchronizer of Fig. 7, and the quick and low regime of pinning with all logical bit that receive is described, phase error is illustrated on the axis of ordinates, and the time is shown on the axis of abscissas with 3 milliseconds of graduation apparatus;

Figure 10 is the position and the byte synchronous exemplary timing diagram of the receiver of Fig. 4;

Figure 11 is the timing diagram that the task of the data receiver of Fig. 4 is served;

Figure 12 is the block diagram of data transmission machine of the modulator-demodulator of Fig. 1;

Figure 13 is the schematic diagram of audio logic data generating device of the data transmission machine of Figure 12;

Figure 14 is the schematic diagram of audio logic data encoder of the data transmission machine of Figure 12;

Figure 15 is Fig. 4's and the flow chart rebuild corresponding to the bit synchronization and the position of the data receiver of Fig. 5 and Fig. 6;

Figure 16 is Fig. 4's and rebuild or the flow chart of logic decoding corresponding to the byte of the data receiver of Fig. 7;

Figure 17 is the byte synchronous flow chart of the data receiver of Fig. 4; With

Figure 18 and Figure 19 are the flow charts that is received the transmission information sets by the data receiver of Fig. 4.

Shown in Figure 1 have a data communication system 10, it comprises an antenna 14, in order to collection and radiation signal, and is connected to a transceiver 16 that receives and transmit, and modulator-demodulator 18, transceiver 16 is docked with main frame 20 or similar device.

In the present embodiment, antenna 14 is configured to collect and radiation HF radio signal on the high frequency such such as air (HF) communication channel.

In the present embodiment, transceiver 16 is forms of HF transmitter-receiver, and is tunable substantially to all frequencies in the HF band.The common transmitter-receiver of the monolateral band of single worker (SSB) type of preferably a kind of usefulness of on voice-grade channel, communicating by letter of transceiver 16.

It will of course be appreciated that modulator-demodulator 18 of the present invention is designed to transmitting and receiving of data difficult especially on the HF communication channel compensated.Therefore, modulator-demodulator 18 easily can be fit to use with other communication media, other communication media, for example all HF citizen's band (CB) radio if any amplitude modulation (AM), or the VHF or the UHF of frequency modulation (FM) or land-line or communication media like that arranged.

Modulator-demodulator 18 comprises a data receiver 18a and a data transmission machine 18b.The HF signal of being collected by antenna 14 by demodulation is fed to data receiver 18a in the audio signal that the output 16a place of transmitter-receiver 16 produces.Data receiver 18a via input and output (I/O) port 20a(for example such as RS232 serial input terminal mouth, or STD computer bus standard port or ibm computer bus standard port or like that) be connected to main frame 20, by this input/output port 20a, main frame 20 can receive the data from the HF signal.

Main frame 20 is connected to data transmission machine 18b via I/O port 20b, thereby data are sent to data transmission machine 18b.Data transmission machine 18b is connected to the input 16b of transmitter-receiver 16, to send the coded data by transmitter-receiver 16 transmission.The all signals that appear at output 16a and input 16b are the audio logic data-signals of sound frequency, correspond respectively to the audio logic data that receive and the audio logic data of transmission.

The frequency of audio logic data-signal preferably is approximately half of audio bandwidth of transceiver 16, promptly is approximately 1500 hertz.

Easily, the logic high of data is by the audio representation that is about 1585 hertz, and data logic low level is by the audio representation that is about 1415 hertz.The frequency representation of logic high and low level is for separately being about 170 He Zhi.Select these frequencies, be because these frequencies in the limit of power of common radio transmitter-receiver.

Certainly, other frenquency representation also may be utilized.

In the context of present embodiment, each of data has the length of the duration that is about 3 milliseconds, and comprises the circulation of a plurality of audio frequency.For example, a logic high can conveniently be represented with 5 circulations of 1585 joseph audios (about 3.15 milliseconds of duration), and a logic low level can conveniently be represented with 4 circulations of 1415 joseph audios (about 2.83 milliseconds of duration).Importantly these two frequencies of logic high and logic low level are selected as about specified 1500 hertz equably at interval, so that two logical bit are provided equal error vulnerability to jamming.Be chosen to be 85 He Zhi here at interval.

Selected one 3 milliseconds duration of logical bit data bit, as trading off between bit rate and the position restorability.Wish that for bigger speed the short duration is arranged, then require the long duration for more reliable bit recovery.Also can adopt other duration to logical data bit.

In addition, the byte of data comprises 7 data bit and 3 parity check bits in the context of present embodiment.The calculating of 3 parity check bits will be discussed hereinafter.

Figure 2 illustrates a data communication network 22 that comprises a plurality of transmitter-receivers 16 and modulator-demodulator 18.Corresponding each transceiver 16 is connected to corresponding each modulator-demodulator 18, thereby and is connected to various types of main frames 20.The type of main frame 20 can comprise a human-like main frame 24, data logger 26, automobile or lightweight main frame 28 and mainframe type main frame 30 or the like.Automobile or lightweight main frame 28 can comprise radio data transmission/control unit, automobile printer unit and intelligent handheld communication key filling/display unit or the like.

In data communication networking 22, data can transmit on the quite long distance between any data communications equipment 10 in such as global range and networking 22.

Modulator-demodulator 18 is designed to and can works on the transformat below, these transformats comprise the point-to-point contact of SELCALL (promptly, you are state there), comprise the SELCALL+TEXT of short message text (transmission fast) and the MESSAGE TEXT of any length.Because the HF communication media is environment of difficulty for the communication of data, has worked out a kind of preferable data protocol that is used to transmit information sets TB ' s.Data protocol comprises that a preamble (PRE-AMBLE) PA, back are the first start byte ST1(FIRST START byte ST1), first information group heading byte HD1(FIRST BLOCK HEADER bytes HD1 then), one second start byte ST2(SECOND START byte ST2 then), packet DP(DATA PACKET DP then) and the second information sets header byte HD2(SECOND BLOCK HEADER bytes HD2) as shown in Figure 3.Data protocol also comprises the guiding LDY of the time-delay of the starting of following the transceiver that is used for posting a letter.

The composition of data protocol generally has following time range:

In the middle of minimum maximum (millisecond)

TLDY-guiding time-delay 50 150 500

The tPA-preamble duration 180

The first start byte duration 30 of tST1-

The tHD1-first information group heading duration 210

The second start byte duration 30 of tST2-

The tDP-packet duration 0 3,840 7650

The second information sets title duration 210 of tHD2-

Modulator-demodulator 18 uses in the SHORT transmission information sets and the data in the LONG transmission information sets.The former is used as call information group and definite signal message group and has zero data package length, and the latter is used to transmit variable data information (message text or SELCAL text).

Preamble PA preferably includes to have parity to be calculated as 010 form is 6 data bytes of 1010101.The structure of this preamble PA makes from height to low number of transitions to reach maximum concerning modulator-demodulator 18, is preferable to helping bit synchronization, as discussed below.When this number of transitions during less than maximum, modulator-demodulator 18 reaches bit synchronous speed and correspondingly reduces.

The first start byte ST1 comprises the byte of a monodrome, such as for example, and 03 hexagon (03 hex) of 01 hexagon (01 hex) of short message group (SHORT BLOCKS) and long information sets (LONG BLOCKS).The byte of sync of the reception data that the modulator-demodulator 18 uses first start byte ST1 helps import.

First information group heading byte HD1 comprises 7 bytes of data easily, the sender unit identification code SID that comprises two bytes, the destination authentication code DID of two bytes, one single state byte STAT, a data checks and (Checksum) byte D-CHK and a title inspection and byte H-CHK.

1 ± s that byte HD1 in the information sets title and HD2 are preferably complementary, their bit model does not conflict with start byte ST1 and ST2 like this.

The modulator-demodulator 18 that sender unit identification code SID sign is being posted a letter.Imagination sender unit identification code SID can comprise one or two speed code (fleet code), and the modulator-demodulator 18 that consequently only has identical speed code can be communicated by letter.

Authentication code DID sign in destination is wished transfer of data modulator-demodulator 18 thereunto.Imagination destination authentication code DID can comprise the code of two positions of a group, so that can wish to be transferred to a plurality of modulator-demodulators 18.

State byte STAT comprises the position of the pattern of the transmission information sets TB that transmits in order to the sign preparation.For example transmit the beginning that information TB is a message call, the perhaps beginning of a message confirmation, the perhaps end of a message call, the perhaps end of a message confirmation, a perhaps SELCALL call information group, perhaps a SELCALL confirms, perhaps END instruction, the data message group ID state that perhaps replaces, perhaps a packet effectively confirms or is like that.

Data checks and D-CHK be 7 rotation XORs in the packet DP of transmission information sets TB data inspection and.Transmitting information sets TB herein is a SHORT BLOCK, do not have data, and data checks and D-CHK has one 000 value.

When the single byte of having only data will be transmitted, it can be put in the data checks and D-CHK byte of SHORT information sets.

Title inspection and H-CHK similarly be one 7 rotation XORs inspection and, but all byte packet are contained among the title HD1 of current transmission information sets.

The second start byte ST2 is 02 hexagon of appointment easily and 04 hexagon that the LONG information sets is appointment except the SHORT information sets, so that beyond can distinguishing with the first start byte ST1, be similar in appearance to the first start byte ST1.If the first start byte ST1 is not received, so can not receive first information group heading HD1 yet.The second start byte ST2 uses the byte of the appointment that is different from the first start byte ST1, is not suitably received so that indicate information sets title HD1.

Packet DP only occurs in the LONG information sets.Packet DP preferably has a fixing length, such as, for example, 128 bytes, though also can adopt other length, for example, the length between 2 and 255 bytes.

The second information sets title HD2 is same as first information group heading HD1, gives 18 2 chances of modulator-demodulator to receive an effective faultless information sets title.If do not receive effective information sets title, transmission information sets TB must be removed, and is scheduled by 18 receptions of the modulator-demodulator in talking about because it may not have.

In data protocol, each byte has one 3 parity bit, is carried out the detection mistake to allow other byte, and indicates when mistake is detected.This represents the first order of the error detection of data communication system 10 of the present invention.Parity bit is to be determined by the counting of one of 7 of byte all logic in other.

Agreement also offers information the destination modulator-demodulator 18 relevant with the clock frequency of source modulator-demodulator 18.This information is to be provided by transistorized decision from logic high to the logic low data.

Therefore, do not wish to have the continuous string that resembles a logical value that may produce with common parity bit.The present invention has aforesaid parity bit, and by a predetermined value biasing, so that have 000000 byte to have different with 000, for example different parity bits with 001.This biasing also provides the burst of data.Data and title inspection and D-CHK and H-CHK also can comprise bias.

Yet data byte odd-even check only about 88% is reliable under noisy situation.Therefore, modulator-demodulator 18 comprises another error detector element, such as hereinafter with the narration Dynamic Group length data byte error mark.

Data protocol of the present invention allows the synchrodata byte transmission between modulator-demodulator 18, so receiving modem 18 can carry out the prediction location of each data bit and each data byte.This provides single byte to recover and provide the location of the information-related byte of mixing up in transmission information sets TB.

In data protocol, need such error detection mechanism like this, to plan to bear the difficulty that is run into the HF medium such as signal fadeout and signal interference and noise.

Receiver 18a shown in Figure 1 comprises that one is connected to the band pass filter 40 of output 16a, and easily, filter 40 is a pair of quad active filters, is arranged to leach below 1415 hertz and the frequency more than 1585 hertz.This frequency that leaches comprises some noise component(s)s and the modulation that caused by multichannel or the like.

Filter 40 comprises that one has the output 42 of audio voltage signal, and this audio voltage signal is by being about 1415 hertz audio pulse string and forming corresponding to 1585 hertz the audio pulse string of being about of logic high data corresponding to the logic low data.Output 42 also can have the audio pulse string that departs from the conspicuous frequency of these preset frequency hundreds ofs.

Output 42 is connected to squaring circuit 44, such as the zero crossings detector, is arranged to pass through zero transformation that lies prostrate to detect in audio signal, and transformation or positive electricity are pressed onto the transformation of negative voltage, and perhaps negative electricity is pressed onto the transformation of positive voltage.Squaring circuit 44 comprises that one has the output 46 of the voltage signal of digital nature, the transformation that this signal has high level, low level and circulates corresponding to numerical data between the two.

Output 46 is connected to the microprocessor 50 of common pattern, and microprocessor 50 is designed to filtering, decoding and reconstruction are carried out in the numerical data circulation that receives.The trailing edge of 50 pairs of numerical data circulations on output 46 of microprocessor in the present embodiment reacts.

Receiver 18a also comprises an audio frequency cycle timer 52, and its input 54 is connected to the output 46 of squaring circuit 44.The output 56 of audio frequency cycle timer 52 is connected to microprocessor 50.

Audio frequency cycle timer 52 is counted with the fixedly rate of change between the continuous numerical data circulation trailing edge.The counting of Huo Deing is the cycle of representing each numerical data circulation like this, and therefore represents its frequency.For example, the relation between the frequency that circulates of counting and numerical data can for:

Cycle frequency f=2000000 is conspicuous

Audio frequency cycle timer counting

Microprocessor 50 has a timing crystal, and in the present embodiment, the frequency of this timing crystal is 2 megahertzes, and the counting and the cycle frequency of audio frequency cycle timer interrelated.

Receiver 18a also comprises a bit rate timer 57 that is connected to microprocessor 50 via its output 57a.

Easily, bit rate timer 57 is to have peaked downward counter, and is configured to send an interrupt signal to microprocessor when arriving zero count.In the present embodiment, be about 3 milliseconds during between these interrupt signals, as discussed above.

The maximum count of bit rate timer 57 (or initial counting) can be adjusted by microprocessor 50, allows the bit rate of data receiver 18a to depart near specified 3 milliseconds of bit rates.

Microprocessor 50 is designed to comprise audio storage storehouse 58, as shown in Figure 5.Audio storage storehouse 58 comprises the memory cell of 16 registers or microprocessor 50 easily, and the layer (level) 60 of 16 storehouses is provided.Each layer 60 of storehouse 58 is configured to the cycle of a circulation of the expression Digital Logic data that are received in output 46 and the data of logic state.Cycle is measured by audio frequency cycle timer 52.58 wraparounds of audio storage storehouse form, so that become the storehouse for no reason 58 with 16 existing layers 60.Each trailing edge in the Digital Logic data interrupts microprocessor 50, and starting is called the task of TASK1, and this task instructs the reading of microprocessor 50 with the counting of obtaining the last circulation of representing the Digital Logic data in audio frequency cycle timer 52 especially.So microprocessor 50 according to TASK1, resets audio frequency cycle timer 52, make the cycle that begins again to count with the consequential circulation of determining the Digital Logic data, occur until another trailing edge, send another interrupt signal or the like.

Microprocessor 50 also is designed to include a bandwidth window 62, as shown in Figure 6.Bandwidth window comprises four time cycle threshold T1, T2, T3 and T4, respectively representative: maximal audio cycle timer 52 countings that minimum audio frequency cycle timer 52 countings that maximal audio cycle timer 52 countings that minimum audio frequency cycle timer 52 counting of circulation becomes logic low, circulation become logic low, circulation become logic high and circulation become logic high.

Audio frequency cycle timer 52 counting of circulation be lower than threshold T1, between threshold T2 and T3 or surpass the occasion of threshold T4, circulation is assumed that uncertain, such as makeing mistakes because of noise, and is marked as uncertain (UD among Fig. 5).Counting in circulation is a occasion between threshold T1 and T2, and circulation is determined to become logic low by microprocessor 50.Counting in circulation is a occasion between threshold T3 and T4, and circulation is determined to be and is logic high.

Such as the count cycle and the frequency of circulation of narration be proportional, therefore do so more useful be since threshold T1, T2, T3 and the T4 of bandwidth filter 62 with relevant with frequency.

In the logic level of output 46, be stored on the audio frequency storehouse 58 with the cycle of circulating via output 63, at layer 60 place as the circulation of determining by bandwidth window 62.

Microprocessor 50 also is designed to comprise clock extracting apparatus 64.Clock extracting apparatus 64 comprises a memory register 66, and this memory register 66 is configured to comprise a copy from the logic state of the last circulation of the Digital Logic data of audio frequency storehouse 58.Clock extracting apparatus also comprises a comparator 68, and comparator 68 has an input to be connected to memory register 66, and another input is connected to the output 63 of bandwidth window 62.

Comparator 68 is identified and has just been stored the circulation on the storehouse 58 into and be stored in similitude between the logical value of the last circulation in the register 66.In existing circulation is uncertain occasion, and clock extracting apparatus 64 interrupts relatively triggering an output 70.Determine the identical occasion of last circulation in last circulation and the register 66 on the storehouses 58 at comparator 68, it triggers an output 72, read bit rate timer 57 with indication microprocessor 50 via output 57a, the counting of the bit rate timer 57 when determining on storehouse 58 last circulation terminal, and this counting is stored among the register LSTT1M.

3 milliseconds of duration of bit rate timer 57, continue to reach approximately 4 circulations of logic low numerical data and 5 circulations of logic high numerical data.Be accredited as under last circulation on the storehouse 58 situation identical at comparator 68 with the circulation in the register 66, at that time in the logical data circulation of output 46 still at the centre or the end of logical bit.Therefore, the time in register LSTT1M can represent occur data bit in the middle of time of circulation, or time of the last circulation during the finishing of data bit.Such situation be can not determine, until till next circulation on the output 47 is loaded onto on the storehouse 58.

Comparator 68 is also determined last circulation on storehouse 58 and the last circulation in the register 66 not simultaneously, is provided with to make output 74 effective.Effectively output 74 ends that are illustrated in last circulation are stored in a logic high that occurs on the counting of register LSTT1M and arrive high-order transformation to low level or low level.

Effectively output 74 also is used to guide new logical value to enter register 66.It should be noted that and when not having detected difference in the circulation, just do not need to upgrade register 66.

The bit rate of modulator-demodulator 18 of transfer logic data or the information of clock are provided with regard to this transformation.It must be noted that the bit rate of extracting from the agreement of transmission information sets TB will not be constant, and will be along with transformation is the paramount or logic high of logic low to low and change.Therefore, between interruption that produces by bit rate timer 57 and bit rate, will there be a phase error by clock extracting apparatus 64 extractions.

Microprocessor 50 also is designed to include a bit synchronizer 76, as shown in Figure 7.Bit synchronizer is connected to output 57a, so that be triggered when interrupt signal receiving from bit rate timer 57.

Bit synchronizer 76 is read register LSTT1M, and the value of its inside was compared with the time of interruption.In other words bit synchronizer 76 determine the actual bit speed extracted from transmission information sets TB and the bit rate predicted by bit rate timer 57 between phase error.

Obtaining bit synchronization needs the prediction of this bit rate, to help the retrieval of all data bit.

Having under the situation of phase error, bit synchronizer 76 sends a signal to bit rate timer 57 via output 57a, to remove to increase or reduce the counting of its inside with a quite little number, so that increase or reduce the approaching actual speed of being extracted by clock extracting apparatus 64 of cycle of bit rate timer 57.

When data receiver 18a was receiving preamble PA, bit synchronizer 76 for example added and deducts 10 times greater than above-mentioned those number, so that reach quite approaching bit synchronization during 180 milliseconds of preamble PA from the counting of bit rate timer 57.

The variable bit rate that the variation of a phase error is arranged between speed timer 57 on the throne and the bit rate extracted, so that when receiving data, the error in the bit rate of extracting, not compensation of phase error strictly.

This depicts in Fig. 9, and the time is illustrated on the abscissa with 3 ms intervals, and phase error PE is illustrated on the ordinate.

During preamble PA, require to proofread and correct fast or pin, during Data Receiving, require to pin at a slow speed.

On this meaning, bit synchronizer 76 plays phase-locked loop (PLL) effect of a speed of fixing.Go up computing at the symbol of phase error (promptly leading or lag behind), rather than computing on the numerical value of phase error.Requiring this computing is that bit synchronizer 76 produces some vulnerabilities to jamming for the error that the extraction because of the mistake of the bit rate of coming from transmission information sets TB causes.

It should be noted the bit rate that counting in the speed timer 57 on the throne should not equal to extract, because the bit rate of choosing has error, and this operation can enlarge this error.

Have been found that bit synchronization can be kept uncertain circulation UD if more effectively circulation is received.

Microprocessor 50 also is designed to include a logical data decoder 78, and its input 80 is connected to bit synchronizer 76.Logical data decoder 78 comprises a circulation accumulator device 82, is configured to read out from the logical value of storehouse 58 in last four circulations of the logical data of output 47.Be used for limiting the logical value of the position that rigidly connects the data of receiving from the logical value of last four circulations of storehouse 58.Should be noted that on storehouse 58, may exist, for example produced under the additional loop condition at noise more than four circulations and relevant with present position.

Because noise and so on problem, last four layers 60 of storehouse 58 can comprise the logical value of logic high and logic low, ignore uncertain UD logic level.Logical data decoder 78 also comprises a logic level identification apparatus 84, and it is connected to circulation accumulator device 82 by an input 86.Logic level identification apparatus 84 is configured to add up with the logic-high value that will be read from storehouse 58 by circulation accumulator device 82 and the occurrence rate of logic low value, and determines that any in 4 circulations is the most frequent.The most frequent occurrence rate is used as the logic level of the data bit that receives by logic level identification apparatus 84.

In the present invention, bit synchronization is absolutely necessary, so that make logic level identification apparatus 84 can read 4 circulations from storehouse 58, these circulations are relevant with last logical data bit.

Logic level identification apparatus 84 comprises an output 88, and this output 88 is carried to one 10 bit shift register 90 with the logical value of the position of the data of evaluation.

Be recycled accumulator device 82 in the continuous circulation of the logical data of output 47 and add up, and all result bits of data are stored in the 10 bit shift memories 90.

Preparation is stored into the parity check bit of byte of last 3 bit representation data of 10 bit shift register 90.

Logical data decoder 78 also comprises a parity calculator device 92, and it is connected to 10 bit shift register 90, with 3 parity check bits of 7 positions of calculating the data in 10 bit shift register 90.Comparator 94 will be from the parity check bit comparison of the parity check bit of the calculating of parity calculator 92 with the byte of data in shift register 90, with output 96 set for effectively to represent unanimity or the difference in each parity bit.

Flag code generator 98 is connected to output 96 to replace the byte of data via input 99, and for the byte of these data, parity check bit does not conform to error code such as BF hexagon (hex).At input 99, all effective bytes with data of consistent parity check bit are not subjected to the influence of flag code generator 98.

Flag code generator 98 has an output 100 to be connected to the storage device of further handling into by receiver 18a 102.

This processing comprises the frequency of the appearance that monitors error byte.Data receiver 18a keeps the error count in the register, and this error count increases when error byte occurring and reduces when effective byte occurring.Error count surpass one such as, under the occasion of the value of the setting as 50, all bytes that receive are scrapped.

This except also comprising the processing by Dynamic Group length data byte error covering appts 104, device 104 is connected to storage device 102.Error covering device 104 is configured to the adjacent bytes of the data of transmission information sets TB in the storage device 102 relatively and records the position of appearance of the byte of error code.

Follow the byte back of some error coded and at the number in abutting connection with the valid data byte of the byte front of other error coded, relatively by error covering device 104.Under the number situation that outnumbers effective byte of error coded byte, effective byte is presumed to be to mistake is arranged, and is masked as error byte by error covering device 104.For example, when the byte back of two error flags was the byte of an effective byte and an error coded, then effective byte was assumed that suspicious and as possible error byte, and is indicated.

By this way, error covering device 104 is dispersed in the mistake in the data of the transmission information sets TB that receives in order to advance notice.

This processing also comprises packet image cladding system 106, and this device 106 is configured to cover the packet DP ' s of the first transmission information sets that comprises the error coded byte with second and other second and other (nearly 8) packet DP that transmits again of the identical traffic information sets that also may comprise the error coded byte.

The image cladding system 106 from all above-mentioned packet DP ' s, takes out the valid data byte, and microprocessor 50 in the packet video memory, the creation the one new packet DP that comprises from the effective byte of all this packet DP ' s.

This processing is called covering, and is used for reaching the integrality of finishing the data of receiving by transmitting again.

Packet image cladding system 106 is connected to receiver output 20a, with the packet DP that sends error correction to main frame 20.Last packet DP also can be used by receiver 18a, as narrating here.

Microprocessor also is designed to include a receiver frequency offset error means for correcting 110, as among Fig. 8 schematically shown in.

Frequency offset error means for correcting 110 comprises a frequency analysis device, and it is configured to carry out frequency analysis with 16 circulations to the data in the storehouse 58.This analysis is carried out during the preamble PA of transmission information sets TB.

The frequency analysis device is read all cycles that are included on the storehouse 58, and with first the circulation duration and each other recycle ratio.In this comparison, the frequency analysis device adds a narrow bandwidth window around first circulation, represents about 5 hertz such as the 0.9%(in the cycle that for example is about circulation with the frequency term).The frequency analysis device is counted the number of other circulations with the cycle in the window on storehouse 58 then.

This counting is that 16 all on the storehouse 58 circulations are carried out.Because used two frequencies, that is, 1415 hertz and 1585 hertz, two circulations with different cycles size are usually expressed as the highest counting.It is the cycle of supposition with two circulations of the highest counting for for logic low with for the actual cycle of logic high that frequency analysis is installed on.This cycle is relevant with the frequency of logic high and logic low circulation as mentioned above.

Being separated by when the frequency with two circulations of the highest counting surpasses 100 hertz or surpass a set point at the highest counting, such as, for example, surpassing possible 8 is 4 o'clock, error correcting device supposes that effective two voice data communications set up.

Because drift in transmitter-receiver 16, actual reception to frequency can not equal 1415 hertz of rated values and 1585 hertz exactly.Departing from is the drift error DE of a tolerance frequency offset correction.The frequency analysis device is adjusted bandwidth window 62, so that be placed on the center of two frequencies that actual reception arrives.

The boundary of the counting of threshold T1, the T2, T3 and the T4 that are equivalent to Fig. 6 of audio frequency cycle timer 52 is calculated as follows:

Audio frequency cycle=XTAL

Timer boundary Ti-De

Ti is the specified boundary of bandwidth window 62 in the formula

That is, the T1=1350 largest logical is low

The minimum logic low of T2=1480

T3=1520 largest logical height

The minimum logic high of T4=1650

DE is a numeration that is equivalent to frequency offset error

XTAL is the frequency of the crystal of microprocessor 50

Frequency offset error is assumed to identical for logic high with logic low circulation both.

Because bandwidth window 62 is adjusted by the frequency error offset correction device, have greater than half the data of frequency error skew of difference on the frequency between the circulation of logic high and logic low, still can be received and be corrected.It is contemplated that present embodiment is for being possible to the correction up to+/-200 hertz frequency error skew during the preamble of transmission information sets TB.In addition, the frequency drift of the reception period in the data message group up to 40 hertz also is possible.

The shared microprocessor 50 of the data transmission machine 18b of modulator-demodulator 18 and data receiver 18a.

Data transmission machine 18b also comprises an output 120, and output 120 is connected to low pass filter 122, such as, for example, the active bandpass filter (two pale active tow pass filter) that drags of double grid.The digital audio that output 120 delivery and output 47 in data receiver 18a receive is according to similar digital audio-frequency data.Filter 122 is removed high order harmonic component from the digital audio certificate, to produce a band limit digital audio at output 124.

Output 124 is coupled to level amplifier 126, to amplify the signal from filter 122.

Audio frequency is isolated and impedance matching transformer 128 is connected to amplifier 126 via input 130.Transformer 128 is connected to the output 16b that is transformed into transmitter-receiver 16.Transformer 128 can supply balance ground connection or imbalance to be connected to the usefulness of transmitter-receiver 16.

Data waiting for transmission deposit storage device 102(Fig. 7 via output 20b with byte mode by main frame 20).

Microprocessor 50 is designed to include an audio logic encoder 142, as shown in figure 14.Connected encoder 142 is with the interruption of origin self-alignment speed timer 57 and trigger, and this bit rate timer 57 is set to the cycling by 3 milliseconds.

Encoder 142 comprises a device 144, to read out the byte from 7 positions of the next one of storage device 102.So 7 positions are loaded in 10 bit shift register 146 as parallel-to-serial transducer work.Parity generator 148 calculates 3 bits parities that also are loaded into register 146.

Bit check device 150 is connected to register 146 by its output 152.One output 154 of bit check device 150 is connected to device 156 to produce the cycle of logic low circulation, and another output 158 is connected to device 160 to produce the cycle of logic high.Register 162 is connected to device 156 and 160, and is configured to the cycle with storage device 156 and 160 circulations of using.

Microprocessor 50 also is designed to include an audio logic data generating device 164, as shown in figure 13.Data generating device 164 comprises device 166, to read out the next semi-cyclic cycle from register setting 162; And another device 168, so that this counting is put into audio frequency cycle timer 52.Audio logic data generating device 164 comprises that one is connected to the circulating generator 170 of device 168.Circulating generator 170 has an output 172, and this output 172 is triggered in each half circulation.Preferably produce four complete circulations and produce five complete circulations in the present embodiment for the logic high data for the logic low data.Output 172 is connected to the output 120 of microprocessor 50.

According to each interrupt signal from bit rate timer 57, another position is encoded, and produces the number of the circulation of a correspondence in output 172.

When circulating at last of position exported 172 generations, the cycle count that bit rate timer 57 interrupts next of guiding entered register 162, and this cycle count is used by data generating device in the circulation of this data bit of generation.

In case be transmitted from register 146 all positions, the byte of another data is loaded into register 146.

By data generating device 164 positions with transmission that produced is that phase place is consistent, and respectively have respectively the circulation in 4 or 5 digital audio of 1415 hertz and 1585 hertz, the phase place unanimity is indispensable to reducing the distortion between the data bit and helping by the method that data receiver changes with prediction bits bit rate to be extracted out from data.

Require modulator-demodulator 18 to comprise that a watchdog timer circuit is arranged to the recurrent pulses (with the operation of indicating correct) that produced by microprocessor 50 to receive, and when in the time of setting, not receiving pulse, little reason machine 50 is resetted.May be significant like this when microprocessor 50 pins owing to electric power is inadequate.

During use, data communication system 10 of the present invention is used in quite long distance, on global range, and with the monolateral band of single worker (SSB) HF transmitter-receiver 16, on the HF communication channel, transmission and reception data.

As depicted in figure 2, data can be at personal computer 24, data logger 26, automobile unit 28 or mainframes 30 or are are similarly received and dispatched between the equipment.

Now consult Figure 15 to Figure 19 and narrate the work of data receiver 18a in the process that receives byte and byte is deciphered.

Figure 15 represents that program comprises functional block 180 to 188 from the program of the position demodulation of the transmission information sets that receives.In functional block 180, data receiver 18a that accept filter with (squared-up) rectangle digital audio logical data, the circulation of these data has two frequencies (Fig. 4 and Fig. 8) that play a major role.Audio frequency cycle timer 52 is measured the cycle of each circulation according to receiving, and produces the counting in a this cycle of representative.

In functional block 182, the logical value of each circulation is definite by bandwidth filter 62, and is stored in layer 60 place on the audio frequency storehouse 58.

In functional block 184, frequency error correction device 110 is read 16 layers 60 of storehouse 58 simultaneously, and carries out a simple frequency analysis to determine about frequency of logic high circulation and logic low circulation.Data in functional block 184 on the storehouse are preamble PA(Fig. 3 of transmission information sets TB) data.

In case about frequency is determined, as mentioned above, they compare for 1415 hertz and 1585 hertz with logic low and the high rated frequency that circulates respectively, and calculate drift error DE.In functional block 182, use drift error DE) to adjust threshold T1, T2, T3 and T4(Fig. 6 of bandwidth window 62.

In functional block 186, the transformation of 64 pairs of positions from a position to another opposite logical value of Clock Extraction apparatus is searched for simultaneously.The time of the appearance that changes is recorded, and bit rate timer 57 maximum count value are adjusted.

The occasion of the speed counter 57 leading bit rate of extracting on the throne, adjustment are to count a little to increase, and vice-versa, bit rate timer 57 is leading herein.

In the preamble PA section of transmission information sets TB, the phase error between the bit rate of the bit rate of extraction and timer 57 can be different significantly.To the speed of extracting, in order to realize the 57 fastish pinnings of bit rate timer, bigger change is made in the maximum count of bit rate timer 57.

In case near reaching, the size of counting alternation can reduce, and has the slower pinning (Fig. 9) that the logic transition of mistake is had better vulnerability to jamming to provide synchronously.

In functional block 188, circulation accumulator 82 is read last four circulations from storehouse 58 then, and logic level identification apparatus 84 is determined the logical value from the position of the data of all circulations.Uncertain circulation is left in the basket, and is identical occasion at the number of logic high and logic low circulation, and the position is presumed to be and is logic high.The position of data is received and demodulation by the program of Figure 15.

The program of simultaneous decoding of the byte of data has been shown among Figure 16, and program comprises functional block 190 to 198.

In functional block 190, not correction (indireted) data bit from the result of the program of Figure 15 is sequentially deposited into shift register 90, and these positions comprise 7 data bit and 3 parity check bits.In functional block 192, parity generating means 92 is 7 data bit computation of parity bits.Parity bit of calculating and the parity check bit comparison that receives, and when a difference was arranged in the parity bit, functional block 194 was an error byte with byte flag.

So the speed of byte error is examined in functional block 196, and if speed is too high, functional block 196 control data receiver 18a are to ignore the data byte that receives.7 positions the data byte that receives deposited in storage device 102 for further handling.

In Figure 17, shown a byte synchronous program.This program comprises functional block 200 to 206.

In functional block 200, data receiver 18a monitor to seek the storage device 102 of the first start byte ST1, so that with the byte of sync of back data.

In functional block 202, the value of start byte is examined, to determine whether the being first start byte ST1 or the second start byte ST2.Functional block 204 waits and receives first information group heading HD1 then.

Functional block 206 is under the occasion that the first start byte ST1 is not received, and HD1 is indicated as not receiving with first information group heading.

Shown the program that receives transmission information sets TB in Figure 18, this preface journey comprises functional block 208 to 214.

In functional block 208, start byte ST1 or ST2 are checked by data receiver 18a, to determine that transmission information sets TB is a SHORT information sets (ST1=01 hexagon, the ST2=02 hexagon) still be a LONG information sets (ST1=03 hexagon, the ST2=04 hexagon), indicate whether that packet DP has 0 byte or 128 bytes.

In functional block 210, the packet DP of 128 bytes is stored into storage device 102.In functional block 212, data checks and byte among the title HD1 are read out, and to check whether data are transmitted inside, instruct such as a SELCALL.

In functional block 214, for the second title HD2 and title HD1 are made comparisons in further error correction.

Figure 19 illustrates the program of the data that receive in the further processing storage device 102, this program comprises functional block 216 and 218.In functional block 216, two title HD1 and HD2 are superimposed, eliminate error byte with attempt.Destination sign DID byte is examined, and is specific modulator-demodulators 18 with the data that determine whether to receive.

In functional block 218, one or several version of the same transmission information sets TB that the data byte (except the error byte) among the transmission information sets TB is transmitted again and again is overlapping, so that set up a faultless transmission information sets.

The typical duration of above-mentioned various programs shown in Figure 10, waveform A represents to take from the time of search preamble PA, the time that waveform B is represented to determine the frequency error skew and adjusted bandwidth window 62, waveform C represents to take from the quick bit synchronous time, and waveform D represents to take from the time of search start byte and the time that waveform E represents to recover to transmit information sets TB.

Figure 11 illustrates regularly schematic diagram of typical case of the present invention, wherein waveform F represent with 3 ms intervals in real time, waveform G represents the audio logic data that receive, waveform H represents the actual frequency of the audio logic data that receive, waveform I is illustrated in the rectangle audio frequency of output 47, waveform J represents to take from the interrupt signal of the trailing edge of waveform I, with routine processes circulation according to Figure 15, waveform K represents to take from the interrupt signal of bit rate timer 57 of the variation in the logic state of prediction data and waveform L and represents that microprocessor 50 handles the time that other work can be adopted.

By utilizing the present invention, data can be transmitted on the global range of HF radio wave, and error recovery.

Because equipment 10 of the present invention can work in the HF medium, can seldom be to work effectively among hostile VHF or the UHF usually such as those also therefore at other radio mediums.

Conspicuous modifications and changes still are deemed to be within the scope of the present invention for those of ordinary skill in the art.

Claims

1, the band that a kind of modulator-demodulator of data communications equipment, described modulator-demodulator are configured to be connected such as transceiver is limit between audio logic source and the main frame, and modulator-demodulator is characterised in that it comprises:

A) data receiver, it has:

B) squaring circuit, be connected to an output of band pass filter, to produce a square-wave signal substantially that comprises a plurality of circulations with quick zero crossings, described all circulations are with all logical bit of the formation of the state variation between logic-high value and logic low value data, and all logical bit of described data form the logic byte of data;

C) an audio frequency cycle timer is connected to an output of squaring circuit, and is configured to draw the counting of delaying time between the expression continuous zero crossings in the same direction;

E) a bit rate timer is configured to drawing another counting, and sends an interrupt signal to predict data bit when and have from the logic high to the logic low and the state variation from the logic low to the logic high a kind of vice versa;

F) a bit rate synchronizer in response to the described state variation of data bit, and is configured as that the predicted time that takes place when described state variation changes with virtual condition and changes the bit rate counter when inconsistent, so that set up a mode synchronous communication;

H) error detector element is configured to detecting the mistake in institute's rheme and the described byte, and with the mistake of these detections of error code sign; And

B) a data transmission machine, it has:

B) low-pass filter device connects to receive all circulations from generating apparatus, so that high fdrequency component is leached from all circulations that produce, to produce a band limit audio logic signal.

2, a kind of modulator-demodulator according to claim 1, it is characterized in that, bandwidth window comprises four counting thresholds that limit two bands, within these two bands one of one of the circulation of described counting and logic-high value or logic low value circulation relevant, described counting is relevant with a uncertain logical value of described circulation beyond these two bands.

3, a kind of modulator-demodulator according to claim 1, it is characterized in that, data receiver comprises an audio frequency storehouse with a plurality of layers, described audio frequency stack arrangement becomes of correspondence of the described logical value of one of of in each layer described counting of storage and all circulations, and the audio frequency storehouse is formed counting and the logical value that layer adjacent in an endless loop so that these layers comprises adjacent circulation in the circulation.

4, according to claim 1,2 or 3 described a kind of modulator-demodulators, it is characterized in that, the bit rate synchronizer of data receiver comprises a comparator, one first data register and one second data register, first data register has an expression to be stored in the memory of the logical value of up-to-date circulation on the audio frequency storehouse, comparator is connected so that logical value in first register and the logical value from bandwidth window output from existing circulation are compared, comparator responds these logical values, so that in the identical occasion of logical value, it is loaded into second register with the bit rate timer to the further counting of said existing circulation, and comparator is in response to described logical value, so that not simultaneously at them, comparator will be loaded into second register from the numeration of the said up-to-date circulation of audio frequency storehouse, with one of said variation of the logic state of the position of expression data.

5, a kind of modulator-demodulator according to claim 4, it is characterized in that, the bit rate synchronizer comprises that one has in order to the further counting with counting in second register and bit rate timer and compares bit synchronizer with the device of determining its phase error, and another is in order to change the bit rate timer by a fixed value relevant with the absolute phase error, so that the bit synchronous device of bit rate timer and described data.

6, according to the described a kind of modulator-demodulator of any one claim in the claim 3 to 5, it is characterized in that, data receiver comprises a frequency offset error means for correcting, it is configured to read all countings from the audio frequency storehouse, the frequency offset error means for correcting comprises a frequency analysis device, be configured to determine two countings, a counting is relevant with the most probable counting of one of logic-high value circulation, another counting is relevant with the most probable counting of one of logic low value circulation, the frequency offset error means for correcting is configured to so that above-mentioned two countings and two defect countings are compared, to determine an one error amount, the frequency departure error correction device also is configured to change value that equals error amount substantially of counting threshold, so that make bandwidth window consistent with circulation.

7, a kind of modulator-demodulator according to claim 6, it is characterized in that, the frequency analysis device is configured to produce a quite narrow time window near individual count, the frequency analysis device is configured to also that other counting occurs so that what to determine to have in each described time window, and it is described most probable countings that logic-high value circulation and logic low value circulate that the frequency analysis device also is configured to determine that therein maximum time windows appears in other countings.

8, according to the described a kind of modulator-demodulator of any one claim of claim 2 to 7, it is characterized in that, data receiver comprises the circulation accumulator device of a response from the interrupt signal of bit rate timer, and circulation accumulator device is configured to read the logical value about the up-to-date circulation of a required number from the audio frequency storehouse; And a logic level determines device, is configured to more described logical value and determines two logical values which plays a major role that this main value is confirmed as the logical value of the position of data, and this logical value and described up-to-date circulation have relation.

9, a kind of modulator-demodulator according to claim 8 is characterized in that, the logic low value position comprises 4 circulations, and the logic-high value position comprises 5 circulations, and the cycle of the circulation of low value position is the cycle greater than the circulation of high value position.

10, a kind of modulator-demodulator according to claim 5, it is characterized in that, the data bit of bit rate synchronizer response preamble type, so that change the bit rate timer to compensate the big or small degree of described phase error, greater than compensation, improve the realization rate of position mode synchronous communication between described preamble period so substantially to other forms of data bit.

11, a kind of data communication system is characterized in that, it comprises a transmitter-receiver, a computer installation and be connected between the two a modulator-demodulator that modulator-demodulator has the described feature of any one claim according to the front.

According to a kind of data communication system of claim 11, it is characterized in that 12, transmitter-receiver is the high-frequency single side band type.