CN103095409B - The interpretation method of safety command receiver safety control command - Google Patents
The interpretation method of safety command receiver safety control command Download PDFInfo
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- CN103095409B CN103095409B CN201310003817.XA CN201310003817A CN103095409B CN 103095409 B CN103095409 B CN 103095409B CN 201310003817 A CN201310003817 A CN 201310003817A CN 103095409 B CN103095409 B CN 103095409B
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Abstract
The present invention proposes a kind of interpretation method of safety command receiver safety control command, utilizes this method effectively can improve void, the missed command probability of safety control command, realizes highly reliable safety control command and receives.The present invention is achieved by following technical proposals: according to the different time window of the frame format of safety control command definition coupling two length and " 6 sentence 4 " counter in FPGA, and according to total time of safety control command frame format determination two-stage time window of system definition and the N value of N bit shift register; Decoder reads the command code pre-set, and N bit shift register is sent in the numerals sum bit synchronization pulse after demodulation, compares, export a decoding spike when two command codes are consistent after number being become N bit parallel data with prepositioned instruction code; When " 6 sentence 4 " counter accumulated counts is to " 1 ", start short time window (2) simultaneously, when " 6 sentence 4 " counter accumulated counts is to " 4 ", exports a decoding spike, complete the decoding of " 6 sentence 4 " safety control command.
Description
Technical field
The invention belongs to the outer survey field of space flight, is the processing method about carrying out the safety control command after the demodulation of safety command receiver to pacify control decoding.
Background technology
The safety command receiver of present use is developed the nineties in 20th century, there is many problems, such as reliability, according to the feature of this safety command receiver, application FPGA completes the functions such as subcarrier demodulation, Instruction decoding, safety command receiver completes after receiving peace control signal and separates mediation Instruction decoding, can not miss bomb false command.Traditional safety command receiver test system comprises multiple stage special equipment and general purpose instrument, and not only line is complicated, complex operation, and take up room large, the testing time is also long, more easily occurs artificial operate miss and test error.Aircraft carries safety command receiver should have that reliability is high, security performance good, antijamming capability is strong, the feature of real time remote control.Wherein especially important with high reliability, absolutely not allow to occur needing its action and being failure to actuate, do not need the phenomenon of its action misoperation again.If do not adopt highly reliable decoding algorithm in safety command receiver decode procedure, time serious, even mortal injury will be brought to target range, aircraft and personnel.
Summary of the invention
In order to improve the reliability of safety command receiver, reduce void, the missed command probability of safety control command, the invention provides a kind of reliability high, realize simple peace control interpretation method.
Above-mentioned purpose of the present invention can be reached by following measures: a kind of interpretation method of safety command receiver safety control command, is characterized in that comprising the steps:
According to safety command receiver safety control command frame format, define the time window that coupling two length are different in the digital circuit in programmable gate array chip FPGA, N bit shift register and digital comparator are set simultaneously; Two time window timing circuits crosslinked " 6 sentence 4 " counter respectively, and by series connection N bit shift register, digital comparator and common port composition decoder; In peace control decode procedure, FPGA program is first according to the safety control command frame format of safety command receiver definition.Determine the total time of two-stage time window and the N value of N bit shift register; During initial power-up, N bit shift register is sent in numerals sum bit synchronization pulse after the demodulation of decoder front-end circuit, digital comparator is sent into after number being become N parallel-by-bit director data, compare with the number pre-set, when both are consistent, digital comparator exports a decoding spike, and decoding spike is within the time window 1 timing circuit stipulated time, and " 6 sentence 4 " counter carries out instruction count; When " 6 sentence 4 " counter accumulated counts is to " 1 ", time window 2 timing circuit starts timing, and when " 6 sentence 4 " counter accumulated counts is to " 4 ", " 6 sentence 4 " counter exports a decoding spike, complete the decoding of " 6 sentence 4 " safety control command, wherein N is natural number.
The present invention has following beneficial effect compared to prior art:
Greatly reduce void, missed command probability.The interpretation method of " 6 sentence 4 " safety control command that this invention adopts, ingenious at safety control command frame format, define the time window that two length of coupling is different, time window 2 timing circuit (short time window 2) effectively can reduce the false command probability that interference signal or burr signal bring, time window 1 timing circuit (long-time window 1) effectively can identify safety control command, and perform " 6 sentence 4 " decision algorithm, when allowing safety command receiver to occur certain error code, still effectively can receive safety control command and make timely response.Two-stage time window (long-time window 1, short time window 2), long-time window 1 controls the total time of decoding, and short time window 2 controls to occur in decode procedure the response time of burr and reduces the false command probability of peace control decoding.
The present invention is ingenious at increasing two-stage time window, to avoid in decode procedure to the erroneous judgement of interference burr signal certainly, and the simple realization decision algorithm of " 6 sentence 4 ", greatly reduces the void of decoding, missed command probability.
The present invention is realized by programmable gate array FPGA inside, add flexible control and the amendment of the parameter values such as long-time window 1, short time window 2, shift register and the number that pre-sets, when reality uses, can define according to safety control command frame format, any change programmable parameter, the decision algorithm of flexible realization " N sentences M ", ensure that the digital confidentiality requirement pre-set simultaneously.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, invention is further illustrated.
Fig. 1 is safety command receiver FPGA safety control command decoding module circuit theory schematic diagram of the present invention.
Fig. 2 is that Fig. 1 pacifies control decoding FB(flow block).
Embodiment
Consult Fig. 1.In the examples below, the interpretation method of " 6 sentence 4 " safety control command is by the digital circuit of design in programmable gate array chip FPGA.In digital circuit in programmable gate array chip FPGA, the time window different according to safety control command frame format definition coupling two length and " 6 sentence 4 " counter, arrange N bit shift register and digital comparator.Two time windows are crosslinked " 6 sentence 4 " counter respectively, and by the common port composition decoder of series connection N bit shift register, digital comparator and two time windows and " 6 sentence 4 " counter; In peace control decode procedure, FPGA program is first according to the total time of safety control command frame format determination two-stage time window and the N value of N bit shift register of definition, and N is natural number.The total time of determining two-stage time window is the total time of long-time window 1 and the total time of short time window 2, the time of long-time window 1 equals the total time of 6 safety control command frame lengths, the time of short time window 2 is greater than the time of 1 safety control command frame length, is less than the time of 2 safety control command frame lengths.Long-time window 1 controls the total time of decoding, and short time window 2 controls the appearance burr in decode procedure.
N bit shift register is sent in numerals sum bit synchronization pulse after the demodulation of decoder front-end circuit, digital comparator is sent into after number being become N parallel-by-bit director data, compare with the number pre-set, when both are consistent, digital comparator exports a decoding spike, and in long-time window 1, " 6 sentence 4 " counter carries out instruction count to decoding spike; When " 6 sentence 4 " counter accumulated counts is to " 1 ", short time window 2 circuit start timing circuit starts timing, and when " 6 sentence 4 " counter accumulated counts is to " 4 ", " 6 sentence 4 " counter exports a decoding spike, completing the decoding of " 6 sentence 4 " safety control command, is N natural number.
Consult Fig. 2.During initial power-up, decoder reads the number pre-set, and N bit shift register is sent in the numerals sum bit synchronization pulse after demodulation, compare with the number pre-set after number being become N bit parallel data, if both are consistent, export a pulse, in long-time window 1, " 6 sentence 4 " counter carries out instruction count to decoding spike, when " 6 sentence 4 " counter counts is counted to " 1 ", start the timing circuit of short time window 2, when " 6 sentence 4 " counter accumulated counts is to " 4 ", export a decoding spike.If time window 2 does not receive second decoding spike in the timing circuit stipulated time, represent that first decoding spike is disturbing pulse or burr pulse, " 6 sentence 4 " counter is reset, reenters wait state.
In the timing of long-time window 1, when the counting of " 6 sentence 4 " counter is added to " 4 ", complete the realization of " 6 sentence 4 " decision algorithm, export a decoding spike, if do not reach " 4 ", represent that the safety control command received is invalid, " 6 sentence 4 " counter, long-time window 1 and short time window 2 are resetted, reenters wait state.
Above-described is only the preferred embodiments of the present invention.Should be understood that, for the person of ordinary skill of the art, under the premise without departing from the principles of the invention, some distortion and improvement can also be made, such as, as can be seen from description above, when changing the parameter values such as long-time window 1, short time window 2 and shift register figure place, the interpretation method of " N sentences M " safety control command arbitrarily can be realized.These change and change and should be considered as belonging to protection scope of the present invention.
Claims (3)
1. an interpretation method for safety command receiver safety control command, is characterized in that comprising the steps:
According to safety command receiver safety control command frame format, define the time window that coupling two length are different in the digital circuit in programmable gate array chip FPGA, N bit shift register and digital comparator are set simultaneously; N bit shift register connects digital comparator and then connects common port, and be connected with two time window timing circuits and " 6 sentence 4 " counter respectively by common port, two time window timing circuits connect " 6 sentence 4 " counter respectively, composition decoder; In peace control decode procedure, first FPGA program according to the safety control command frame format of safety command receiver definition, determines the total time of two-stage time window and the N value of N bit shift register; During initial power-up, N bit shift register is sent in numerals sum bit synchronization pulse after the demodulation of decoder front-end circuit, digital comparator is sent into after number being become N parallel-by-bit director data, compare with the number pre-set, when both are consistent, digital comparator exports a decoding spike, and when long in time window timing circuit (1) official hour, " 6 sentence 4 " counter carries out instruction count to decoding spike; When " 6 sentence 4 " counter accumulated counts is to " 1 ", short time window timing circuit (2) starts timing circuit and starts timing, when " 6 sentence 4 " counter accumulated counts is to " 4 ", a decoding spike is exported by " 6 sentence 4 " counter, complete the decoding of " 6 sentence 4 " safety control command, if do not receive second decoding spike in window timing circuit (2) stipulated time short time, represent that first decoding spike is disturbing pulse or burr pulse, " 6 sentence 4 " counter is reset, reenter wait state, wherein N is natural number.
2. the interpretation method of safety command receiver safety control command as claimed in claim 1, it is characterized in that, in the timing of long-time window timing circuit (1), when the counting of " 6 sentence 4 " counter is added to " 4 ", complete the realization of " 6 sentence 4 " decision algorithm, export a decoding spike, if do not reach " 4 ", represent that the safety control command received is invalid, " 6 sentence 4 " counter, long-time window timing circuit (1) and short time window timing circuit (2) are resetted, reenters wait state.
3. the interpretation method of safety command receiver safety control command as claimed in claim 1, it is characterized in that, the total time of two-stage time window is the total time of long-time window timing circuit (1) and the total time of short time window timing circuit (2), the time of long-time window timing circuit (1) equals the total time of 6 safety control command frame lengths, the time of short time window timing circuit (2) is greater than the time of 1 safety control command frame length, is less than the time of 2 safety control command frame lengths.
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| CN2741291Y (en) * | 2004-11-25 | 2005-11-16 | 中国电子科技集团公司第五十四研究所 | Security controlling receiver of satellite digital TV-set |
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| CN2741291Y (en) * | 2004-11-25 | 2005-11-16 | 中国电子科技集团公司第五十四研究所 | Security controlling receiver of satellite digital TV-set |
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