CN86206615U - Digital step speed regulating electric fan - Google Patents

Abstract

The utility model discloses a digital electronic step speed regulating electric fan, composed of a motor, a bidirectional thyristor, a digital conversion circuit and a switch network. The electric fan fundamentally solves the high-frequency electromagnetic interference of the electronic stepless speed regulation proceeded by using a thyristor phase shift wave cutting method, and the electric fan capable of being run and accomplished in ultra-low speed through the specific speed regulating method has 16 wind speeds basically and uniformly distributed from zero to the maximum wind speed, at the aspect of simulating the natural wind, the changes of the wind speeds and the time interval can have randomness, the highest and lowest wind speeds can be selected and limited, the electric fan can select 15 classes of simulating the natural wind, the 15 classes are not repeated with each other, the basic types of simulating the natural wind have 2211840 kinds, and the basic types of simulating the natural wind can reach more than tens of thousands when the kinds are changed.

Description

Digital step speed regulating electric fan

The utility model belongs to a kind of household electric appliance.

General electric fan carries out step speed regulation with reactance method, tapping method, auto-transformer method etc.; Its shortcoming be progression very little, 3-5 level only, and be difficult to take into account the Ultra-Low Speed operation of the following classification of 40% rated power.In recent years carry out electronic stepless speed regulation with controllable silicon phase-shifting chopped waves method; Its shortcoming is the serious distortion of voltage waveform and become the electrical network public hazards and disturb with high-frequency electromagnetic; In addition because the time lag that the electric fan electromechanical properties causes when between phase shift phase angle and wind speed being complicated non-linear relation and speed governing makes this advantage of stepless speed regulation generally can only closed loop use, and electric fan designs by open system.Therefore according to the feedback principle of controlling automatically, just can obtain suitable wind speed for revising repeatedly several times traditionally by the general user that the pure linear mode of open loop is regulated, this phenomenon is particularly evident at the speed adjustable range two ends.

People wish the equal tool randomness of variation in its wind speed, the time lag aspect natural wind simulating; But not the sort of randomness of real natural wind, because it not necessarily closes symbol people's needs; People are having different strong and weak requirements with electric fan simultaneously, therefore wish to select the different natural wind simulating of randomness type.Wish in addition its high wind speed and minimum wind speed also can be selected and be limited.The scope of Xuan Zeing is also bigger in addition, and the electric fan with microcomputerized control in the prior art has the natural wind simulating function, better performances, but the natural wind simulating kind that can select and limit is seldom; Its cost is also higher.

The purpose of this utility model provides a kind of digital electronic step speed-controlled electric fan; Can realize the no-voltage wave distortion, thereby fundamentally solve the source that high-frequency electromagnetic disturbs; There is abundant linear discrete to regulate progression for digital open loop speed governing.It also can make digital setting compensation to improve performance when starting and Ultra-Low Speed operation.

Aspect natural wind simulating, the variation in wind speed, the time lag all can be had randomness; High wind speed and minimum wind speed can be selected and limit, and selectable natural wind simulating kind.Simultaneously can for the kind that natural wind simulating provides will be greatly more than existing electric fan.

Principle of the present utility model is that the rotating speed of electric fan and the electric power of input are linear approximate relationships, and therefore the electric power of restriction input can realize speed governing, is similar to chopper speed control.Method is that the ratio of sinusoidal wave total number of sinusoidal wave number and the burst of conducting in the burst is input electric power and the ratio that can import maximum electric power, is similar to speed ratio.The content of the technical program is that the bidirectional triode thyristor of control motor is zero to trigger and positive-negative half-cycle is complete and conducting and be controlled by digital conversion circuit in couples; This circuit decision controllable silicon allows L minimum working cell conducting in an operation cycle.Wherein: the operation cycle is made up of M minimum working cell, and minimum working cell is made up of the individual complete sine wave of N '; L is provided with the N bit; N, N ', M, L are positive integer.The phase angle that the The Trigger of Bidirectional Triode Thyristor pulse of motor is promptly controlled in zero triggering is zero degree basically, as the clock of digital conversion circuit, the trigger impulse of digital conversion circuit output allows signal just to guarantee that bidirectional triode thyristor is zero triggering and positive-negative half-cycle is complete and conducting in couples to the clock that is positioned at the zero phase angle by the pulse edge of electrical network zero cross detection circuit output like this behind 2 * N ' frequency division.Digital conversion circuit mainly is made up of counter and decoding circuit, and allows signal that two kinds of waveforms are arranged with the trigger impulse of different its outputs of circuit; The continuous conducting of the individual sine wave of a kind of L of being * N ' promptly in the operation cycle trigger impulse allow signal only to change once, another kind be the individual sine wave of L * N ' dispersedly conducting promptly in the operation cycle trigger impulse allow signal to change L time.

Can must to the high position of L, an inferior high position effective level compensation be set by electric delay circuit with one in order when starting, to improve performance.Can make selectable ripple compensation to some position of L with a frequency, square-wave generator that dutycycle is all adjustable in order when Ultra-Low Speed moves, to improve performance.

In order all can to have randomness in the variation that obtains wind speed, the time lag aspect the natural wind simulating; High wind speed and minimum wind speed can be selected and limit, the considerable effect of selectable natural wind simulating kind, an available numeral set to select that network (switch selection network) makes L each all can between the N position output terminal of a randomizer and high-low level, select.Randomizer makes the variation in wind speed, the time lag all can have randomness like this; The high wind speed and the minimum wind speed that add the combine analog natural wind of high-low level just can be selected and be limited.The numerical value of randomizer can change by the quasi random number generator Changing Pattern; The time lag of its variation is that the pulsewidth between the effective edge of clock can change by another quasi random number generator numerical values recited Changing Pattern, and this quasi random number generator clock is from the output of the square-wave generator of a frequency adjustable.In order more to be changed, the N position output terminal of quasi random number generator all can have anti-phase output.Switch is selected network each can be had eight kinds of selections like this, and the array output coding of its N position is just very considerable.Two mutual contrapositions of quasi-random sequence of number were determined and were determined the type of natural wind simulating when pressing the variation of quasi random number generator Changing Pattern by the start stochastic regime numerical value of randomizer and the time lag of variation thereof.In order to select natural wind simulating, be between time lag of the numerical value of randomizer and variation thereof that contraposition can add manual transfer mutually, promptly the clock end at the quasi random number generator that determines randomizer numerical value adds an individual pulse generator, and when the manual transfer of randomizer, add suggestion device, as the output state of diode displaying quasi random number generator.In order to obtain further randomness, controllable silicon is triggered allow signal to do with anti-phase output by turns by certain rule.As with a T trigger and control a same reversed phase converter that is made of and gate and the clock two divided-frequency that makes quasi random number generator gets final product, the length of quasi-random sequence of number doubles like this.Be controlled by the square-wave generator that a same reversed phase converter that the counter or the and gate of clock division are constituted is controlled by a frequency, EDM Generator of Adjustable Duty Ratio as the T trigger, then the length of quasi-random sequence of number will increase more than ten times.

Advantage compared with prior art of the present utility model be fundamentally to have solved with controllable silicon phase-shifting chopped waves method carry out the serious distortion of voltage waveform of electronic stepless speed regulation and become the electrical network public hazards and with high-frequency electromagnetic disturb thereby no-voltage wave distortion; Distinctive speed regulating method not only makes the Ultra-Low Speed operation of the following classification of 40% rated power feasible, and available abundant linear discrete is regulated the custom that progression has satisfied the general user who regulates by the pure linear mode of open loop.Embodiment has provided the electric fan of a kind of N=4, has from 0 to 16 kinds of uniform substantially wind speed of maximum wind speed.Except that the electric fan of microcomputerized control, do not consider optimum start in the prior art, and the utility model just can be realized with simple circuit.But when Ultra-Low Speed moves frequency of superposition, dutycycle is all adjustable, the selectable fluctuating wind of wind speed size, only this function has been better than the natural wind simulating of general electric fan.

Electric fan with microcomputerized control in the prior art has the natural wind simulating function, but selectable natural wind simulating kind seldom; Its cost is also high.The utility model is aspect natural wind simulating, and the variation in wind speed, the time lag all can be had randomness; Outstanding advantage is that high wind speed and minimum wind speed can be selected and limit, and can select the kind of natural wind simulating.Embodiment has provided the electric fan of a kind of N=4, has from 0 to 16 kinds of uniform substantially wind speed of maximum wind speed, and aspect natural wind simulating, the variation in wind speed, the time lag all can be had randomness; High wind speed and minimum wind speed can be selected and limit, and can select 15 kinds of big classes of natural wind simulating.It does not repeat basic natural wind simulating type mutually 2211840 kinds, adds that changing its kind can reach more than ten million.

The utility model is described in further detail by accompanying drawing embodiment, parameter: N=4, and N '=1, M=15, digital circuit is example with CMOS.

Fig. 1: motor, controllable silicon and controlled trigger circuit thereof, DC electrical source and electrical network zero cross detection circuit, Fig. 2,3,4: three kinds of digital conversion circuits, Fig. 5: oscillogram, Fig. 6: STCP starting compensatory circuit, Fig. 7: the pulsed compensating circuit of Ultra-Low Speed, Fig. 8: quasi random number generator, Fig. 9: switch is selected network, Figure 10: randomizer, Figure 11: period multiplication circuit.

Fig. 1: D is motor; KP is controllable silicon; L₂、D _1－4、C ₁、R ₁、R ₂, GD forms circuits for triggering. GD-multiple tube output photoelectric coupler (Darlington type), GD had Voltage-output to remove to trigger controllable silicon when the T signal was high level, current-limiting resistance R₁By current limliting 30mA design, R₂＝1K，L ₂、D _1－4、C ₁Form the simplest dc source design parameter: V_＋Between 5-10V, load current 0.05A. L₃、D _5－10、C _2－3、R _3－5, BG consists of dc source and the electrical network zero cross detection circuit of digital circuit power supply. L₃、D _5－9、C ₂、R ₃, the dc source that consists of digital circuit power supply designs parameter routinely: V_DDValue between 5-15V, load current 0.08A. D₁₀、R _4－5、C ₃, BG forms electrical network zero cross detection circuit, D₁₀Pulsating direct current is separated R₄、C ₃Be sampling, filtering, phase-shift circuit, transistor BG is ended in zero crossing, the RC time constant is less than 1ms, R₄Double as BG base stage current-limiting resistance and R₅The saturation current of BG is got final product, the clock of f end output 100Hz less than 3mA. Transformer BT is 2VA, fuse RD, K switch₁Routinely design.

Fig. 2: IC₁、IC ₂Be and can preset the 1/N frequency divider, D, C, B, A are that tetrad is put the number end, and CP is the clock end, makes clock by the f from the electrical network zero cross detection circuit behind T trigger two divided-frequency, puts number and allows end P_EDuring high level D, C, B, A are inserted frequency divider, do to subtract a computing by the CP pulse, and complete zero the time by all-zero signal output O_CHigh level pulse of end output. IC₂The work period length M is done to subtract a computing, and D, C, B, A are high level, its O when each work period finishes_CHigh level pulse of end output makes IC₁、IC ₂Put simultaneously number, and the T trigger is overturn, and its Q end sets high level and output allows signal T as the trigger impulse that makes controlled silicon conducting. IC₁D, C, B, A end link with the switch that tetrad L is set, at IC₂O_CL inserts IC under the impulse action₁Work subtracts a computing, its O_CEnd output pulse makes the upset of T trigger set low level. IC₁、IC ₂O_CEnd through one or gate action in the clock end of T trigger. Its controllable silicon work wave is that the continuous conducting of the individual sine wave of L * N ' is to allow signal only to change once in the work period, and the waveform of digital circuit output T signal sees that Fig. 5 illustrates.

Fig. 3: IC₃Be the tetrad counter; Clock and Fig. 2 are together; The tetrad of its output is sent into tetrad comparator IC₄B₁、B ₂、B ₃、B ₄End, IC₄With its with send into A₁、A ₂、A ₃、A ₄Tetrad L relatively, the result is at OUT(A＞B) and OUT(A=B) end through or door output. IN(A＞B) and IN(A=B) be high level; IN(A＜B) is low level; OUT(A when A＞B＞B) is high level, OUT(A=B during A=B) be high level, two ends are low level during A＜B. Or door is output as silicon controlled and touches Send out pulse and allow signal T, waveform and Fig. 2 are together.

Fig. 4: IC₅Be the tetrad counter; Its clock and Fig. 2 are together; D, C, B, A and the switch that tetrad L is set link to each other its decoding circuit logical formula:

T′＝A· Q _d·Q _b·Q _a+B· Q _c·Q _b·Q _a+C· Q _b·Q _a+D· Q _a+ CP

J is monostable flipflop, and it becomes T signal, pulsewidth＞13ms,＜20ms with T ' broadening. R, C decides by selected monostable flipflop. The waveform of Fig. 4 digital conversion circuit is different from Fig. 2; The trigger impulse of exporting in a work period allows signal T to change L time, and L individual pulse namely arranged in M, and Fig. 2 then is that the pulsewidth of triggering permission signal T is L. The controllable silicon waveform of Fig. 4 is the dispersedly conducting of the individual sine wave of L * N '.

Fig. 5: three kinds of digital conversion circuit oscillograms; If L=5, A=1 then, B=0, C=1, D=0; The frequency of CP is 50Hz; T₁、T ₂Be respectively Fig. 1, Fig. 2 and allow the waveform of signal T; T₃Waveform for Fig. 4 T '; Can find out the difference of two kinds of waveforms, T with regard to motor characteristic₃Waveform better.

Fig. 6: STCP starting compensatory circuit; Use to such an extent that the monostable flipflop that triggers of electrical pulse constitutes by one, pulsewidth＞5 second;＜20 seconds, utilize the high input impedance of CMOS or door can conveniently make derivative-type monostable circuit, R ₆=500K; C ₄=220 microfarads.Or another input termination tetrad L of door switch, the high position of its output termination digital conversion circuit output terminal be set.

Fig. 7: the pulsed compensating circuit of Ultra-Low Speed; A ultra-low frequency frequency, the square-wave generator that dutycycle is all adjustable utilizes the d type flip flop of CMOS to constitute, when the Q of d type flip flop end during for high level through current-limiting resistance R ₇(300K), potentiometer W ₁(1M) to C ₅Charging constitutes integration circuit.D type flip flop Q end is low level, C when the R of d type flip flop end reaches the upset level ₅On voltage through the diode D that releases ₁₁Discharge; At this moment R ₈, W ₂, C ₆, D ₁₂Branch road is held integration to S, principle, parameter and R ₇Branch road together.W ₁, W ₂Be used for the frequency modulation rate, dutycycle, its cycle is from several seconds to tens seconds, CP ₁For the output pulse can through or door some position of connecing digital conversion circuit make ripple compensation.

Fig. 8: quasi random number generator; Form ring register by four d type flip flops, but its first input provided behind and gate by two at end.Along with the input of CP, it is the quasi-random sequence of number of 15 numbers that the D of quasi random number generator, C, B, A send a Cycle Length of forming with tetrad; Its 16 system form is F, 7,3,1,8,4,2,9, C, 6, B, 5, A, D, E.

Fig. 9: switch is selected network; D, C, B, A are from the output terminal of quasi random number generator; K ₁, K ₂, K ₃, K ₄Be anti-phase control end, and gate is with the anti-phase output of D, C, B, A of correspondence when closing, and four current-limiting resistance R are 100K.K ₅, K ₆, K ₇, K ₈Be selector switch, when doing the selection of conllinear not in it is having D, C, B, the A of anti-phase output, switch selects output D ', C ', B ', the A ' of network to have 384 kinds of mutually different quasi-random sequence of number; When being chosen in V _DDThe time quasi random number lower limit be defined, the upper limit is defined when ground connection; Limit value is determined by 8421 yards.LED, BG ₁, R ₉, R ₁₀, be that general LED display circuit is made prompting usefulness, each connects one the tunnel, by the universal law design.

Figure 10: randomizer; ［ 1 ］, ［ 2 ］ are the quasi random number generator of Fig. 8; ［ 3 ］, ［ 4 ］ are the switch selection network of Fig. 9; IC ₆With IC ₁With.Output D, the C of this circuit, B, A do the input of digital change-over circuit.IC ₆Clock CP with the CP of the square-wave generator of Fig. 7 ₁, can save a branch road; The output of quasi random number generator ［ 1 ］ is selected to send into IC behind the network ［ 3 ］ through switch ₆D, C, B, A; IC ₆O _CExport a pulsewidth and press the pulse sequence that switch is selected the quasi random number numerical value change of network ［ 3 ］ output, as the clock CP of quasi random number generator ［ 1 ］, ［ 2 ］; The time lag of the numerical value of randomizer and variation thereof all can change by the quasi random number generator Changing Pattern like this.Because respectively there are 384 kinds of quasi-random sequence of number ［ 1 ］, ［ 2 ］, each sequence length is 15 numbers, and the stochastic regime during along with start makes ［ 1 ］ and ［ 2 ］ have 15 kinds of combinations at random; Therefore total mutual unduplicated fundamental type 384 * 384 * 15=2211840 kind adds to derive to change its kind at least more than ten million.K ₉, current-limiting resistance R(100K) or door form the manual transfer circuit, promptly the additional hours clock makes 15 kinds of combined optionals of ［ 1 ］ and ［ 2 ］.

Figure 11: period multiplication circuit; Make the clock of quasi random number generator after with the clock two divided-frequency with a T trigger; Control a same reversed-phase control circuit that constitutes by and gate simultaneously, another input termination T signal of and gate.T signal inversion during T trigger output high level.

Embodiment one: basic model; Add that by Fig. 1 Fig. 2,3, one of 4 is provided with switch (16 scale coding switch) with tetrad L and forms.Have that open loop sets from 0 to 16 kinds of uniform wind speed of maximum wind speed, do not have natural wind at random.

Embodiment two: basic model adds Fig. 6, Fig. 7.Increase STCP starting compensatory, the pulsed compensation of Ultra-Low Speed; But when Ultra-Low Speed moves frequency of superposition, dutycycle is all adjustable, the selectable fluctuating wind of wind speed size, only this function has been better than the natural wind simulating of general electric fan.

Embodiment three: basic model adds Fig. 6, Fig. 7, Figure 10; Aspect natural wind simulating, the variation in wind speed, the time lag all can be had randomness; High wind speed and minimum wind speed can be selected and limit, and can select 15 kinds of big classes of natural wind simulating.It does not repeat basic natural wind simulating type mutually 2211840 kinds, adds that changing its kind can reach more than ten million.

Embodiment four: basic model adds Fig. 6, Fig. 7, Figure 10, Figure 11; The wind type changes the natural wind at random of 1105920 kinds of basic models (30 number one-period) into.Change the T trigger into as Figure 11 and be controlled by a counter clock division; IC as Fig. 2 ₁Perhaps the same reversed phase converter of and gate formation is controlled by the square-wave generator of a frequency, EDM Generator of Adjustable Duty Ratio, and then the length of quasi-random sequence of number will increase more than ten times.

Claims (7)

1, a kind of digital electronic step speed-controlled electric fan, by motor, bidirectional triode thyristor, transformer, digital circuit counter and gate circuit, the electrical network zero cross detection circuit, the binary system configuration switch is formed, its feature is the clock of the pulse of mains frequency integral multiple as digital conversion circuit behind frequency division one of electrical network zero cross detection circuit output, counter and decoding are formed a digital conversion circuit with gate circuit, counter is to clock count, decoding circuit is provided with count status and binary system configuration switch whether several trigger impulses of relatively exporting with the decision digital conversion circuit are Actual level, and bidirectional triode thyristor is from the zero phase conducting when it is Actual level.

2, according to the described electric fan of claim 1, it is characterized in that the binary system configuration switch is that a switch is selected network, the N+2 end of being thrown switch by the N position output terminal of a high-low level and a quasi random number generator and the individual hilted broadsword N+2 of N ' links, and the hilted broadsword end is that the binary number of output terminal and digital conversion circuit is provided with to hold and links.

3, according to the described electric fan of claim 2, it is characterized in that the N position output terminal of quasi random number generator all can add a controlled same reversed phase converter, can anti-phasely export.

4,, it is characterized in that quasi random number generator can have just anti-phase output according to the described electric fan of claim 2.

5,, it is characterized in that the time lag of the clock variation of quasi random number generator changes by another quasi random number generator Changing Pattern according to the described electric fan of claim 2.

6, according to the described electric fan of claim 1, it is characterized in that starting and can the high level pulse compensation be set to the high position that the digital conversion circuit binary number is provided with end during the Ultra-Low Speed operation temporarily, wherein its frequency, dutycycle are all adjustable for pulsation Ultra-Low Speed when operation, by or the couplet on the door connect.

7, state electric fan according to claim 2,3,4,5, it is characterized in that controllable silicon triggers the permission signal and can do just anti-phase output by the parity of quasi random number periodicity, promptly control positive reversed phase converter to the output conversion by a T trigger.

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