CN85201034U

CN85201034U - Synchro control high-speed sampling apparatus

Info

Publication number: CN85201034U
Application number: CN 85201034
Authority: CN
Inventors: 解明
Original assignee: NANJING POLYTECHNICAL COLLEGE
Current assignee: NANJING POLYTECHNICAL COLLEGE
Priority date: 1985-04-01
Filing date: 1985-04-01
Publication date: 1986-03-26

Abstract

The utility model relates to a synchro control high-speed sampling apparatus, belonging to an ultrasound lossless detection device. The utility model uses digital devices, and through definite numbers combination completes the synthesis to the phi-[0] non-integral frequency in an internal clock of a computer, the synthesized frequency is used as the externally synchronously controlled cycle to generate a micro time difference with the A/D conversion cycle in the computer, and the sampling technology is used to complete the quantized works to the high-speed ultrasound signal using an ordinary A/D converter.

Description

Synchro control high-speed sampling apparatus

The present invention is used for ultrasonic non destructive detection equipment.Because the frequency height of ultrasonic signal, quantizing ultrasonic signal adopts the high speed A device usually or uses sampling oscilloscope with ultrasonic signal broadening in sampling oscilloscope, and then use common A/D converter that ultrasonic signal is quantized, the system cost that above-mentioned quantification technique constituted is all too high.The present invention utilizes common A/D converter (50 μ S) that ultrasonic signal is quantized, and realizes the high-speed sampling conversion.

Key problem in technology of the present invention is how to produce the sample period signal, the outer synchronous control signal of ultra-sonic defect detector, but also to make sample period and outer synchronizing cycle of synchronised.Because the sample period of A/D converter can be by the assembly instruction control of computing machine.And the assembly instruction execution is the clock φ according to computer-internal ₀Can accurately calculate needed clock sum of A/D converter sample period like this.And time length that should the cycle can require and be greater than the A/D converter quantization time as long as its condition meets the outer synchro control cycling of ultra-sonic defect detector by peopleware's arbitrary decision.By above work, just can determine the time of sample period, how to produce the outer synchro control cycle of ultra-sonic defect detector, synchro control high speed sampling instrument is to use computer-internal clock φ here ₀By certain frequency synthesis, make to produce a small mistiming in time as the outer synchro control cycle of ultra-sonic defect detector and the sample period of A/D converter after the frequency synthesis, just can reach the effect that stepping or step move back, finish quantification ultrasonic signal.

Because frequency synthesis technique complexity, high to the circuit design requirement is difficult to realize with general device.But digital device (using 74 serial TTL circuit in this instrument) can constitute the frequency division and two frequency multiplier circuits of non-decimal easily, by combination of them, just can finish computer-internal clock φ ₀Frequency synthesis.For example the sample period of mould/number conversion is 200 φ ₀(establish φ ₀Be 1 μ S), so, as long as make the outer synchro control cycle of the ultra-sonic defect detector after the frequency synthesis accomplish 199.96875 φ ₀, △ t=200 * φ like this ₀-199.96875 * φ ₀=1/32 * φ ₀Owing to established φ ₀Be 1 μ S, sampling rate is exactly 32MHZ.Realize 199.96875 φ ₀Step be: to computer-internal clock φ ₀Carry out 32(2 ⁵) frequency multiplication and 6399 frequency divisions just can reach above requirement.Synthetic result like this is to φ ₀Not not its integral multiple just.Perhaps use an oscillation source that is higher than computer-internal clock frequency several times,, obtain the internal clocking φ of the desired frequency of computer-internal clock frequency at last as computing machine with its frequency division one by one ₀Again to oscillation source one by one the result that obtains of frequency division carry out frequency division, so also can reach the purpose of frequency synthesis with digital technology.Use second method, in total system, all be to use frequency dividing circuit.Can be for divider ratio by the mode of components and parts realization and the synchronizing frequency requirement design of ultra-sonic defect detector.Combination of frequency can be formed frequency dividing circuit by counting devices such as varactor doubler and multi-disc 74LS90,74LS92,74LS93.For example 1755 divider ratios can be decomposed into 15 * 13 * 9 times the attainable divider ratio of monolithic.

Because the reference source in the sample period of computing machine and the outer synchro control cycle of ultra-sonic defect detector all comes from the internal clocking φ of computing machine ₀, they are not subjected to strict synchronism the interference of other factors, and sampling process is stable.By starting point, terminating point and number of sampling to all right arbitrary decision sampling of the modification of software.

The synchro control high speed sampling instrument cost that uses this technology to constitute is low, easy to use, flexible, the components and parts consumption is few, as long as do suitable change on the line, just can produce various sampling rates.Can directly constitute computerized ultrasonic fault detection system and other with it and require computed supersonic sounding system.

It is as follows to provide inventive embodiment below in conjunction with accompanying drawing:

Fig. 1 is to computer-internal clock φ ₀Carry out the block diagram of frequency synthesis.

Fig. 2 utilizes outer oscillation source to produce the block diagram of synchronous control signal and computer-internal clock signal.

An embodiment as shown in Figure 1 is with computer clock φ ₀Be connected on the input end of varactor doubler, its output terminal continues to be connected on the input end of second varactor doubler, analogizes therewith, till satisfying its sampling rate requirement.On each time two frequency multiplication output terminals and first two frequencys multiplication input end, signal can be carried out frequency division according to the specific requirement of sampling rate, to reach the requirement of synchro control.Frequency multiplier output terminal in each time can connect frequency dividing circuit according to specific requirement, also can not connect frequency dividing circuit, and the port that does not have synchro control frequency output not connecing frequency dividing circuit is this sampling rate not just.

An embodiment as shown in Figure 2 is to use one to be higher than computer clock φ ₀The oscillation source of several times, the some grades of frequency dividing circuits of output access for oscillation source make it end to end, and it is to make its last output satisfy computer clock φ that its frequency division requires ₀Requirement as the clock of this computing machine, can insert suitable frequency dividing circuit to the output terminal of oscillation source frequency division and the output terminal of oscillation source itself one by one, can export all at every turn and connect, also can insert frequency dividing circuit at concrete output terminal and carry out suitable frequency division, to reach the frequency requirement of synchro control according to the requirement of sampling rate.

Two frequency multiplier circuits that embodiment shown in Figure 3 is to use digital device, resistance, electric capacity to form.

1755 frequency divisions that embodiment shown in Figure 4 is to use digital device to form, its array mode is 15 * 13 * 9.

After using secondary two frequencys multiplication and one time 1755 times frequency divisions, as long as A/D software is adjusted to 439 * φ ₀Can realize 4MHZ(φ ₀=1 μ S) sampling rate.

By matching with the execution of A/D software again with Fig. 3 synchro control frequency that the embodiment circuit constituted shown in Figure 4 among Fig. 1 or two kinds of embodiment of Fig. 2 and constituting synchro control high speed sampling instrument.

Claims

1, a kind of synchro control high speed sampling instrument is characterized in that being formed or being made up of oscillator [4], computing machine [1], frequency dividing circuit [3] by computing machine [1], varactor doubler [2], frequency dividing circuit [3], becomes to be electrically connected between them.

2,, it is characterized in that computing machine (1) clock φ according to the described high speed sampling instrument of claim 1 ₀Be connected on the input end of varactor doubler (2), its output terminal continues to be connected on the input end of second varactor doubler, by that analogy, till satisfying its sampling rate requirement, on each time two frequency multiplication output terminals and first two frequencys multiplication input end, signal can be carried out frequency division according to the specific requirement of sampling rate, frequency multiplier output terminal in each time can connect frequency dividing circuit according to specific requirement.

3, according to the described high speed sampling instrument of claim 1, it is characterized in that being higher than computer clock φ with one ₀The oscillation source of several times (4), the output terminal access some grades of frequency dividing circuits (3) at oscillation source (4) make it end to end, and it is to make last output satisfy computer clock φ that its frequency division requires ₀Requirement, can require to insert frequency dividing circuit according to sampling rate at the output terminal to the output terminal of oscillation source (4) frequency division and oscillation source itself one by one.