CN85105124A - Transistor - Google Patents
Transistor Download PDFInfo
- Publication number
- CN85105124A CN85105124A CN85105124.3A CN85105124A CN85105124A CN 85105124 A CN85105124 A CN 85105124A CN 85105124 A CN85105124 A CN 85105124A CN 85105124 A CN85105124 A CN 85105124A
- Authority
- CN
- China
- Prior art keywords
- electrode
- emitter
- base
- mentioned
- emitter electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The invention provides and a kind ofly have the 1st emitter electrode that contacts in the mesh emitter district and the 1st base stage that contacts in island base stage contact zone and be arranged on above the interlayer dielectric respectively the 2nd emitter electrode and the 2nd base electrode that connects with the 1st above-mentioned emitter electrode and the 1st base stage, above-mentioned the 2nd emitter electrode and above-mentioned the 2nd base electrode form the broach shape, make above-mentioned the 2nd emitter electrode and above-mentioned the 1st emitter electrode on each broach, carry out banded contacting, suppress concentrating of electric current by enlarging contact area significantly, little chip area and the transistor of the high current capacity of stronger anti-destructive power is arranged.
Description
Technical field
The invention relates to transistor, particularly about transistorized improvement through too high current capacityization.
Prior art
From the structure that is used as increasing transistorized allowable current all is the way that adopts the effective area that enlarges emitter, and this is well-known.Cause as this netted base stage structure and the island emitter that is configured with as shown in Figure 5.Among Fig. 5, the collector area that (1) is made up of Semiconductor substrate; (2) be the base region; (3) be the island emitter region; (4) that dot are the base electrodes that (2) carry out the resistance contact in the base region; (5) be at each island emitter region (3) ... (3) carry out the emission electrode that resistance contacts.
In above-mentioned structure, by the island emitter region (3) of majority ... (3) can enlarge girth that the base stage utmost point engages so that the purpose that can easily reach high current capacityization., can clearly learn, in island emitter region (3) from Fig. 5 ... (3) increase of area the time, the area of netted base region (2) is also along with increase, thereby also just causes the increase of chip area., in base stage because can only be by the 1/h of collector current
FEElectric current.So the increase of base stage (2) can not played any effect to transistorized high current capacityization basically.
Thereby just consider to adopt the transistor of mesh emitter structure as shown in Figure 6.The collector area that (10) among Fig. 6 are made up of Semiconductor substrate; (11) be the base region, (12) are netted emitter regions; (13) that dot are the emitter electrodes that carries out the resistance contact at emitter region (12); (14) be the base electrode that carries out the resistance contact in the base region that is distributing (11).
In above-mentioned structure, because can only enlarge the area of emitter, so quite effective to the increase that prevents chip area by mesh emitter district (12).Yet can clearly learn from Fig. 6, because emitter electrode (13) forms the broach shape with base electrode (14), so emitter electrode (13) can only carry out the resistance contact at the only about half of area of netted utmost point emitter region (12), thereby emitter (12) though area can obtain enlarging, the area of emitter electrode (13) just can't enlarge.So mesh emitter district (12) just can not obtain utilizing fully, and mesh emitter district (12) also just can't play one's part to the full aspect the expansion current capacity as a result.
, further repeatedly improve for this reason, considered a kind of transistor as the mesh emitter with multi-layered electrode structure of Fig. 7 (a) shown in (b).This transistor has collector area (20), base region (21 of being made up of silicon semiconductor substrate) and mesh emitter district (22), the almost all surfaces of (21) has all disposed emitter region (22) in the base region, the contact zone (23) of base region (21) ... (23) then in most islands emitter region (22), dispose with the state that is launched polar region (22) encirclement fully.Silicon oxide film (24) top on substrate (20) surface, the 1st base electrode (25) of the ground floor that formation dots and the 1st emitter electrode (26), the 1st base electrode (25) is each contact zone (23) of in the base region (21) ... (23) carry out the resistance contact, become most islands; The 1st emission electrode (26) is to carry out resistance with the almost all surfaces of emitter region (22) to contact and form netted.The 1st base electrode (25) and the 1st emitter electrode (26) are covered with by interlayer dielectrics such as polyimides (27).On interlayer dielectric (27), the 2nd layer the 2nd base electrode (28) and the 2nd emission electrode (29) represented with pecked line have been formed.The 2nd base electrode (28) is respectively at the 1st base electrode (25) of the majority that distributes with island ... (25) carry out resistance contact, form the broach shape and extend towards a direction.The 2nd emission electrode (29) is that the peripheral part at netted the 1st emission electrode of representing with oblique line (26) carries out the resistance contact, and extends to pad.
According to above structure, because almost can dispose the 1st emitter electrode (26) all in mesh emitter district (22), thus can make mesh emitter district (22) carry out work expeditiously, thus current capacity enlarged., when adopting the multi-layered electrode structure, blocked up if the thickness of the 1st emission electrode forms, the stage difference of the 1st layer of electrode will become greatly, so that has influence on the 2nd layer formation.Therefore, the thickness of the 1st emission electrode (26) can not be blocked up, and big electric current one passes through, and just has the shortcoming that is damaged owing to current concentration in the contact portion with the 2nd emission electrode (29) of the peripheral part of being located at the 1st emission electrode (26).
In view of above-mentioned shortcoming, the present invention is by making the 2nd emission electrode (29) not only can be at the 1st emission electrode (26) and peripheral part, and also the way that can contact in inside comes original shortcoming is significantly improved.
Handle of the present invention contacts with the resistance of the 1st emission electrode (26) of the 2nd emission electrode (29) and can be provided with numerously so that electric current disperses with banded state, thereby prevents because the caused destruction of current concentration.
The simple declaration of accompanying drawing
Fig. 1 (a) is that vertical view, Fig. 1 (b) of the transistorized Semiconductor substrate of explanation is the profile along the I of Fig. 1 (a)-I line; Fig. 2 (a) illustrates that Fig. 2 (b) is the profile along the II of Fig. 2 (a)-II line according to transistorized vertical view to the 1st layer of electrode of the present invention; Fig. 3 (a) is an explanation transistorized vertical view of the present invention; Fig. 3 (b) is the profile along the III of Fig. 3 (a)-III line; Fig. 4 (a) is the sectional view of expression transistorized manufacture method of the present invention to Fig. 4 (f); Fig. 5 is the transistorized vertical view of the original netted base stage structure of explanation; Fig. 6 illustrates the transistorized vertical view of original mesh emitter structure; Fig. 7 (a) is the transistorized vertical view of the mesh emitter structure after explanation further improves original work; Fig. 7 (b) is the profile along Fig. 7 (a) IV-IV line; Fig. 8 is original and performance plot safety operation area of the present invention of explanation.
Embodiment
Fig. 1 (a) (b) (b) represents the transistor configurations of the present invention's mesh emitter structure to Fig. 3 (a).Also have, the numbering among the figure is (b) general with Fig. 7 (a).
The present invention's transistor as Fig. 1 (a) (b) shown in, have collector area ⒇, base region (21) and mesh emitter district (22) formed by silicon semiconductor substrate, emitter region (22) is disposed at the almost all surfaces of base region, the contact zone (23) of base region (21) ... (23) be in emitter region (22), to form many islands, and be launched polar region (22) fully and surround and disposing.Also have, as Fig. 2 (a) (b) shown in, useful thick line is represented formed the 1st layer the 1st base electrode (25) and the 1st emitter electrode (26) on the silicon oxide film (24) on substrate ⒇ surface, the 1st base electrode (25) is each contact zone (23) of in the base region (21) ... (23) carry out resistance contact and form many islands, the 1st emitter electrode (26) then is to carry out resistance with the almost all surfaces of emitter region (22) contact formation netted.And then as Fig. 3 (a) (b) shown in, the 1st base electrode (25) and the 1st emitter electrode (26) are covered by the interlayer dielectric (27) of polyimides etc., then are formed with the 2nd layer the 2nd base stage (28) and the 2nd emitter electrode (29) represented with thick line on interlayer dielectric (27).The 2nd base electrode (28) be respectively with many 1st base electrodes (25) that distributing with island ... (25) carry out resistance contact, form the broach shape and stretch to a direction.Also have, the part of above-mentioned the 2nd base electrode (28) also can form the pad district.
Feature of the present invention is the shape that is the 2nd emitter electrode (29).The 2nd emitter utmost point electrode (29) and the 1st emitter electrode (26) are as with being to carry out banded resistance contact between the 2nd base electrode (28) that stretches with the broach shape shown in the oblique line.In addition, as Fig. 3 (a) (b) shown in, between the broach shape between above-mentioned the 2nd base electrode, also can distinguish separately and to be provided with.The 2nd emitter electrode (29) is to be staggered in and to form the broach shape and extend to pad with the 2nd base stage (28).This 2nd emitter electrode (29) and original comparing can enlarge the contact area with the 1st emitter electrode (26) significantly, thereby can disperse the electric current of the 1st emitter electrode (26) and export to the 2nd emitter electrode (29).The result can suppress the current concentration of the 2nd emitter electrode (29), becomes the very strong structure of anti-destructiveness.
Below use Fig. 4 (a) to Fig. 4 (f) expression transistorized manufacture method of the present invention.
At first, shown in Fig. 4 (a), prepare the silicon semiconductor substrate ⒇ of a conductivity type, and use formation silicon oxide films such as thermal oxidation method on the surface of above-mentioned silicon semiconductor substrate ⒇.
And then shown in Fig. 4 (b), adopt etching method on above-mentioned silicon chloride film, to open the base diffusion hole, diffuse to form the base region (21) of opposite conduction type.
Then as Fig. 4 (c) shown in, make it to form the emitter region (22) of a conductivity type in lining, aforementioned base district (21) use diffusion method etc.Here the emitter region of indication (22) is to form netted shown in Fig. 1 (a), and most surface is being configured in the base region.
Below shown in Fig. 4 (d), form contact in aforementioned base district (21) and above the emitter region (22).Here, the contact zone (23) of base region (21) ... (23) be to be formed on the inside of emitter region (22) with many islands, and be launched polar region (22) and surround fully and disposing.And then, on the silicon oxide film (24) on above-mentioned substrate ⒇ surface, form shown in Fig. 2 (a) the 1st layer the 1st base electrode (25) and the 1st emitter electrode (26) that for example form with aluminium-vapour deposition.Here, the 1st base electrode (25) is each contact zone (23) of in the base region (21) ... (23) carry out the resistance number and touch and form many islands, the 1st emission electrode (26) then carries out resistance with almost all surfaces of emitter region (22) and contacts and form netted.
And then shown in Fig. 4 (e), at the 1st base electrode (25) and the topped interlayer dielectric (27) that polyimides etc. is arranged above the 1st emitter electrode (26), adopt etching method to have the 2nd emitter electrode (29) ... (29) and the 2nd base electrode (28) ... (28) contact hole.
Last shown in Fig. 4 (f), for example adopt aluminium-vapour deposition on above-mentioned interlayer dielectric (27), to form the 2nd layer the 2nd base stage (28) ... (28) and the 2nd emitter electrode (29) ... (29).The 2nd base electrode (28) be respectively with many 1st base electrodes (25) that distributing with island ... (25) carry out resistance contact and form the broach shape and stretch towards a direction.The 2nd emission electrode (29) is to carry out the resistance contact between the 1st emitter electrode (26) and the 2nd base electrode (28) with the extension of broach shape bandedly, and the 2nd emission electrode (29) is to be staggered to form the broach shape and to extend to pad with the 2nd base electrode (28).
Fig. 8 represents that 25V is the safety operation area of 1.2mm square chip.Solid line is the characteristic of Fig. 4 (a) original structure (b), and dotted line is the characteristic of structure of the present invention.The present invention can enlarge the ASO characteristic significantly in the thermal resistance district.
According to the present invention,, current capacity is further increased by enlarging the contact area of the 2nd emitter electrode (29) and the 1st emitter electrode (26).As a result, because of just reaching high current capacityization, so can provide production efficiency high transistor with very little area of chip.
Claims (3)
1, one transistor, it is characterized in that: have collector area, base region and emitter region, this emitter region is located at surface, aforementioned base district with netted state, the contact zone in aforementioned base district is configured in the above-mentioned emitter region with many islands, the 1st emitter electrode and the 1st base electrode be made up of the 1st floor carry out the resistance contact are set in the contact zone in above-mentioned emitter region and aforementioned base district, the 2nd base electrode that on by the interlayer dielectric of multiple the 1st emitter electrode and the 1st base electrode, has a broach shape that connects above-mentioned the 1st base electrode with carry out resistance with above-mentioned the 1st emitter electrode and contact and stretch to the transistor of the 2nd emitter electrode of pad, dispose between the broach that is located at above-mentioned the 2nd base electrode, carry out banded the 2nd emitter electrode that contacts with above-mentioned the 1st emitter electrode.
2, the transistor put down in writing of claim 1 is characterized in that: the contact site of said the 1st emitter and the 2nd emitter electrode is arranged at respectively between the broach of said the 2nd base electrode.
3, the transistor put down in writing of claim 1 is characterized in that; The part of said the 2nd base electrode in said base region is formed as the pad district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN85105124.3A CN1004844B (en) | 1985-07-04 | 1985-07-04 | Transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN85105124.3A CN1004844B (en) | 1985-07-04 | 1985-07-04 | Transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN85105124A true CN85105124A (en) | 1986-12-31 |
| CN1004844B CN1004844B (en) | 1989-07-19 |
Family
ID=4794272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN85105124.3A Expired CN1004844B (en) | 1985-07-04 | 1985-07-04 | Transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1004844B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544002A (en) * | 2010-12-20 | 2012-07-04 | 三菱电机株式会社 | Semiconductor device and method of manufacturing the same |
-
1985
- 1985-07-04 CN CN85105124.3A patent/CN1004844B/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544002A (en) * | 2010-12-20 | 2012-07-04 | 三菱电机株式会社 | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1004844B (en) | 1989-07-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0291014B1 (en) | Semiconductor device in which wiring layer is formed below bonding pad | |
| CN1107340C (en) | Method for forming self aligned contact in semiconductor device | |
| CN88101994A (en) | Solar cell | |
| US4278989A (en) | Semiconductor device having cross wires | |
| CN1094252C (en) | Semiconductor substrate and method for making semiconductor device | |
| CN1620715A (en) | Two-mask trench schottky diode | |
| JPH06105708B2 (en) | Semiconductor device | |
| EP0731985A1 (en) | Improved mesh geometry for mos-gated semiconductor devices | |
| CN85105124A (en) | Transistor | |
| US5633526A (en) | Photodiode array and method for manufacturing the same | |
| US4973562A (en) | Method of manufacturing a semiconductor device having interconnections located both above a semiconductor region and above an isolation region adjoining it | |
| DE3542166C2 (en) | ||
| CN1020991C (en) | Isolation method of semiconductor device | |
| EP0847083A3 (en) | A method for manufacturing a capacitor for a semiconductor device | |
| JPS622713B2 (en) | ||
| JPS6289360A (en) | Power thyristor | |
| CN1220486A (en) | Semiconductor device having simultaneously formed contacts on different impurity injected regions and method of forming contacts in semiconductor device | |
| CN1358335A (en) | Light-emitting thyristor matrix array | |
| KR950008239B1 (en) | Semiconductor connect device | |
| JPH0587144B2 (en) | ||
| CN2548262Y (en) | Current-equalizing loop transistor | |
| JPS6386455A (en) | Semiconductor device | |
| SU1037779A1 (en) | Permanent memory storage | |
| TW548793B (en) | Metal interconnect structure | |
| JP2511023B2 (en) | Bidirectional thyristor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C13 | Decision | ||
| GR02 | Examined patent application | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |