CN85104473A - The method of storing responce type digital frequency modulation - Google Patents
The method of storing responce type digital frequency modulation Download PDFInfo
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- CN85104473A CN85104473A CN 85104473 CN85104473A CN85104473A CN 85104473 A CN85104473 A CN 85104473A CN 85104473 CN85104473 CN 85104473 CN 85104473 A CN85104473 A CN 85104473A CN 85104473 A CN85104473 A CN 85104473A
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Abstract
Mode with storage response method realization digital frequency modulation relates to the radio communications system Digital Transmission.The present invention overcomes prior art and takies radio frequency line bandwidth, the weakness strong to adjacent channel interference.Clock signal is sent into level Four frequency divider (1), and its output is the low address signal of memory (4); It is output as the high-order address signal of memory (4) seven bit shift register (2).The clock signal of register (2) is provided through inverter (3) by (1) output of frequency divider.Memory (4) storage digital modulation response signal, its output signal is transformed to modulated-analog signal through D/A translation circuit (5) and (6).Above circuit can be made monolithic integrated circuit.
Description
A kind of mode with storage response method realization digital frequency modulation relates to the radio communications system Digital Transmission.
Existing digital modulation technique generally adopts FSK of frequency shift keying system or MSK, as DRP DE3238143, U.S. Pat 4368439, they all exist and take radio frequency line bandwidth, the weakness strong to adjacent channel interference, therefore can only be used for the wireless radio transmission of the numerical data of low rate.
Task of the present invention is to provide a kind of and realizes the digital frequency modulation mode with the storage response method, can overcome and take radio frequency line bandwidth, the weakness strong, make the digital language signal of two-forty or the data can be in existing analog radio channel to adjacent channel interference.
Task of the present invention is that following mode is finished: external timing signal is sent into level Four frequency divider (1), its output Qa, Qb, Qc, Qd are as the low address signal of memory (4), seven bit shift register (2) are deposited 7 input data signals, and its output Qa, Qb, Qc, Qd Qo, Qf, Qg are as the high address of memory (4).The clock signal of register (2) is provided through inverter (3) by the output Qd of frequency divider (1).Memory is storing the digital modulation response signal of binary form, is read by the address signal that frequency divider (1) and register (2) are provided.Its binary output signal D0, D1, D2, D3, D4, D5, D6, D7 are transformed to modulated-analog signal with binary digital modulation signals and remove to modulate frequency modulator (7) behind D/A (D/A) translation circuit (5) and (6), just obtain digital frequency-modulation signal.More than be that to hold back length be that 7T(T is the cycle of digital signal in impulse response) circuit, if seven bit shift register (2) change five bit shift register into, circuit also can operate as normal, this situation belongs to impulse response and holds back the circuit that length is 5T.Above circuit can be made monolithic integrated circuit except that frequency modulator (7).
Accompanying drawing is a circuit diagram of the present invention.
The invention has the advantages that and to realize neatly various digital radio modulation systems. Optimum working state is to be that Nyquist (NyQUIST) frequency adds that roll-off factor is that 0.5 straight line roll-offs or the response of cosine roll off low pass filter is stored in the circuit with cut-off frequency, be the number language of 16Kbits/S or data-signal then the digital frequency-modulation signal of circuit output can be the analog radio channel of 25KHZ in channel spacing if input is numeric code rate, interference to neighboring trace is lower than 60db, meet Consultative Committee on International Radio's requirement, the channel utilization of present digital radio transmission mode is enhanced about more than once, and the Digital Transmission that realizes with the present invention, error performance is also fine, be that the bit error rate is lower than 10 in the situation of 20db in signal to noise ratio-5, have in addition circuit simple, realize convenient, be convenient to integrated advantage.
Claims (5)
1, a kind ofly realizes the mode of digital frequency modulation, it is characterized in that the circuit of forming by level Four frequency divider (1), seven (or five) shift registers (2), inverter (3), memory (4), steering D/A conversion electrical equipment (5) and (6) with the storage response method.
2, mode according to claim 1, the low address signal that it is characterized in that memory (4) is output Qa, Qb, Qc, the Qd of level Four frequency divider (1), and the high-order address signal of memory (4) is output Qa, Qb, Qc, Qd, Qo, Qf, the Qg of seven (or five) shift registers (2).
3, mode according to claim 1 is characterized in that the output Qd process inverter (3) of the clock signal of register (2) by frequency divider (1).
4, mode according to claim 1, the feature of optimum working state is: be stored in that cut-off frequency is arranged in the circuit is that Nyquist (NyGUIST) frequency adds that roll-off factor is that 0.5 straight line roll-offs or the response of cosine roll off low pass filter.
5, realize that with the storage response method digital frequency modulation mode is characterized in that making monolithic integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85104473 CN85104473A (en) | 1985-06-07 | 1985-06-07 | The method of storing responce type digital frequency modulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85104473 CN85104473A (en) | 1985-06-07 | 1985-06-07 | The method of storing responce type digital frequency modulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN85104473A true CN85104473A (en) | 1986-07-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 85104473 Pending CN85104473A (en) | 1985-06-07 | 1985-06-07 | The method of storing responce type digital frequency modulation |
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| CN (1) | CN85104473A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102752254A (en) * | 2011-04-18 | 2012-10-24 | 美国博通公司 | Communication device and method for operating the communication device |
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1985
- 1985-06-07 CN CN 85104473 patent/CN85104473A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102752254A (en) * | 2011-04-18 | 2012-10-24 | 美国博通公司 | Communication device and method for operating the communication device |
| CN102752254B (en) * | 2011-04-18 | 2015-03-04 | 美国博通公司 | Communication device and method for operating the communication device |
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