CA1079857A - Multi-line, multi-mode modulator using bandwidth reduction for digital fsk and dpsk modulation - Google Patents

Abstract

MULTI-LINE, MULTI-MODE MODULATOR USING BANDWIDTH
REDUCTION FOR DIGITAL FSK AND DPSK MODULATION
Abstract A multi-line multi-mode modulator uses compatible digital modulation techniques for multifrequency (MF), frequency shift keyed (FSK) and differential phase shift keyed (DPSK) modulation to achieve a multi-line multi-mode modulator which is capable of handling a plurality of lines requiring a dynamic mix of the three modulation techniques. The compatible modulation techniques utilize bandwidth reduction schemes which enable the use of simple RC fil-ters on each output line for the sole purpose of removing the quantizing noise introduced by the digital modulation technique.

Description

Field of the Invention The invention relates to modulators in general and more parti-cularly to novel modulators which directly provide a reduced band-width modulated signal and to a multi-line multi-mode modulator capable of simultaneously, on a time shared basis, modulating mutli-frequency, frequency shift keyed and differential phase shift keyed signals from a plurality of sources for transmission over a plurality of lines.
Summary of the Invention The invention is directed to novel digital FSK and DPSK
modulators which are compatible with each other and which produce at their output modulated signals in which out of band energy is reduced thus eliminating the need of any filtering except for simple RC filters for removing quantizing noise introduced by the digital modulation used. These modulators are combined in a novel multi-line multi-mode modulator which is capable of dynamically providing a wide variety of signal modulations on a large number of lines with a substantial reduction of equipment and cost.

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' 1 ~rief Description of the Drawings

2 Fig. 1 is a schematic diagram of a prior art digltal FS~

3 modulator;

4 Figs. lA, lB and lC are graphs illustrating the signals present at several polnts in the circuit of Flg. l;
6 Fig. 2 is a schematic diagram of a novel FSK modulator 7 according to the invention;
8 Fig. 2A is a graph for illustrating the operation of the 9 modulator illustrated in Fig. 2;
Fig. 3 is a table showing the relationship between the 11 selection signals applied to the address generator o~ Fig. 2 12 and the read only memory contents;
13 Fig. 4 is a schematic diagram of a novel DPSK modulator 14 according to the invention;
Figs. 4A, 4B and 4C are graphs~for illustrating the 16 operation of the modulator shown in Fig. 4;
17 Fig. 5 is a table showing the relationship between the 18 selection signals applied to the address generator of Fig. 4 19 and the read only memory contents;
Fig. 6 ls a schematic diagram of a multifrequency 21 modulator constructed in accordance with the prior art;
22 Fig. 7 is a table showing the relationship between 23 the selection signals applied to the address generator of Fig. 6 24 and the read only memory contents;
Fig. 8 is a block diagram of a novel multiline 26 multimode modulator constructed in accordance with the 27 invention;
28 Fig. 9 is a schematic diagram, in greater detail, of 29 the clock and line control word memory unit illustrated in Fig. 8; and RA9-74-oQ2 -2-,~, iO798S7 1 Fig. 10 is a schematic block diagram of the novel modulator illustrated in Fig. 8.
Description of the Prior Art A technique in current use permits the digital synthesis of a sinusoidal wave by directly computing phase angle and performing a phase to amplitude translation by means of a table look-up of previously computed digital values. The digital values may then be converted to analog form by conventional digital to analog conversion techniques. This general digital technique of tone synthesis has been specifically applied to digitally implemented frequency and phase shift keyed modulators. Such a prior art frequency shift keyed modulator is illustrated in Fig. 1. In Fig. 1, a memory 11 con-tains two values a oo and ~81. These digital values represent increments of phase of two waves sinO0 and sin~l used to represent in analog form the binary 0 and 1 data. The input data is applied to a controller 12 which selects, via a switch 14, 400 or ~01 de-pending on the input data applied. This is shown in Fig. lA for a serial input data pattern of (010).
The selected value of a~ is applied via a gate 15, under con-'~ 20 trol of a clock 16 at a frequency fs, to one input of an adder 17 which adds this value to the contents of a buffer 18 which is con-nected to the output of adder 17. The output of adder 17 is illustrated in Fig. lB. The output of adder 17 is applied to a read only memory 19 which accepts the digital phase of O(t) and by table look up pro-vides a digital amplitude signal sin C(t). This signal is applied to a digital to analog converter 20 which supplies a signal to a ;
filter 21 (Fig. lC).
The filter 21 is, of necessity, a complex filter since the .-signal from the modulator includes significant out of band energy introduced by the step-like frequency shifts. In addition, the characteristics of filter 21 must be modified to take into account the specific frequencies used to transmit the binary 1 and 0 values 1 and the rate of transmission. Thus, a different filter must be provided for each type or modulator implemented. Similar digital techniques may be used for both multifrequency (MF) and differential phase shift keyed (DPSK) modulation.
A modulation technique similar to that illustrated in Fig. 1 is utilized in the time shared multiline FSK modulator disclosed in U.S. Patent 3,697,892 to Lawrence et al which provides a specific type of FSK modulation for a set of lines. The multiline time-shared modulator, however, requires separate digital to analog con-verters for each line and a band pass filter for each line capable of eliminating undesired out of band frequency components generated in the modulation process. Because of these requirements, the multiline modulator is incapable of handling a wide variety of modulation techniques which may be used for any of the output lines.
This is so because of the specific requirements for the individual output line band pass filters. In the patented device, each out-put line must, of necessity, be limited to one type of modulation.
If it is desired to change the modulation characteristics for a , given line, it becomes necessary to alter the characteristics of the connected band pass filter. This requirement severely limits the usefulness of the multiline modulator since the lines cannot b~e dynamically allocated to different modulation techniques.

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~079857 I Description of the Preferred Embodiment Fig. 1 described in detail above illustrates the application of digital tone synthesis techniques in an FSK modulator. A digi-tal value of phase O(t) is accumulated and updated each processing cycle determined by fs where fs is the sampling rate of the result-ing modulated digital line signal. The amount by which the phase is incremented each sample time, ~ ~, determines the slope of O(t) and hence the instantaneous frequency of the sine wave generated.
For binary FSK, one of two values of phase increment ~00 and Q01 are selected depending on the data which is to be transmitted. The frequency of the sine wave being generated is directly proportional to the value of ~ 0. a 0 and ~(t) are both digital signals and the accumulation is performed with conventional arithmetic com-ponents. The digital phase signal is scaled such that arithmetic overflow of the accumulator or buffer 18 corresponds to the normal modulo 360 property of the trignometric sine function.
_ The digital representation of phase Ot is translated to a digi-tal representation of sin O(t) by means of the read only memory 19.
The resulting digital amplitude signal is converted to analog by 1 20 conventional digital to analog conversion techniques and subsequent analog filtering. The quantizing noise resulting from the conver-sion from digital to analog is removed by the analog filtering along with other unwanted frequency components introduced by the modulat-ing technique.
In the FSK modulator illustrated in Fig. 1, as well . . . . .

1~79~5'7 1 as in other conventional FSK modulators implemented with 2 either analog or digital circuits, the instantaneous ~requency 3 of the transmitted signal is abruptly swi~ched between two 4 values in the course of being modulated by the input data signal. ~he abrupt transitlon in frequency causes an increase 6 in the bandwldth of the transmitted signal over that actually 7 required to communicate the data by the FM modulation 8 process~ When FSK data transmission over telephone channels 9 is required, it is necessary to reduce the excessive bandwidth generated in two signiflcant applicatlon areas. One in high 11 speed FSK, 1200 to 1800 bits per second transmission, bandwidth 12 reduction is necessary to comply with out of band signal 13 regulations imposed by various regulatory agencies and 14 two in full duplex transmission using a single physical channel, the recelved signal can, in many instances, be 16 significantly smaller in amplitude than the local transmitted 17 signal and the two frequency bands occupied by the two signals 18 may be relatively close. Thls requires that the bandwidth of 19 the transmitted signal be sharply reduced in order to prevent lnterference with the received slgnal.
21 Classically, FSK bandwldth reduction has been at~ained 22 through band pass filtering of the transmitted signal. Some 23 modulators have used premodulation flltering of the data signal;
24 hqwever, this approach has had llmited application since it requires a Iinear FM modulator. Either of the above approaches 26 for reducing unwanted signals introduced in the modulation process 27 has a drawback in a digital implementation of the modulator since 28 the arithmetlc requirements of a digital filter greatly increase 29 the functional complexity of the unit. For this reason, some digital modulators have used rather complex analog filters in 31 their implementation.

RA9~74-002 -6-~0~857 1 A signi~icant reduction in bandwidth can be achieved by 2 eliminating the abrupt frequency transltions normally present 3 in FSK modulation of blnary data. ~his ~n be done by having 4 the instantaneous frequency make a smooth or continuous transition ln changlng from one value to another. Thls 6 is pointed out by Bettinger in "Digital Transmisslon for 7 Mobile Radio", Electrical Communications, Vol. 47, No. 4, 8 1972 at page 225. Such an approach has been implemented 9 by the use of a premodulation filter, as noted earlier, or by the application of a control signal or voltage to 11 a linear modulator. This approach while producing a 12 desirable result is not flexible in many uses and limits 13 the utility of the modulator to a single baud rate and set 14 Of frequencies~
In a digltal FSK modulator constructed according to the 16 invention, a smooth transition ln frequency is accomplished 17 by storing ln memory dlgital values whlch represent a 18 predetermined tra~ectory for the instantaneous frequency to 19 follow and selecting these values based on the interbaud time or time since the last data transition. Such an approach 21 is viable only in a digital FSK modulator where the phase 22 and rate of phase change can be accurately specified.
23 The tra~ectory followed as the frequency is slewed from 24 one value to another is selected to minimize the bandwidth of the modulated signal. Both the shape and the number 26 of intermediate points in the tra~ectory, per bit time, 27 are important parameters in this regard. Analysis and 28 experiment has shown that a sinusoidal tra~ectory with 29 eight points specified in time over the data bit give the 3 best performance in terms of minimum transmit signal 1 bandwidth and minimum loss in receiver detectability.
2 This does not, however, imply that an eight point sine 3 wave tra~ectory is optimum in general. When this technique 4 is implemented as shown in the modulator illustrated in Fig. 2, out of band signaling is reduced to the point where 6 output filtering is no longer required and the sole filtering 7 requirement is that necessitated by the digital modulation technique employed, that is, the removal of the quantizing g noise. This may be accomplished by a simple RC filter.
The modulator illustrated in Fig. 2 is capable of 11 providing the FSK modulation for a single line of a number 12 of different types or frequencies of FSK modulation. It 13 requires binary input data and a line control word signal 14 which in the illustrated embodiment is a single line designating either one type of FSK modulator or another.
16 If the one type is designated, the llne will be at a voltage 17 level indicating the binary 0 and lf the other type is indicated, lB the line voltage will be at a voltage indicating a binary 1.
19 This, of course, could be expanded by providing additional lines for designating the line control word. In addition, 21 the clock generator 30 operating at a frequency fs provides 22 two clock phase signals Cl and C2. These are lllustrated 23 graphically in the flgure and are 180 out of phase with each 24 other. The data signals, the line con~rol word and the two clock signals are applled to an address generator 31. The 26 address generator 31 also receives signals from three conductors 27 32A, 32B and 32C. These 3 conductors represent the three high 2~ order blts from a buffer reglster 32, the functlon of which will 29 be described later on. Based on the inputs described above, address generator 31 logically derives an address which is RA9-74-002 ~8-- ~07~357 l applied to a read only memory 33 to access during one-half - 2 of the clock cycle fs, a value ~T and during the other half 3 of the clock period fs, the value ~9T.
4 The contents of memory 33 are set out in the table of Fig. 3. This table ls divided into two sections. It shows 6 memory address i - i+9 whlch are associated with line control 7 word 0 for one type of FSK modulator and memory addresses j -8 J+9 whlch are associated with line control word l, another 9 type of FSK modulator. Obviously, if additional types of FSK
modulators are to be implemented, additional sections of memory ll would be necessary as well as additional lines for the line 12 control word to distinguish the various FSK modulators being ; 13 implemented. The conditions of the selection signals are 14 indicated ln the righthand columns of the table underneath the headings "Line Control Word, Data, T~ cl and c2. During 16 the first half of the clock cycle fs, that is, when cl and c2 17 are l, 0 respectively, the contents of addresses i and i~l or 18 ~ and ~+l depending on the line control word, will be selected l9 if the three high order bits from buffer 32 are all zeroes or all ones and the data bit is 0 or l, respectively, the 21 contents from address i+l or ~+l, namely, all zeroes will 22 be provided at the output of the read only memory during 23 that particular fs clock cycle. If the contents of the three 24 high order bits and the data bits are any other value, the contents of address i or ~ depending on the line control 26 word will be selected. In this case, this value is an increment 27 dividing the bit period ~ into eight dlfferent values to 28 provide as shown in Fig. 2A, eight dlfferent values of 29 ~ over a single blt period for causing the frequency of the output of the modulator to change values smoothly or 1 sinusoidally as discussed above. For example, if the sampling 2 frequency fs of 18,000 cycles per second ~s selected, this 3 would yleld 30 samples per bit for a 600 bit per second line.
4 Thus, a value of 120 for t/8 will provide eight substantially equal steps if the three high order bits of a 12 bit 6 position register are examlned. Therefore, the numerical 7 value 120 will be stored in blnary form in memory address i 8 to implement a FSK modulation for a 600 bit per second data g rate. During the first half of each cycle fs, this value under the conditions described above, that is, data not 11 zero and the three high order bits from buffer 32 not all 12 zero or data not one and the three high order bits from buffer 13 32 not all ones, will be added or subtracted to modify the 14 contents of register 36. How this is accomplished will become apparent as the description of the circuit shown ln Fig. 2 16 continues.
17 During the second half cycle of clock fs, that is, Cl(0) 18 and C2(1), the values Q~l through Q~8 residing in address 19 locations i+2 through i+9 will be added in a manner similar to that illustrated in Fig. 1 and described below to thus 2~ generate the actual output frequencies from the modulator.
22 The form of the values Q~l through ~8 is illustrated 23 in the graph shown in Fig. 2A. These values are selected 24 to provide a smooth transition from the one frequency to the other.
26 The contents, under the conditions described above, from 27 read only memory 33 are applied to one input of an adder circuit 28 34. The output of the adder circuit is selectively applied 29 under control of clock 30 and a read write memory control circuit 35 to one of two registers 36 and 37. During the first half .

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~079857 1 of the clock period fs, the output of adder circuit 34 is 2 inserted in register 36 under control of read wrlte memory 3 control circuit 35 and during the second half of the clock 4 fs, the output of adder circuit 34 ls inserted in register 37.
Likewise, the contents of register 36 are added in adder 34 6 during the first half of the clock cycle from clock 30 with 7 the output of read only memory 33 and during the second half 8 cycle of clock 30, the contents of register 37 are added in 9 adder 34 with the output from read only memory 33. The addition and readback occur under control of read write memory control 11 circult 35 at different portions of the output from clock 12 circuit 30. Thus, durlng the first portion of each of the 13 clock cycles, the contents of the reglsters 36 and 37 are 14 added to the output of memory 33 by adder 34. After the addition takes place the sum of this addition is inserted into the 16 reglsters 36 and 37. Read wrlte memory control clrcuit 35 may 17 take many forms as is well known in the prlor art for controlllng 18 readlng lnto and out of memory devices and is not shown ln 19 greater detail here since it is well known ln the prlor art.
The contents of register 36 under control of the clock 30 21 Cl output are transferred to buffer 32 and the three high order 22 bits of this register which may, for example, contain 12 bit 23 positions are applied via conductors 32A, 32B and 32C to the 24 address generator 31 and are used as described above for generating the address within read only memory 33 of the 26 data which must be applied during each clock cycle to 27 adder 34.
28 An adder control clrcuit 38 responds to the output of 29 clock 30 and the data input to control the function of adder 3 34; that is, whether an addition or subtraction takes place.
31 During the first half of the clock period of clock 30, an .
.: ' ' 10798~;7 1 addition or subtraction will take place depending upon the 2 direction of change of the data. If the data changes from 3 a 1 value to a 0 value, the contents o~ register 36 must be 4 decremented and if the data changes from a 0 to a 1, the contents of register 36 must be lncremented. Adder control 6 38 includes an AND clrcuit 39 having one input connected to 7 the data line and another input connected to the Cl output 8 of the clock 30. The output of AND circuit 39 is connected 9 vla an OR clrcult 40 to a control lnput of adder 34. When the data is 1 and during the flrst half Or the clock period 11 o~ clock 30, AND clrcuit 39 provides an output via 12 OR circuit 40 which causes the adder to increment or add.
13 When th0 data is zero, the output of AND gate 39 is down 14 and thls signal level causes adder circuit 34 to decrement.
The speciflc lmplementation of thls control is well known in 16 the art and is not further descrlbed here. During the second 17 half of clock 30, the C2 output is connected via OR clrcuit 40 18 to the control lnput of adder 34 and causes the adder to 19 increment during thls second half of the clock period. Buffer 32 ls loaded under control of the Cl output of clock 30, thus, 21 after the contents of reglster 36 have been modlfied as 22 desoribed above, the new value calculated is loaded into 23 buffer 32 where it will be available for the next cycle of 24 clock 30 during the next sampling period.
The output of adder 34 ls applied to a ~ to sine ~
26 converslon circuit 41 which may be a read only memory loaded with 27 precomputed values of sine ~ to perform the conversion.
28 Such devices are well known in the prior art and readily 2y available and are lllustrated throughout this specification in block form only. The output of ~ to sine ~ converter 41 31 is applied to a register 42. Register 42 ls strobed under .

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10'79857 1 control of the C2 clock from clock generator circuit 30 and the 2 contents applled at that time to a conventional digital to 3 analog converter 43. The output of digital to analog 4 converter 43 pulses a simple RC filter 44 whlch ls designed solely to remove the quantlzing noise introdu~ed by modulation 6 process. It is obvious from the above description that the 7 modulator may be changed from any group of frequencies to some 8 other group of frequencles simply by changlng the line control g word and storing the appropriate values for that group in the read only memory 33 since the filter 44 is the same for 11 all values, it need not be changed or switchable.
12 The basic processing time in Fig. 2 is divided into 13 two parts, Cl and C2. During Cl time, a running accumulation 14 Of bit time is calculated. During C2 time, a phase accumulation is calculated as is done ln the conventional dlgltal modulator 16 illustrated ln Flg. 1, wlth the exceptlon that the values of 17 Q~ are selected from memory on the basis of the bit time T
18 ~rom register 32. Ir a data transition occurs, during 19 Cl time, numerical value which at the sampling rate will provlde elght substantially equal detectably dlfferent outputs 21 from register 32 is selected from the ~ memory and 22 added or subtracted depending on the data input. The 23 baud tlme accumulatlon is made sharing the same adder 34 as 24 i3 used for the phase accumulation. The digital value of baud time is prevented from underunning, that is, golng 26 below the all zero state when ~lis subtracted or overrunning, 27 that is, golng above the all one state when ~T iS added.
28 This is accomplished by the all zero condition stored in 29 memory location 1+1 or ~+1 since adding or subtracting all zeroes to any number does not change it. This memory - ; . .

1 address is selected on the basis of the condltions shown 2 in the table of Fig. 3, namely, data 1 and r all one or data 0 and 3 T all zero. In both of these condltlons an under or over 4 run cou~d occur. Therefore, the zero value is added to the ~alue of T contained ln reglster 36 during each processlng 6 cycle. With this control, the baud time value changes from 7 an all zero state to an all one state in eight equal steps 8 spanning the complete bit time when the data changes from 9 a 0 to a 1. Thereafter, the baud time remalns at the all one state until the data changes back to zero. At which 11 time, ~l is subtracted and T iS permitted to increment 12 to the all zero state.
13 At the end of Cl time, the highest three bits of T
14 are transferred to reglster 32 and used to address the ~
memory during C2 time. The three hlghest bits of T select 16 one of the 8 values o~ ~ to be accumulated as T traverses 17 from one data state to the other. As indicated in Fig. 2A, 18 the values o~ ~ addressed by ~ produce a smooth or 19 slnusoidal tra~ectory ln the instantaneous frequency of the transmitted signal. The phase accumulatlon, phase to sine 21 converslon, and digltal to analog conversion are performed in 22 the same manner as for the conventional modulator illustrated 23 in Fig. 1.
24 Fig. 4 is a schematic diagram of a.dlfferential phase shift keyed modulator compatible in implementation with the FSK modulator 26 described above with respect to Fig. 2. The implementation 27 in Fig. 4 provides a narrow band modulation in which the 28 generated transmit signal spectra are sufficiently narrow 29 as not to requlre subsequent filtering for transmission 3 over telephone lines or similar transmission media. The .'.

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- ~ 1079857 1 only requirement being a slmple RC filter to remove the 2 ~uantizlng noise assoc~ated wlth the dlgltal generation of 3 the signals and conversion to analog ~orn.
4 The implementatlon o~ the DPSK modulator illustrated in Fig. 4 ls structurally similar to the FSK modulator lllustrated 6 in Fig. 2. Slnce the two modulation techniques are compatible 7 with each other, the ma~or differences are in the nature 8 of the signals stored in the read only memory. In view of 9 this similarlty, the reference numerals used in Fig. 2 will be used in part ln connection with the description of this 11 flgure. In the DPSK modulator, the clock 30-1 operating at 12 a sampling frequency fs provides five outputs during each sampling 13 tlme. These outputs are illustrated graphlcally in the figure.
; 14 The first output Cl occurs during the first quarter of the perlod of clock 30. The second output C2 occurs during the 16 second quarter, the third output C3 occurs during the third 17 quarter and the fourth and ~ifth outputs occur during the 18 fourth quarter. The fourth output C4 occupylng the first 19 half of the fourth quarter and the fifth output, C5, occupying the last half of the fourth quarter. The clock outputs Cl-C5 21 are applle~ to the address generator 31-1 along with the 22 three high order blts from the ~ buffer 32-1. The line control I ?3 word and one of the two slmultaneously provided data blts for 24 a four phase DPSK modulation. The modulation contemplated in - 25 thls modulator is a conventional four-phase DPSK modulatlon 1 26 ln whlch two blts of a binary digital signal are slmultaneously 27 encoded. The flrst bit D0 defining the sign of the differential 28 phase change and the second blt Dl deflning the magnltude of the 29 change. In this modulator, the magnitude bit is applied to address generator 31 for selecting along with the other inputs 10"~9857 1 the appropriate address within the memory 33-1.
The output of address generator 31-1 selects an address during each of the ~ive processing cycles of cloc~ period 30-1 and reads the data stored in that address from the read only memory 33-1. This data is applied to one input of an adder 34-1. Two feedback register 36-1 and 37-1 similar to the registers 36 and 37 of Fig. 2 are connected from the output of the adder 34-1 to the other input of the adder 34-1 and selectively entered therein by the clock signals from clock generator 30-1 which are applied to a read write control circuit 35-1.
The contents of register 36-1 are applied to adder 34-1 during clock time Cl and added to the contents supplied from read only memory 33-1 then reinserted into register 36-1. At the end of this clock period, the contents of register 36-1 are also inserted into buffer 32-1 and ' are used as previously described for generating the address in address generator 31-1 along with the other inputs applied thereto. How these particular inputs access specific data in the memory will be described I later in connection with the description of Fig. 5 which includes a j table of the memory and the selection signals.
During the second clock period, C2, the contents of register 37-1 are added to the data supplied from read only memory 33-1 and then rein-serted in the register 37-1. T~iis step is repeated during the third :~ :
clock period C3. During clock period C3, the adder 34-1 will either add or subtract depending upon the sign of the D0 data bit applied to ` the adder control circuit 38-1. If the sign bit is negative, adder control~circuit 38-1 will provide an appropriate signal to adder 34-1 ¦ ~ ~ causing a subtraction to take place. If the sign bit is positive, an addition will take place. The ~ ~ .

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l arrangement of adder control circuit 38-1 wlll be described below.
2 Durlng the fourth clock perlod C4, the contents : .:
3 of register 37-l are added to the slgnal supplied by the read 4 only memory 33-l, passed through 9 to sln ~ conversion read only memory 41-l and inserted ln a buffer 45 which is 6 under control of a read-write and clear control circuit 46.
7 Clrcuit 46 responds to clock pulses C4, C5 and Cl. Durlng 8 clock pulse C4 the output from ~ to sln ~ conversion circuit 9 41-l is inserted into buffer 45. The contents of register 37-l are not altered at this tlme. That ls, the summation during ' ll the fourth clock perlod C4 does not alter the contents of buffer ,:1 12 37-l. Thls ls ef~ected by read/wrlte control clrcuit 35-1 in 13 response to the C4 clock pulse. Durlng the fifth clock pulse C5, 4 the slgnalæ supplied from read only memory 33-1 are subtracted , 15 from the oontents of reglster 37-l under control of circuit 38-1. :
.~ 16 The output of adder 34-1 18 passed through e to sin ~ conversion . 17 clrcuit 41-l and applled to one lnput of an adder 47. The 18 other lnput of adder 47 18 connected to bu~fer 45 which during . 19 clock tlme C5 18 read lnto the other lnput of adder 47 under . ~20 control Or read/wrlte and clear clrcult 46. The output of : :~ 21 adder 47 18 lnserted ln reglster 42-l which at the traillng ~ , ~ .
. ~ 22 edge of clock tlme C5 ls applied to a dlgltal to analog ¦ 23 ¢onverter 43-l whlch has lts output connected to fllter 44-1.
~ 24 : Adder control circult 38-l ls provlded with an OR gate 48 - i~25 havlng two lnputs connected to the Cl and C2 outputs of clock . ,- ~
~ 26 generator 30-1. The output of OR gate 48 is connected to one .; ~27 lnput~of another pR gate 49 whlch has lts output connected ~:~ `~28 to tha oontrol lnput Or adder 34-1. When this output is in a ~; 29-~ tate, that is when elther clock pulse Cl or C2 are present, . ~
o ~adder 34-l wlll add the contents applied at its two inputs.

RA9-74-002~ ~ ~ -17-, , .. , . . -- . - . .. .

107~857 1 When the output of OR circuit 49 is 0, the contents applied to the two inputs will be subtracted. An AND gate 50 has one input connected to the DO data bit l;ne said a second input connected to the C3 clock output of clock generator 30-1. When the data b;t DO is 1, during clock period C3, AND gate 50 provides an output which is applied via OR circuit 49 to cause adder 34-1 to assume the adding mode, if the data bit is O indicating the negative sign, the adder will be controlled to perform a subtraction. A
third input to OR circuit 49 is connected to the C4 output of clock gener-ator 30-1 and causes an addition to occur during the C4 clock time. Sum-marizing adder 34-1 under control of adder control circuit 38-1 performs an addition during Cl, C2, and C4 times regardless of the circumstances.
During C3 time it performs an addition, when the DO bit is positive and a subtraction when the DO bit is negative. During C5 time, a subtraction is always performed.
The modulator of Fig. 4 is specifically configured to perform -the function of a four-phase modulator such as the IBM* 3872 and the Bell*
201 modems and is based on encoding two bits of data per baud by the differential phase between bauds as indicated in the table below.
DO Dl Phase Differential 1 1 +45 1 0 +135 ~....
As with the FSK modulation previously described, abrupt trans-itions in phase between bauds in DPSK modulation produce modulated output signals containing excessive out of band frequencies. A significant reduction in the bandwidth of the output signal can be achieved by *Trade Marks - 18 -.

l having the ~ increments between the bauds vary in a 2 smooth manner. Addltional reductions ln bandwidth can 3 be obtained by comblning amplltude modulation wlth the 4 phase modulatlon. The above attrlbuteæ are obtained through a widely used approach which employs a modulated 6 slgnal conslstlng of uslng two phase modulated carrlers, ' 7 each wlth envelope modulatlon. Abrupt phase changes are 8 made when the envelope of the partlcular carrier is zero.
9 The equl~alent modulated signal has a smooth phase transltion, lO and can be wrltten wlth the followlng form.
L(t) 8 E(T) COS ~wct + ~m + ~(T)]
j 12 where Wc - carrler rrequency ¦ 13 9m ~ arbltrary phase angle tnot slgnlflcant since the i, .
14 modulatlon ls on a differentlal phase) E( T) - envelope or amplltude runctlon 16 and ~(T) ~ Phaslng functlon whlch describes the phase 17 change between bauds.
18 The direct but straightforward approach to lmplementlng l9 the above llne signal requires a dlgltal multiplier to accompllsh the amplltude modulatlon. Such an approach would ~21 slgnirloantly~ lncrease the complexlty of the transmitter.
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: ~ ~ ?2 Multlplloatlon ls avolded by taking advantage of the ability , ; 23 to accurately control phase angle withln the transmitter slgnal 24~ ~low. The technlque used ls descrlbed below. Let . , .~ 25~ Ltt) ~ E(T) c08 ~9(t)]
`~^26 where ~t)~Wct + ~m + ~(T) 27 and assume E(T) 1S scaled to a maxlmum level of l.
28 ~ th n E(:T)~ COS 0(t) 3 1/2 {cos ~(t)+cos lE(T)]+cos~(t)-cos lE(T)]~
~129 ~or Lrt)~-~cos;~(t) + 9 0 ( T ) ] + COS [~(t) - ~ O ( T ) ]
3~ ~ where ~90(T)~iS an ofrset angle equal to cos~l~l/2 E(T)]

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~ .

.. ~ .. : .. .. . ~ .

1 Amplltude modulatlon is accomplished by generating 2 two phase modulated slnusoids properly displaced in phase ; 3 by 200(T) and transmitting thelr vector sum as described 4 above in connectlon with the Fig. 4. The processing period as described for the llne ls segmented into five 6 parts. During the flrst part, Cl, a runnlng accumulation of interbaud time T iS made. This is similar to the accumulatlon 8 performed with respect to the FSK modulator described above.
g However, ln the case of DPSK modulation, T can be allowed to overflow since a phase change is made in each baud tlme.
; 11 As in the case of FSK, the three most signiflcant bits of 12 T are used. Thus, E(T) and ~(T) are each defined by eight 13 discrete values per baud. See the graphs ln Flgs. 4A, B and C.
! During the second time periods, C2 of the processing cycle ¦ 15 ~(t) is incremented by an amount ~c whlch corresponds to that 6 part of the phase accumulation due to the carrier frequency 17 Wct. During the third processing time period, C3, 0(t) ls 18 changed by àn~amount ~( T ) which generates the smooth transltion 19 ~(T) ln phase~change over the baud time. Again, this may be seen from the graphs in Figs. 4A-C. ~ ( T ) iS determined by T and the 21 magnitude of thé phase change to be made which 18 determined by .
22 the Dl data bit. The slgn of ~ ( T ) iS determlned by the D0 ~2~3 data bit which controls the sign of the adder via the adder ; z4 control;oircult 38-1. During the fourth and fifth processlng .
;~25 times of each cycle, the offset angle 00(T) is selected from ~26 memory. The particular value selected is determined by the ~--value of~ T and the magnitude o~ the phase change by the data ¦ ;128~ bit Dl. The magnitude of ~O(T) iæ independent of the sign of ¦ 29~ the change. During the fourth C4 tlme, the sum 0(t) + 00(T) ls calculated and converted to an amplitude value whlch is placed ... .... .

i~RA9-74-002 -20-:
I ~ ' . . . , - . . . .:. .
. . .

1 in buffer 45. During the fifth time period, C5, ~(t) - ~O(T) 2 is calculated and converted to an amplitude value and added to the 3 contents of buffer 45 in adder circuit 47, to thus produce 4 the composite modulated signal at the end of C5 time. The output of adder 47 is inserted in the register 42-1 and gated 6 to the digital to analog converter 43-1 at the appropriate 7 tlme by the trailing edge of the C5 clock pulse from clock 8 generator 30-1. the output of the dlgltal analog converter 9 43-1 pulses ~ilter 44-1 to provide the signal on the line.
The filter, a simple RC filter, removeæ the quantizing noise 11 lntroduced by the digltal generation process.
12 The memory contents for read only memory 33-1 are 13 illustrated in Fig. 5. A single bit line control word 14 which may assume two states, 0 and 1. Two sets of values are stored. Each occupy 44 addresses in the memory. The 16 flrst set i-i+33 are associated wlth modulation type ~j 17 LCW = O. The selection process or logic required ln the 18 address generator 31-1 for each of the addresses and the 19 data lnput supplied thereto are illustrated ln the table alon~side each of the address locations.
21 Address i includes a value T/8 which for the sampllng 22 frequency selected wlll when successively added to the contents 23 ln buffer 36-1, reduce the substantially equally spaced detectable 24 outputs from buffer 32-1 which are applled to the address generator 31-1 during a slngle baud time. The contents of 26 address 1 are obtained durlng the clock tlme Cl of each sampling 27 cycle. The data content of the Dl bit and the values from the i~ 28 T buffer 3?-1 have no consequence. Thus, durlng each baud time 29 register 36-1 counts up by the predetermined value T/8 which is selected based on the baud rate of the lnformation and ., ' . , ' ~

.

10798S~

1 the sampling frequency fs by 8 detectably different outputs 2 in the three high order bits of the T buffer 32-1 substantially 3 equally spaced across the baud time. Address i~1 contains a 4 value ~c which in the circuit disclosed in ~ig. 4 produces

- 5 the carrier frequency when lncrementally added in the ~(t)

6 register 37-1. Thls particular quantity 1s provided during

7 the second or C2 clock time and the value again of T and

8 the value of the Dl bit are immaterial. The value selected

9 for ~c is dependent upon the carrier frequency of the modulation.
The contents of memory addresses 1+2 through i+9 contain 11 the ~ (T ) ~ S necessary to provide a smooth transition ~n eight 12 successive steps where the phase is to be advanced or retarded by 13 135 as determined by D0 for the selected baud rate and carrier 14 frequency defined by line control word zero. The particular value selected from these addresses is determined by the three 16 high order bits from the I buffer 32-1. These are illustrated 17 in the table. One of these values is selected during the third 18 clock time of each sampling period C-3, dependlng upon the 19 value of the ~ buffer 32-1. Addresses i+l0 through i+l7 contain simllar values for ~( T ) for a smooth transition of 21 + or -45 and are selected on the same basis and during the 22 same clocking period as addresses 1+2 through 1+9. These 23 values are selected if the Dl bit is a 1 instead of a 0.
24 As prevlously stated, the values of ~O(T j are the same durlng the fourth and fifth cycles, therefore a single set 26 of values for ôO(T) is provided in address i+l8 through i+25 27 for a pHase change of 135 and another set of values for ~O(T) 28 is provided in address 1+26 through i+33 for a phase change 29 of 45 depending upon the status of bit Dl. One or the other 3 of these groups of values for ~0( T ) iS selected during the . , .

~ RA9-74-002 -22-., , .. .. .. .

- ~;079857 1 C4 and C5 processlng perlods. The partlcular one selected 2 from each of the groups ls determlned by the value o~ ~
3 buffer 32-1. More speclfically, the three hlgh order bits 4 contained in the buf~er. During the C4 perlod the value read from memory 33-1 i8 added to the contents o~ reglster 37-1 and stored ln 6 buffer 45 after belng converted ln ~ to sln 3 converslon 7 clrcult 41-1, and during the C5 processing period, the value 8 of eO(T) read from memory 33-1 is subtracted ~rom the contents 9 of register 37-1, converted ln ~ to ~lne 9 converslon circult 41-1 and at that time added to the contents prevlously 11 stored in buffer 45 in the adder 47.
12 The memory includes another set of addresses ~ through ~+33 13 for a ~econd type of DPSK modulator identlfled by llne control 14 word one. These values are slmllar to the values descrlbed above ln addresses 1 through 1+33, however, the partlcular 16 values stored wlll depend upon the carrier frequency and 17 the baud rate for the modulator. If additional modulatlon 18 ~requencles and baud rates are to be lmplemented, addltlonal 19 blocks of memory addresses wlll be requlred and the llne . .
control word will have to be expanded to unlquely ldentlfy i 21 which is to be 6elected by the address generator 31-1.
22 While the modulatlon process has been described ln terms 23 of 4-phase modulatlon, it is extendable to hlgher levels of 24 phase modulation such as 8-phase by providing suitable functions for Q~(T) and 90(T) as will be-well understood by those 26 8killed ln the art.
27 In some lnstances such as where low baud rates are used i ~1~
or where less stringent out of baud slgnal reductlon requirements ~ 29 are stipulated, the amplltude modulatlon described and illustrated i 30 may be ellmlnated. Thls may be accompllshed by elimlnatlng the . , -` ~07~357 1 processlng steps performed furing the c4 and c5 clock times.
2 In this event, the circuit components following ~/sln ~
3 converslon circult 41-1 would be ldentlca to those following 4 the corresponding circuit 41 in Fig. 2.
In addltion, the circult illustrated ln Flg. 4 and 6 described above may be used to perform an amplitude modulation 7 only. This may be accomplished by eliminating the processing 8 step which occurs in the c3 clock time. This would elimlnate 9 the addit~on of the phase components ~ ). In this instance, no structural changes are requlred except for the eliminatlon 11 or suppression o~ the c3 clock tlme and processing steps 12 which occur therein.
13 The modulator illustrated in Fig. 6 is specifically 14 arranged to perform a multlfrequency modulation similar to what ls commonly known as touchtone slgnalllng. In this 16 form of signalling, pairs of selected frequencies are 17 slmultaneously transmitted to convey information. If four A and 18l four B frequencles are available, and one A and one B frequency 19 are simultaneously transmitted, sixteen different paired frequency combinations are avallable for transmltting data. These may 21 typically transmit ten numeric dlglts and six control characters.
22 The modulator has the same ge~eral format as 23 modulators prevlously descrlbed. Four parallel data bits 24 are required to identify two tones, one of which is selected from a group of four and the other of which is selected from 26 another group of four. These are indicated in the drawing as 27 D0 through D3 and are applied directly to the address generator 28 31-2. A clock generator 30-2 provldes a sampling frequency 2~ fs having two phases Cl, C2. The Cl phase occuples the first half of the clock period and the C2 phase occupies the second '.!

' '. ' :. '. .... .. ',, ', ' '. , : ,. .' : .

107~857 1 half of the period of clock 30-2. Both of these signals are 2 applied to address generator 31-2 which based on the lnput 3 signals generates an address ~or accessing phase information stored 4 in a read only memory 33-2. Read only memory 33-2 includes two sets o~ values ~1 and ~2 which are the increments of 6 phase and are simllar to those described in the previous modulators.
7 The value of Q~ selected thus determlnes the frequency of the tone 8 which will be generated by the modulator.
9 The contents of read only memory 33-2 are illustrated in tabular form in Flg. 7, In address locations i through i+l5, the 11 selection signals include the line control word, data bits D0 12 through D3, and the two clock phases Cl and C2. The elght 13 addresses i through i+7 are associated with one of A and B
14 frequencies each including four different frequencies and the addresses i+8 through 1+15 are assoclated wlth another set. These 16 sets are ldentlfied by the line control word being zero or one.
17 The data blts D0 and Dl define the A frequency which must 18 be generated. The generatlon of the A frequency occurs during 19 the first half of the clock perlod lndlcated by Cl being in a posltlve state and C0 in a negative state. The generation 21 of the B freqùency is accomplished durlng the second half 22 of the clock perlod. This may be seen ln the table.
23 The partlcular conflguratlon o~ the D0 and Dl blts selects 24 one of four values of ~1 and the configuration of the D2 and D3 bits selects one of four values of ~2 , selectlons 26 belng made from addresses 1 through i+7 on the basis of 27 the line control word and from the ~1 group on the basis 28 of the Cl clock pulse and from the ~2 group on the basis 29 of the C2 clock pulse. As previously stated, the nature of the data stored and the location 1+8 through i+l5 is similar .~ :
.
~ ............ . . .

1)79857 1 differing only in the values stored. The selection signals 2 except for the llne control word are substantially similar.
3 The contents of the read only memory 33-2 acces~ed by the 4 output o~ address generator 31-2 are applied to one input of an adder clrcult 34-2. The adder clrcult 34-2 ln thls modulator 6 ls always operated ln the add mode and the adder control circuit 7 38-2 produces thls result since the two clock pulses are applied 8 to an OR circuit 52 whlch has lts output connected to one of 9 two lnputs of an AND circult 53. The other lnput of the AND
circuit is connected to a posltive source of voltage and provldes 11 one level at all times slnce the clock pulses Cl and c2 are 12 positive ln alternate half-cycles of the clock generator 30-2.
13 The other control clrcult 38-2 was inserted primarlly to lndlcate 14 the compatibility with the other modulator forms disclosed and 15 descrlbed above.
16 The output of adder 34-2 ls selectlvely 17 applled to one of two reglsters 36-2 or 37-2 under control 18 of a read/write control clrcult 35-2 which responds to 19 clock pulses Cl and C2. When clock pulse Cl is received, ~i 20 register 36-2 lS aonnected to the output of adder circult 34-2 i 21 and when clock pulse C2 lS recelved, register 37-2 is connected 22 to the output of adder clrcult 34-2. The outputæ of reglsters 23 36-2 and 37-2 are connected to the other lnput of adder clrcuit 24 34-2 and are controlled by read/wrlte control clrcuit 35-2 ln 25 the same manner as the input from adder 34-2. Thus, during the 26 flrst clock cycle, ~1 selected by the inputs prevlously 27 descrlbed ls added to the contents of register 36-2 and ~ -28 reinserted in reglster 36-2. During the second half-cycle 29 of the clock period, ~2 as prevlously described, 1~ added to th~ contents of register 37-2.

.` ~

._ _ 1 The output o~ adder 34-2 is applied to a ~ to sine 2 conversion circuit 41-2 ldent~cal to the circuits previously described. The output of the conversion clrcuit ls connected ~;
4 to a register 45-l which is under control of a read/write control circuit 46-l whlch responds to clock pulses Cl and C2.
6 Durlng cloc~ pulse Cl, the output of the converter circuit 41-2 ls lnserted in register 45-1. Durlng clock pulse C2, the contents 8 previously stored in register 45-l ls applied to one input of i g an adder clrcult 47-l. The other input of adder circuit 47-l ls connected to converter 41-2 and forms the sum of the two values :`
11 applied to the two lnputs. The output Or adder 47-l is connected 12 to another reglster 42-2 whlch ls gated at the tralllng edge 13 of clock pulse C2 to a dlgltal to analog converter 43-2 whlch 14 has lts output connected to a slmple RC fllter 44-2.
The modulator descrlbed above ln Flg. 6 is useful for 16 multifrequen¢y or parallel tone generation whlch may be 17 appll¢able for data tran~mlsslon or auto dlallng. These appll-18 oatlon8~u8e 8u~flclently low baud rates as not to require the 19 bandwidth redu¢tlon te¢hniques used ln the two previously 2Q des¢ribed modulators. If hlgher baud rates are requlred, 21~ the technlque~;described ln connectlon wlth Fig. 2 may be used.
22~ Oné~of~four tones are generated~from eac~h of two bands depending ~23~ on~a baud or data oon8istlng of four blts. The processing 24~ ~period ls dlvlded lnto two segments Cl and c2. During the a~5~ Cl~segment~,~blts~D0 and Dl select one of four values of ~
~26~ ~from the memory, the value of ~ determlnes the frequency of 27~ the tone~whl¢h~will be generated. The value of tone 1, 91(t) ~28~ ~stored~ln reglster 36-2, ls incremented durlng each Cl time 29 ~and~converted~to~anlamplltude value sln ~l(t~) and placed 30 ~ ln~the~burfer~register 45-1. Durlng C2 time, -he phase of the A9-74-002 ~ -27-, ... , . . . ~ ,. . . , . ~ . . . . . . .:

~079857 1 second tone, 02(t) is incremented by a value ~ C determined by input bits D2 and D3. The amplitude of the second tone sin 02(tJ
stored in register 37-2 is added to the contents of buffer register - 45-1 to produce the next two tone transmitted signal at the end of C2 time.
Fig. 8 discloses an overall block diagram for a multiline multi-mode modulator which is capable of servicing n input and n output lines substantially simultaneously by a time sharing technique of the modulator. The modulator is capable of providing different varieties of three major types of modulations for any mix of the n lines. The modulation types provided are multifrequency, frequency shift keyed and differential phase shift key modulation. A number of different varieties of each of the types of modulators may be implemented as will become apparent as the description continues.
The multiline multimode modulator includes an input multiplexer 60 connected to n multiwire input lines or cables Ll through Ln.
The multiplexer outputs are connected via an OR circuit 61 to a mul-timode modulator 62 where the signals from each of the n lines are sequentially modulated as required for the particular line. The modu-lated signals from the multimode modulator 62 are applied to a second multiplexer 63 which distributes the modulated signals to the appro-priate output lines l-n via individual RC filters 64-1 through 64-n.
Filters 64-1 through 64-n are identical and each are simple RC fil-ters whose sole function is to remove the quantizing noise from the digital to analog conversion process. A master clock circuit 65 pro-vides control signals to multiplexers 60 and 63 as well as to the multimode modulator 62. In addition, master clock circuit 65 pro-vides control signals to a line control word . ' ' .

~079857 1 memory unit 66 which provides signals to the multimode modulator 2 62 and the master clock circuit 65. Multiplexers 60 and 63 3 operate in synchronism under control of mas~er clock circuit 4 65, thus input llnes l-n are sequentially connected through the multimode modulator 62 to output llnes l-n, respectively~
6 The line control word memory unit 66 includes n address each 7 identified with one of the input lines Ll-n and in which is 8 stored a line control word ldentlfylng the preclse modulation g requlred for that line. That is, which type of modulator lt ls and whlch varlety of modulator of that type is being serviced for 11 that line at that tlme. The line control words may be changed as 12 requirements for modulation for any line are changed. This 13 may be done manually or automatically as will become apparent 14 as the descriptlon contlnues.
The master clock 65 and the line control memory unlt 66 16 are lllustrated ln detall in Flg. 9 slnce these units provide 17 all of the control slgnals for the multiplexers 60 and 63 and ~-18 the multlmode modulator 62.
19 A clock generator 67 operates at a frequency nfs where fs is the sampllng frequency per llne and n is the number of 21 llnes which must be sampled. Except for the actual frequency 1 22 utillzed, this clock is simllar to clock 30-1 of Flg. 4 and 23 provldes during each clock perlod, ~ive outputs lllustrated 24 below the clook ln graphlc form. The flrst output is posltive during the flrst quarter of the perlod and negatlve during the 26 remalnder of the perlod. The second output is positlve only 27 during the second quarter of the perlod. The thlrd output ls 28 positlve only durlng the third quarter of the period. The 29 fourth and fifth outputs are positive during the first and second halves of the fourth quarter, respectively. The one .

;

- 107~857 .:
l output ~rom clock generator 67 ls applied to a binary counter 2 68 which ls arranged to count as hlgh as n and recycle thus 3 lncrementlng one count durlng each period o~ clock generator 4 67. The output of binary counter 68 are applied to a decoder circult 69 wh~ch provldes the enabllng outputs for operatlng 6 multiplexers 60 and 63 since the outputs of decoder 69 sequentially identify one of the n lines. The outputs of binary counter 68 are also applied via gate circuits 70 to latches 71 to 9 provlde a blnary output identlfylng the llnes. The output of ;1 lO latches 71 are applled directly to the multimode modulator 62 I ll and the use of this output will be descrlbed later.
12 In addlton, the outputs o~ blnary counter 68 are utilized I 13 as addresses~or accessing the random access line control word 14 memory 72. Thus, each tlme blnary counter 68 lncrements to a .
15 new value, a new word ls read out of random access line control ~;

16 word memory 72 and provlded on the data output bus 73. Random 17 access llne control word memory 72 is also provided with a data ¦ 18 lnput bus and write control circults whereby llne control words ~l; l9 ~ may be ln8erted lnto the random access memory as needed or deslred rrom some external source such as a computer 74 illustrated 2l ln the~draw1ngs. Typically, computer 74 may also be the source ~ 22 o~ the~da~ta whlch ls being transmitted over lines Ll through ¦ 23 Ln. AIternatlvely, the llne control words may be inserted 24 from a locally assoc1ated terminal connected to~the data bus 25;; and the wr1te~`oontro1~circuits and need only supply the address 26 location and the data to be stored therein.

~ 27 The data output on bus 73 from random acce s line control `1~ `2~ word memory 72;1s applied to a decoder circuit 75 which provides 29~ one of three outputs identi~ying the modulation type. The 30~ ~out~t~s are 1-be1ed MT1, MT2 and MT3. The outputs o~ MTl-MT3 are ¦ -RA9-74-002 _30_ .1 1: ' .

1[)79857 1 applied to the multimode modulator 62 as wlll be apparent in 2 connection with the description of Fig. 10. The data output bus 3 73 is also applied to the multimode modulator 62 and the use of 4 these signals will be described in connectlon wlth the description of Fig. 10.
6 The MTl output from decoder 75 ls connected to two AND
7 gates 76-1 and 76-2. The output MT2 is connected to two AND
8 gates 77-1 and 77-2 and the output ~T3 ls connected to five 9 AND gates 78-1 through 78-5. Gates 78-1 through 78-5 are connected to outputs 1-5 respectively from clock generator 67 and provide 11 flve sequential outputs when the llne control word decoded 12 indicates a differential phase shift keyed modulation function 13 must take place for that line. The outputs o~ the gate 78-1 14 through 78-5 ~or convenience have been labeled A, B, C, Dl and D2, respectively. These pulses in the descrlptlon whlch follows will 16 be consldered clock pulses appearing during a slngle sampllng 17 period for processing purposes ln the circult of Flg. 10 18 whlch-ls a detalled block dlagram of the multlmode modulator 19 62. These signals are applied to the modulator 62 as seen ln 1 20 Fig. 10 in the places indicated by the above alphabetic labels.
21 Outputs 1 and 2 o~ clock gènerator 67 are connected to an OR
22 circuit 79 whlch has lts output connected to AND gates 67-1 and 23 77-1. Outputs 3, 4 and 5 from clock generator 67 are 24 connected to OR circult 80 whlch has its output connected to AND gates 76-2 and 77-2. AND gates 77-1 and 77-2 provide 26 outputs Al and Bl respectlvely when the modulatlon required 27 is FSK while AND gates 76-1 and 76-2 provide outputs A2 and B2 28 when the modulatlon requlred is multi~requency. The tlmings 29 provided by the signals from these AND gates may be determined 3 from the graphs shown below clock generator 67.

.

- , - - . . .

1 Clocks Al and Bl occupy the first and second halves o~
2 a sampling period, and are actlve durlng a FSK modulation.
3 Clocks A2 and B2 occupy the first and second halves 4 of a sampling period and are provlded when a multi-frequency modulatlon takes place for a glven llne.
6 Clocks A, B, C, Dl, and D2 are provlded when a DPSK
7 modulatlon ls taking place for a given llne and are identlcal 8 ln timing during a single clock period as shown ln the graphs 9 below clock generator 67.
, The multlmode modulator lllustrated in Fig. 10 ls similar 1 11 ln many respects to the DPSK modulator illustrated in Fig. 4.
, 12 However, it utlllzes three separate address generators, each -13 slmllar to those prevlously descrlbed and three adder control 14 clrcults simllar to those previously described and selection gates under control of the signals MTl through MT3 illustrated 16 in Flg. 9 and prevlously descrlbed.
17 A three sectlon address generator 80 havlng a 18 flrst section 80-1 for generatlng addresses based on the lnput I 19 data for the selection of signals from the memory sultable for 20 producing multirrequency tone palrsi a section 80-2 for ~ -21 generating addresses suitable for the selectlon of data , 22 for generatlng dlfferentlal phase shlft keyed signals; and ?3 a sectlon 80-3 sultable for generatlng addresses for accessing ; 24 data suitable for generatlng frequency shlft keyed slgnals ; ~ 25 ls conneoted to the output as lndlcated of OR clrcuit 61 whlch ~ 26 provides up to four data llnes ln parallel. The sections are `~ 27 also conneoted to the Al, Bl, A2, B2, A, B, C, Dl and D2 clock 2~ ~signals from-the~master clock 65i to the line control words from 1~ 29~ the~data output bu3 73 of random access line control word memory 30~ ~72; and to a T register 32-2 slmilar to the ~ reglsters previousl~

¦ RA9-74-002 -32-, . .

. r~ ~

~c~798s7 1 described ln connectlon with the description of Figs. 2 and 4 2 and which will be described in detail below. Section 80-1 may 3 be identical to the address generator 31-2 illustrated in Fig. 6.
4 Section 80-2 may be identical to the address generator 31-1 illustrated in Fig. 4 and section 80-3 may be identical to the 6 address generator 31 illustrated in Fig. 2. The outputs of 7 sections Bo-l through 80-3 are connected by gates 81-1 through 81-3 -8 to the control input of a read only memory 82 which contains 9 all the information in read only memories 33, 33-1 and 33-2 of Figs. 2, 4 and 6, respectively.
11 The three section adder control circuit 83 provides adder 12 control for each of the three modulatlon modes, and includes 13 a firqt section 83-1 for provlding the adder control functlon 14 for differential phase shlft keyed modulation, a second section 15 83-2 for providing adder control for frequency shift keyed 16 modulation and a third sectlon 83-3 for performing adder control 17 for multifrequency modulatlon. The inputs to each of these 18 sections are ldentlcal to the correspondlng adder control 19 clrcuits shown in Figs. 2, 4 and 6. Each of the sections is 20 connected by a switch 84 under control of the MTl through MT3 21 outputs from decoder 75 to the control input of an adder 34-3 22 which is similar to adders 34-1 through 34-2 shown in the '. . ' 23 previous figures.

24 The output of read only memory 82 ls connected to one of the inputs Or adder 34-3. The output of adder 34-3 is 26 connected to the data lnput bus of a random access memory 85 and 27 the output bus of random access memory 85 ls connected to the other 28 input of adder 34 and to a T buffer 32-2 similar to the 29 buffers 32 and 32-1 shown in Figs. 2 and 4, respectively, 30 Random access memory 85 contains two address locations for :
, , , ~ - . , . . ~ ,.
: .
- -. , .
.

~079857 1 each of the n lines serviced by the multiline, multifrequency 2 modulator. Which of these addresses is selected is controlled - 3 by an address generator and read/write control circuit 35-3 4 which responds to the LC output from latches 71 and the clock signals Al, Bl, A2, B2, A, B, C, Dl and D2 from master clock 6 circuit 65.
7 For example, if the multiline, multimode modulator is 8 serving four lines, the output of binary counter 68 will be g provided on two lines whlch may be 00, 10, 01 and 11 depending upon which line is being serviced. These two lines may be used 11 as the high order bits of the address in random access memory 85.
12 The low order bit for the address wtll be selected as a function 13 Of the clock signals, Al, A2, and A indlcating a 0 low order bit 14 and the other clock pulses indicatlng a 1 low order bit. During clock times Dl and D2, a read operatlon only takes place.
16 The output of random access memory 85 in additlon to being ~`
17 connected to the other lnput o~ adder circuit 34-3 is connected ' 18 to a T buffer 32-2 whlch is loaded durlng the A and the Al clock J 19 pulse tlmes. The three hlgh order bits from buffer 32-2 are ,l 20 applied to address generators 80-2 and 80-3 and perform the 21 same functionæ in these address generator sections as they 22 performed ln the single line versions described ln Flgs. 2 and 23 4~ ~he output of adder 34-3 ls applled to a ~/sln ~conversion 24 circuit 41-3 slmilar to all of the previously descrlbed ~sin~
25 conversion circults. The remalnder of the circult is functionally 26 similar to that of Fig. 4 and includes a register 45-2 connected 27 to the output of ~sin ~ conversion clrcult 41-3 for receiving 28 the output therefrom under control of a read/write and clear 29 circuit 46-2 and supplying an lnput to a second adder circuit 3o 47-2 which i3 also connected to the output of circuit 41-3. A ~ :

RA9-74-002 -34- ~

.

-107~857 1 register 42-3 is connected to adder 47-2 and supplies when gated 2 a digital to analog converter circuit 433. Read/write and clear 3 control circuit 462 is responsive to cloc~ pulses A, Al, A2, B2, 4 Dl and D2. During clock pulses A and Al, the register is cleared to thus cause adder ¢lrcult 472 to dlrectly pass the output of 6 converslon clrcuit 41-3 to the register 42-3 without alteration 7 since in these instances, the function performed by the adder 8 circuit 47-2 is not needed or desired. During the Dl and A2 9 clock tlmes, the contents from conversion circuit 41-3 are read into the register 45-2 and during the D2 and B2 clock pulses, 11 the contents of reglster 45-2 are read into the adder circuit 12 47-2 where they are added to the then available contents from 13 conversion circult 41-3. The output from dlgital to analog 14 converter circult 43-3 ls applied to the input of multiplexer 63 lllustrated ln Flg. 8 and under control of the master 16 clock slgnals from clock 65, lt ls distributed to the 17 approprlate output llne l-n vla the slmple RC fllters 64-1 18 through 64-n.
19 The three ma~or modulatlon technlques implemented ln Flg. 10 are identical to the three modulation techniques 21 illustrated and described with respect to Figs. 2, 4 and 6.
22 The only di~ference being that the address generator for 23 accesslng read only memory 82 ls expanded to encompass all 24 of the varlous modulatlon types, the clock is expanded to provide each of the clocklng signals, the adder control circuit 83 26 18 expanded to provide the three dlf~erent types of addition 27 control previously described and the ~witch 84 is pro~ided 28 to connect the appropriate adder control slgnals as indicated 29 by the signals from the master clock 65. The only other addition is the expansion Or random access memory 85 to include RA9-74-002 _35 .
.

1 two address positions for each of the lines handled by the multiline, multimode modulator. Since only two address positions are required for each line~ random access memory 85 is general purpose and the only signals needed to select the appropriate addresses are those signals from master clock 65 which identify the line currently being serv;ced and those clocking signals necessary to control the function of the memory 85. The remaining circuits are, as previously stated, identical to those of Figs. 4 and 6.
~nsofar as the modulation technique described in Fig. 2 is concerned, the adder 47-2 and the register 45-2 and control 46-2 are superfluous and the reason for providing the reset signal as stated above, is to remove these circuits in those instances where the frequency shift key modulation is being implemented. Since in those instances, zero is inserted in the register 45-2 and an addition of zero to the digital signals provided by the converter circuit 45-3 passes those signals on through to register 42-3 unchanged.
It is obvious that this circuit provides substantial savings in cost since expanding it to 16 or more lines merely required minor additions to the read/only memory 82 to store the factors of the different types of modulation required and the expansion of the random access memory 85 to include two registers for each of the lines serviced.
While the invention has been particularly shown and described , with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

::-: ~ , . .

Claims (27)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A DPSK modulator for modulating serial binary encoded data by generating an analog signal, the phase of which varies as a func-tion of the serial binary data comprising:
first memory means storing a first numerical value represent-ing a fraction of the baud time of the serial binary encoded data, a second numerical value corresponding to a phase increment of a carrier wave, and a group of n numerical values for each of the possible phase transistions for encoding the data on the carrier wave, each of said n numerical values representing a predetermined phase trajectory;
an adder having two inputs, one of which is connected to the output of said first memory means;
first and second registers, each having an input connected to the output of said adder and an output connected to the said other input of said adder;
a sampling clock means providing first, second and third clock pulses during mutually exclusive parts of each of said sampling periods;
first means responsive to said first register and said first clock pulse for providing signals corresponding to the contents of said first register during each sampling period;
control means responsive to said first, second and third clock pulses for connecting said first register between the output and input of said adder under control of said first clock pulse and said second register under control of the said second and third clock pulses;
adder control means responsive to said data signal and said clock signals for generating a control signal applied to said adder which causes said adder to perform an addition function under control of said first and second clock pulses and a sub-traction function under control of said third clock pulse when the sign value of the data signal is negative and addition function when the sign value of the data is positive;
an address control generator responsive to the data signals, the signals from said first means and said first, second and third clock signals for generating a first address signal during each sampling period under control of said first clock signal for access-ing the first numerical value from said memory for modifying the value stored in said first register as a function of the numerical value accessed and the status of the adder control means, for generat-ing a second address signal during each sampling period under con-trol of said second clock pulse for accessing the second numerical value for modifying the value stored in the said second register as a function of the numerical value, and for generating a third address signal during each sampling period under control of said third clock pulse for accessing one of said n numerical values as a function of the signal to be modulated and the signal supplied by said first means for modifying the value stored in said second register as a function of the numerical value accessed and the output from said adder con-trol means; and second means responsive to the adder output under control of the said third clock pulse for converting the adder output to an analog signal.

2. A DPSK modulator as set forth in claim 1 in which the groups of n numerical values for each of the possible phase transitions are selected to cause said phase transitions, under control of the data, to be made in a substantially continuous manner within a single baud time whereby out of band frequency components in the generated analog signal are substantially reduced.

3. A DPSK modulator as set forth in claim 2 in which the said first numerical value is substantially smaller than the numerical value of the sampling frequency and which when accumulated in the first register will when selected outputs therefrom are monitored provide n substantially equispaced detectably different outputs during each baud time.

4. A DPSK modulator as set forth in claim 3 in which n is selected to have a value of 8.

5. A DPSK modulator for modulating serial binary encoded data at different baud rates and carrier frequencies comprising:
first memory means storing for each said baud rates and car-rier frequencies a first numerical value representing a fraction of the baud time of the serial binary encoded data, a second numerical value corresponding to a phase increment of a carrier wave, and a group of n numerical values for each of the possible phase transi-tions for encoding the data on the carrier wave, each of said n numerical values representing a predetermined phase trajectory;
an adder having two inputs, one of which is connected to the output of said first memory means;
first and second registers, each having an input connected to the output of said adder and an output connected to the said other input of said adder;
a sampling clock means providing first, second and third clock pulses during mutually exclusive parts of each of said sampling periods;
first means responsive to said first register and said first clock pulse for providing signals corresponding to the contents of said first register during each sampling period;
control means responsive to said first, second and third clock pulses for connecting said first register between the output and input of said adder under control of said first clock pulse and said second register under control of the said second and third clock pulses;
adder control means responsive to said data signal and said clock signals for generating d control signal applied to said adder which causes said adder to perform an addition function under control of said first and said second clock pulses and a subtraction function under control of said third clock pulse when the sign value of the data signal is negative;
an address control generator responsive to a line control word signal which uniquely defines one of said baud rates and carrier frequencies, the data signals, the signals from said first means and said first, second and third clock signals for generating a first address signal during each sampling period under control of said first clock signal for accessing one of the said first numerical values from said memory corresponding to the line control word sig-nal for modifying the value stored in said first register as a func-tion of the numerical value accessed and the status of the adder control means, for generating a second address signal during each sampling period under control of said second clock pulse for access-ing the said second numerical value corresponding to the line control word signal for modifying the value stored in the said second regis-ter as a function of the numerical value, and for generating a third address signal during each sampling period under control of said third clock pulse and said line control word signal for accessing one of said numerical values from the group corresponding to said line con-trol word signal as a function of the signal to be modulated and signal supplied by said first means for modifying the value stored in said second register as a function of the numerical value accessed and the output from said adder control means; and second means responsive to the adder output under control of the said third clock pulse for converting the adder output to an analog signal.

6. A DPSK modulator as set forth in claim 5 in which each of the groups of n numerical values for each of the possible phase transi-tions are selected to cause said phase transitions under control of the data to be made in a substantially continuous manner within a single baud time whereby out of band frequency components in the generated analog signal are substantially reduced.

7. A DPSK modulator as set forth in claim 2 in which the said first numerical value is substantially smaller than the numerical value of the sampling frequency and which when accumulated in the first register will when selected outputs therefrom are monitored provide n substantially equispaced detectably different outputs during each baud time.

8. A DPSK modulator as set forth in claim 7 in which n is selected to have a value of 8 .

9. A method for digitally generating narrow bandwidth DPSK modulated signals comprising the steps of:
storing a digital numerical value corresponding to a phase increment of a carrier wave and a predetermined trajectory for each of the possible phase transitions in the form of n discrete digital numerical values for each of the possible phase transitions;
for each data transition; selecting the stored value correspond-ing to the carrier wave, calculating the instantaneous phase in digital form and storing the calculated value, selecting one of the stored groups of n discrete numerical values as a function of the signal to be modulated and selecting from said group each of said n discrete numerical values at least once as a function of the interbaud time, and algebraically accumulating as function of the signal to be modulated the selected values and the stored digital phase value of the carrier wave; and converting each such accumulated digital phase values to an analog signal having the same instantaneous phase.

10. A DPSK modulator for modulating serial binary encoded data by generating an analog signal, the phase of which varies as function of the serial binary data comprising:
first memory means storing a first numerical value represent-ing a fraction of the baud time of the serial binary encoded data, a second numerical value corresponding to a phase increment of the carrier wave, a group of n numerical phase values for each of the possible phase transitions for encoding phase data on the carrier wave, each of said n numerical phase values representing a pre-determined phase trajectory, and n numerical amplitude values for each of the possible phase transitions in the form of n discrete numerical amplitude values, each of which represents an offset angle with respect to the phase angle of the phase modulated carrier wave;
an adder having two inputs, one of which is connected to the output of said first memory means;
first and second registers, each having an input connected to the output of said adder and an output connected to the said other input of said adder;
a sampling clock means providing first, second, third, fourth and fifth clock pulses during mutually exclusive parts of each of said sampling periods;
first means responsive to said first register and said first clock pulse for providing signals corresponding to the contents of said first register during each sampling period;
control means responsive to said first, second, third, fourth and fifth clock pulses for connecting said first register between the output and input of said adder under control of said first clock pulse and said second register under control of the said second and third clock pulses and for connecting said second register to the input of said adder under control of said fourth and fifth clock pulses;
adder control means responsive to said data signal and said clock signals for generating a control signal applied to said adder which causes said adder to perform an addition function under control of said first, second and fourth clock pulses and an addition function when the sign value of the data signal is positive under control of said third clock pulse and a subtraction function at all other times;
an address control generator responsive to the data signals, the signals from said first means and said first, second, third, fourth and fifth clock signals for generating a first address signal during each sampling period under control of said first clock signal for accessing the said first numerical value from said memory for modifying the value stored in said first register as a function of the numerical value accessed and the status of the adder control means, for generating a second address signal during each sampling period under control of said second clock pulse for accessing the said second numerical value for modifying the value stored in the said second register as a function of the numerical value accessed, for generating a third address signal during each sampling period under control of said third clock pulse for accessing one of the said n numerical phase values as a function of the signal to be modulated and the signal supplied by said first means for modifying the value stored in the said second register as a function of the numerical value accessed and the output from said adder control means, for generating a fourth address signal during each sampling period under control of said fourth clock pulse for accessing one of the said n numerical amplitude values as a function of the sig-nal to be modulated and the signal supplied by the said first means for forming the sum of the accessed signal and the contents of the second register at the output of the adder, and for generating a fifth address signal during each sampling period under control of the said fifth clock pulse for accessing one of the said n numerical amplitude values as a function of the signal to be modulated and the signal supplied by the said first means for forming the differ-ence at the output of the said adder between the values stored in the said second register and the numerical value accessed;

converter means connected to the output of said first adder for converting the digital values supplied thereto to digital sinusoidal signals;
second adder means having one of two inputs connected to the said converter means, buffer means responsive to said fourth and fifth clock pulses having an input connected to the said converter means for storing the converted output available during the fourth clock pulse and for providing the output stored during the fourth clock pulse to the other input of the second adder means during the fifth clock pulse;
gate means responsive to the output of said second adder means for passing the output during the terminal portion of the fifth clock pulse; and second means responsive to the gate means output for converting the digital output to an analog signal.

11. A DPSK modulator as set forth in claim 10 in which the groups of n numerical phase values for each of the possible phase transi-tions are selected to cause said phase transitions under control of the data to be made in a substantially continuous manner within a single baud time and in which the groups of n numerical amplitude values for each of the possible phase transitions are selected to cause said amplitude transitions under control of the data to be made in a substantially continuous manner within a single baud time whereby out of band frequency components in the generated ana-log signals are substantially reduced.

12. A DPSK modulator as set forth in claim 11 in which the said first numerical value is substantially smaller than the numerical value of the sampling frequency in which when accumulated in the first register will when selected outputs therefrom are monitored provide n substantially equally spaced detectably different outputs during each baud time.

13. A DPSK modulator as set forth in claim 12 in which value n for the phase and amplitude transitions is selected to have a value of 8.

14. A DPSK modulator for modulating serial binary encoded data at different baud rates and carrier frequencies comprising:
first memory means storing for each of said baud rates and carrier frequencies a first numerical value representing a fraction of the baud time of the serial binary encoded data, a second numerical value corresponding to a phase increment of the carrier wave, a group of n numerical values for each of the possible phase transitions for encoding phase data on the carrier wave, each of said n numerical values representing a predetermined phase trajectory, and n numerical values for each of the possible phase transitions in the form of n discrete numerical amplitude values, each of which represents an offset angle with respect to the phase angle of the phase modulated carrier wave;
an adder having two inputs, one of which is connected to the output of said first memory means;
first and second registers, each having an input connected to the output of said adder and an output connected to the said other input of said adder, a sampling clock means providing first, second, third, fourth, and fifth clock pulses during mutually exclusive parts of each of said sampling periods;
first means responsive to said first register and said first clock pulse for providing signals corresponding to the contents of said first register during each sampling period;
control means responsive to said first, second, third, fourth and fifth clock pulses for connecting said first register between the output and input of said adder under control of said first clock pulse and said second register under control of the said second and third clock pulses and for connecting said second register to the input of said adder under control of said fourth and fifth clock pulses;
adder control means responsive to said data signal and said clock signals for generating a control signal applied to said adder which causes said adder to perform an addition function under con-trol of said first, second and fourth clock pulses and an addition function when the sign value of the data signal is positive under control of said third clock pulse and a subtraction function at all other times;
an address control generator responsive to a line control word signal which uniquely defines one of said baud rates and carrier frequencies, the data signals, the signals from said first means and said first, second, third, fourth and fifth clock signals for generating a first address signal during each sampling period under control of said first clock signal for accessing one of the said first numerical values from said memory corresponding to the line control word signal for modifying the value stored in said first register as a function of the numerical value accessed and the status of the adder control means, for generating a second address signal during each sampling period under control of said second clock pulse for accessing the said second numerical value cor-responding to line control word signal for modifying the value stored in the said second register as a function of the numerical value accessed, for generating a third address signal during each sampling period under control of said third clock pulse and said line control word signal for accessing one of the said n numerical phase values from the group corresponding to said line control word signal as a function of the signal to be modulated and the signal supplied by said first means for modifying the value stored in the said second register as a function of the numerical value accessed and the output from said adder control means, for generat-ing a fourth address signal during each sampling period under con-trol of said fourth clock pulse and said line control word signal for accessing one of the said n numerical amplitude values from the group corresponding to said line control word signal as a function of the signal to be modulated and the signal supplied by the said first means for forming the sum of the access signal and the con-tents of the second register at the output of the adder, and for generating a fifth address signal during each sampling period un-der control of the said fifth clock pulse and said line control word signal for accessing one of the said n numerical amplitude values from the group corresponding to said line control word signal as a function of the signal to be modulated and the signal supplied by the said first means for forming the difference at the output of the said adder between the values stored in the said second re-gister and the numerical value access;
converter means connected to the output of said first adder for converting the digital values supplied thereto to digital sinu-soidal signals;
second adder means having one of two inputs connected to the said converter means;
buffer means responsive to said fourth and fifth clock pulses having an input connected to the said converter means for storing the converted output available during the fourth clock pulse and for providing the output stored during the fourth clock pulse to the other input of the second adder means during the fifth clock pulse;
gate means responsive to the output of said second adder means for passing the output during the terminal portion of the fifth clock pulse;
second means responsive to the gate means output for converting the digital output to an analog signal.

15. A DPSK modulator as set forth in claim 14 in which the groups of n numerical phase values for each of the possible phase transi-tions are selected to cause said phase transitions under control of the data to be made in substantially continuous manner within a single baud time and in which the groups of n numerical amplitude values for each of the possible phase transitions are selected to cause said amplitude transitions under control of the data to be made in a substantially continuous manner within a single baud time whereby out of band frequency components in the generated analog signals are substantially reduced.

16. A DPSK modulator as set forth in claim 15 in which the said first numerical value is substantially smaller than the numerical value of the sampling frequency in which when accumulated in the first register will when selected outputs therefrom are monitored pro-vide n substantially equally spaced detectably different outputs during each baud time.

17. A DPSK modulator as set forth in claim 16 in which value n for the phase and amplitude transitions is selected to have a value of 8.

18. A method for digitally converting narrow bandwidth DPSK modu-lated signals in which the signals are both phase and amplitude modulated comprising the steps of:
storing a digital numerical value corresponding to a phase increment of a carrier wave, a predetermined trajectory for each of the possible phase transitions in the form of n discrete numerical phase values for each of the possible phase transitions, and a pre-determined trajectory for each of the possible phase transitions in the form of n discrete numerical amplitude values each of which represents an offset angle with respect to the phase angle of the phase modulated carrier wave;
for each data transition; selecting the stored value correspond-ing to the carrier wave, calculating the instantaneous phase in digital form and storing the calculated value, selecting one of the stored groups of n discrete numerical phase values as a function of the signal to be modulated and selecting from said group each of said n discrete numerical phase values at least once as a func-tion of the interbaud time, algebraically accumulating as a function of the signal to be modulated the selected values and the stored digital phase value of the carrier wave, selecting one of the stored groups of n discrete numerical amplitude values as a function of the signal to be modulated and selecting from said group each of said n discrete offset numerical amplitude values at least once, forming the sum and difference of the selected offset numerical amplitude values and the accumulated value, converting the said sum and difference values to digital sinusoidal signal, and summing the converted digital sinusoidal signals; and converting the said summed converted signals to an analog sig-nal having the same instantaneous phase as the accumulated value and an amplitude modulation which is equal to the cos of the off-set angles.

19. AN FSK modulator for modulating serial binary encoded data by generating an analog signal of a first frequency for representing binary data of one value and an analog signal of a second freqency for representing binary data of said other value comprising:
first memory means storing a first numerical value representing a fraction of the baud time of the serial binary encoded data and a plurality of second numerical values each representing different frequency increments;
an adder having two inputs, one of which is connected to the output of said first memory means;
first and second registers, each having an input connected to the output of said adder and an output connected to the said other input of said adder;
a sampling clock means providing a first clock pulse during one part of each sampling period and second clock pulse during another part of the sampling period;

first means responsive to said first register and said first clock pulse for providing signals corresponding to the contents of said first register during each sampling period;
control means responsive to said first and second clock pulses for connecting said first register between the output and input of said adder under control of the first clock pulse and the second register under control of the second clock pulse;
adder control means responsive to said data signals and said clock signals for generating a control signal applied to said adder which causes said adder to perform a subtraction function under control of said first clock signal when the data signal represents a binary zero value and an addition function at all other times;
an address control generator responsive to data signals, and signals from said first means for generating a first address signal during each sampling period under control of said first clock signal for accessing a said first numerical value from said memory for modifying the value stored in said first register as a function of the numerical value accessed and the status of the adder control means, and for generating a second address signal during each samp-ling period under control of said second clock pulse for accessing a second numerical value for modifying the value stored in said second register as a function of the numerical value accessed; and second means responsive to the adder output under control of said second clock pulse for converting the digital adder output to an analog signal.

20. An FSK modulator as set forth in claim 19 in which the plurality of second numerical values are selected to cause frequency transi-tions between said first and second frequencies to be made in a substantially continuous manner within a single baud time whereby out of band frequency components in the generated signal are sub-stantially reduced.

21. An FSK modulator as set forth in claim 20 in which the said first numeric values are all zero and a positive value substantially smaller than the numeric value of the sampling frequency, which when accumulated in the first register will when selected outputs there-from are monitored provide n substantially equispaced detectably different outputs during each baud time.

22. An FSK modulator as set forth in claim 21 in which n is selected to have a value of eight.

23. An FSK modulator suitable for modulating serial binary encoded data at different baud rates and modulation frequencies comprising:
first memory means storing for each said baud rate and frequencies a first numerical value representing a fraction of the baud time of the serially encoded binary data and a plurality of second numerical values each representing different frequency increments;
an adder having two inputs, one of which is connected to the out-put of said first memory means;
first and second registers, each having an input connected to the output of said adder and an output connected to the said other input of said adder;
a sampling clock means providing a first clock pulse during one part of each sampling period and second clock pulse during another part of the sampling period;
first means responsive to said first register and said first clock pulse for providing signals corresponding to the contents of said first register during each sampling period;
control means responsive to said first and second clock pulses for connecting said first register between the output and input of said adder under control of the first clock pulse and the second register under control of the second clock pulse;
adder control means responsive to said data signals and said clock signals for generating a control signal applied to said adder which causes said adder to perform a subtraction function under control of said first clock signal when the data signal represents a binary zero value and an addition function at all other times;
an address control generator responsive to data signals, a line control word signal which uniquely defines one of said baud rates and frequencies, and signals from said first means for generat-ing a first address signal during each sampling period under con-trol of said first clock signal for accessing one of said first numerical values corresponding to the line control word signal from said memory for modifying the value stored in said first register as a function of the numerical value accessed and the status of the adder control means, and for generating a second address signal during each sampling period under control of said second clock pulse for accessing a second numerical value from the plurality of second numerical values corresponding to the line control word signal for modifying the value stored in said second register as a function of the numerical value accessed; and second register means responsive to the adder output under control of said second clock pulse for converting the digital adder output to an analog signal.

24. An FSK modulator as set forth in claim 23 in which each of the plurality of second numerical values are selected to cause frequency transitions between the frequencies used for encoding the data to be made in a substantially continuous manner within a single baud time whereby out of band frequency components in the generated signals are substantially reduced.

25. An FSK modulator as set forth in claim 24 in which each of the said first numerical values are all zero and a positive value substantially smaller than the numeric value of the sampling frequency, which when accumulated in the first register will when selected outputs therefrom are monitored provide n substantially equi-spaced detectably different outputs during each baud time.

26. An FSK modulator as set forth in claim 25 in which n is selected to have a value of eight.

27. A method for digitally generating narrow bandwidth FSK modulated signals comprising the steps of:
storing a predetermined trajectory for the instantaneous fre-quency transitions in the form of n discrete digital numerical values;
selecting within each baud time in which a frequency transition occurs each of said n discrete numerical values at least once, said selections being determined as a function of the interbaud time;
calculating the instantaneous phase in digital form based on each selected numerical value, and converting the calculated instantaneous digital phase to an analog signal having the same instantaneous phase.