CH654155A5 - CONVERTER IN A MODULATOR FOR THE PHASE MODULATION OF DATA SYMBOLS. - Google Patents

Description

The present invention relates to a converter according to the preamble of claim 1. The phase modulation of data symbols, of which each symbol is received during a time interval and converted into a sequence of phase values by means of a memory arrangement, serves to determine how the phase of the carrier frequency generated in the modulator is continuously shifted during the time interval. In symbol correlation, which includes L. symbols, each sequence of data values is determined by a current symbol and symbols preceding L-1. In order to facilitate a so-called coherent demodulation, the phase should not only change continuously within each time interval, but also during successive time intervals that are associated with any symbol sequence.

Thorough theoretical studies have shown that the quality of the signal transmission of the phase modulation is improved if the symbol correlation increases and if the data symbols contain M> 2 signal levels of unchanged bit rate. M = 2 or 4 or 8 defines a binary, a quaternary or an octal system. The theoretical basis for digital phase modulation was e.g. published by Aulin, Rydbeck and Sundberg in "Further results on digital FM with coherent phase tree démodulation - Minimum distance and spectrum", Technical Report TR-119, November 1978, Télécommunication The-ory, University Lund, Sweden; pages 70-74 of this publication contain a detailed list of relevant references.

In the literature reference (33) of the above-mentioned Technical Report TR-119 and in the Swedish patent application No. 78.09358-0, a symbol correlation-converting converter and a method for the so-called “Tamed Frequency Modulation” (tamed frequency modulation) are described. The known converter comprises a memory arrangement for storing and entering sequences of cosine and sine

Phase values in digital form. The memory arrangement is provided with a shift register which receives differential encoded data symbols M = 2 and contributes to the implementation of the symbol correlation.

Overall phase continuity is accomplished using a quadrant counter and thanks to the fact that cosine and sine sequences stored in the memory array are determined by a filtered version of a number of consecutive binary signals, and further by selecting a modulation index h = 0.5 , resulting in exact phase shifts with the angles 0; ± n / 4 and ± n / 2 leads.

If ML different phase value sequences are calculated in a known manner, the phase values indicating phase changes relative to the phase value at the end of the preceding symbol time interval, overall continuity of the phase can be achieved trivially and simply by means of a memory arrangement for entering, addressing and reading the ML phase change sequences, which memory arrangement is a register for inputting said final phase values and an adder for adding the stored final phase value to the phase change values successively read from the memory arrangement.

The Swedish patent application mentioned above explains that such a trivial continuity solution is accompanied by serious demodulation difficulties with the resulting high probability of errors. However, it must be possible on the receiver side to reproduce both the modulation carrier frequency and the time intervals of the symbols. It is therefore necessary that the phase value sequences are connected to absolute phase values 0 g 0 <2 7 t. Because with demodulation, accumulating phase fields during transmission are avoided, and unknown frequency shifts caused by interference between the transmitter and receiver can be more easily distinguished and eliminated.

Phase errors that accumulate in the known converter mentioned are easily avoided because the phase value remains in the same phase quadrant during a symbol interval or changes over to the adjacent higher or lower phase quadrant. In this regard, the known converter is created for the storage of sine and cosine sequences, the values at the ends of which relate to the edge or the center of a quadrant.

However, such a quadrant counter is completely inadequate for modulating data symbols with M> 2 in connection with a correlation extending over an arbitrary number of symbols, and also in connection with any rational modulation indices and sequences of absolute phase values which are necessary to achieve a transmission and high quality demodulation.

The present invention is therefore based on the object of creating a converter with which an arbitrarily complex digital phase modulation can be achieved and with which the quality of a simple phase modulation system can also be improved compared to that of known modulators.

According to the invention, this object is achieved by a converter as defined in claim 1. In such a converter, the known quadrant counter is replaced by a unit for calculating so-called phase states, each of which defines a phase state number from a finite group of phase state numbers. Access to the sequences of absolute phase values stored in the memory arrangement is thus achieved by means of addresses which are determined by the symbols received and the phase status numbers. The number of addresses, i.e. the required capacity of the memory remains small in relation to the degree of complexity of the system.

5

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654 155

Further details of the invention will be described with reference to the drawing, in which the

1 and 4 known modulators for the phase modulation of data symbols,

5 to 8 different forms of the converter according to the invention and

2, 3 and 9 to 12 “phase trees”, phase transition diagrams and phase value sequences show how they are stored in the memory arrangement.

A general description of a modulated signal as used in the converter according to the invention is given below. The required optimal maximum-likelihood sequence estimator (MLSE; investigator of the greatest probability sequence) has been calculated assuming that the signal is transmitted on an additive white Gaussian channel. Thanks to the fact that the logarithmic probability function can be written recursively and that the signal at the symbol transition moments can be described by a finite number of states, it is demonstrated that the Viterbi algorithm can be used.

The invention is based on the following system model:

(1)

a sequence of uncorrelated Mth data symbols [ai =

± 1, -1-3, + (M-l)] up to the nth symbol time interval.

The constant envelope CPFSK signal is called

(2)

defines in which the phase function carrying the information

(3)

and where g (t) is a pulse of the duration of L symbol intervals. That is,

(4)

E is the symbol of energy, fo the carrier frequency and 0 any constant phase shift, which can be set to zero in the case of coherent transmission without loss of generality.

A schematic modulator for such a signal [see equation (2)] is shown in FIG. 1 and comprises a filter with impulse response g (t) and a voltage-controlled oscillator VCO.

The modulation index is referred to as variable h and is defined by equation (9). For positive pulses or pulses that satisfy equation (7), this means that the largest absolute phase change over a symbol interval (M-1) is h rad. This is exactly or approximately fulfilled for all considered pulses. The phase change over a symbol interval is using equation (3)

(5)

The variable substitution x - iT -> a results

(ö).

If the pulse g (t) is not negative for all t e [0, LT], or applies

(7)

the largest absolute phase change over a symbol interval

(8th)

Hence the normalization condition

(9)

5 This condition is met if

(10)

For any pulse g (t), using equation (10), a search for the largest absolute phase change over a symbol interval with respect to the variables an, <Xn-i, .. \, a ".l + i must be carried out will.

If pulses g (t) which have no limited duration are used, the greatest phase change is over a 15 symbol interval

(11)

which is a generalization of equation (6). The pulse g (t) need not be causal. This quantity 20 can be approximated with high accuracy by assuming that

(12)

where Nl is a sufficiently large number. This is the shortening

(13)

equivalent to.

We now define

(14)

30th

Using equation (10) and the fact that g (t) is defined to be causal and of duration LT, one obtains

(15)

35

Hence, the phase function can be written according to equation (3) as

(16)

40 where 0 (t, cu) and 0n correspond to the first and the last sum, respectively.

The Viterbi algorithm works recursively when using a metric to select the sequences that maximize the logarithmic probability function up to the nth symbol interval. A lattice is used to choose between the possible extensions of these sequences. This gridwork consists of a set of states, and a path through the gridwork should only correspond to a certain sequence of data symbols and vice versa. A lattice work is always obtained for rational values of the modulation index h = 2k / p, because in this case

(17)

55 finally many values, i.e. _p takes values. These values are called the phase states.

(17)

It also has the function

60

(18)

for each determined at most ML different values'.

We now define the set of states in latticework 65 by L times

(19)

The total number Ns of such states is

654 155

4th

(20)

It can be seen that the state space consists of the phase states and the L-1 preceding data symbols. The latter are called the correlative states.

In order to illustrate the above explanation, an example will now be given in which M = 2, i.e. the data symbols are ai, bipolar ± 1. As a pulse

(21)

selected, which is an increased cosine pulse over three bit intervals (L = 3), (3RC).

Finally, h = 1/2 (k = l) is chosen. This directly gives p = 4, and consequently 0n can only have the four values e.g. Assume 0, Jt / 2, n, 3 ti / 2. This also gives the possible states

(0, -1, -1) (7t / 2, -1, -1) (tc, -1, -1) (3TC / 2, -1, -1)

(0, -1.1) (TT / 2, -1.1) (TT, -1.1) (371/2, -1.1)

(0.1, -1) (7t / 2, l, -l) (7t, l, -l) (3jt / 2, l, -l)

(0.1.1) (71 / 2.1.1) (71.1.1) (371 / 2.1.1)

2, the so-called “phase tree” is plotted over five bit intervals. This phase tree simply represents all phase profiles <p (t, a.n), assuming the zero phase at t = 0 and the selection of preceding data symbols as a sequence with the values M-1. The phase tree should be modulo 27t, i.e. can be considered drawn on a cylinder.

Since at time t = 0 the phase is zero and the preceding data symbols are both +1, this state is designated by (0,1,1). Assuming the new data symbol is still +1 until time T, the correlative portion of the state is the same, but the phase curve is now ti / 2. The phase state is changed so that the state (7t / 2, 1,1) results. Assuming the new data symbol is -1, the correlative portion of the state has changed, while the phase state has been changed from zero to 7t / 2 (0, -1.1). It is easy to understand how the states are linked to the phase tree when looking at Figure 2 at t = 4T and 5T. As can be seen, the twelve phase values form groups around the phase states 0.7 t / 2 and 3 ti / 2. The positions within the groups are given by the previous history (correlation).

The number of phase values at the bit transition moments is twelve, while the number of states is sixteen. This is the case because four states are linked to two states. It can also be seen that there are four phase profiles that lead into these phase values and also four that lead away from them. This creates a crossing point. The lattice work according to FIG. 3 is easily derived from FIG. 2.

It was shown that the number of states in the latticework is Ns = p.ML_1. If b is equal to the number of bits per channel symbol, this means that Ns as

(22)

can be written there

(23)

is.

Table 1 shows the data calculated using the above equation. If b.L is given as the correlation time in bits, it is found that the number of states with increasing b (M) with fixed correlation time b.L and fixedj? decreases. Therefore, the number of states for M-ary schemes is smaller than that for binary schemes with the same correlation time.

For example, an octal 2RC scheme (M = 8, L = 2) has 32 states for p = 4. The correlation time for this system is six bits. A binary L = 6 scheme with 128 states has the same p. p = 4 corresponds to a higher average modulation index in an octal scheme than in a binary scheme. This means that in a binary scheme with p = 4 (h = 1/2) and an octal scheme with p = 16 (h = 1/8), which is the more appropriate, the number of states for a 6 bit correlation time is 128 for both schemes.

A normalized transmitted signal is s0 (ta.n)

(24)

The division of s0 (t, a.n) into quadrature components provides

(25)

wherein

(26)

From equations (3) and (16) one obtains

(27)

wherein

(28)

0n means the phase state and 0 (t, a.n) / nT <t <(n + l) T is the phase branch.

Fig. 1 shows a simple optic arrangement. In embodiments based on this arrangement, the problem arises of achieving an exactly rational relationship between the modulation index jh and the bit rate. An accumulated phase error occurs when the "sensitivity of the VCO" does not exactly match the bit rate. 4 avoids this problem, since in this case the I (t) and Q (t) generators are time-coordinated with a multiple of the bit rate.

The I (t) and Q (t) generators for a general M-poor system can be implemented in different ways. A solution leading directly to the goal is shown in FIG. 5. In this solution, all possible I (t) and Q (t) shapes are entered into memory over a symbol interval T and addressed by the states (a.n-i, 0n) and the present input information symbol. The phase states 0n are generated by a sequential device consisting of a phase state read only memory (ROM) and a delay of the length of a symbol interval T. At each symbol time, the data sequence a.n and the preceding phase state 0n-i determine the next phase state 0n. The phase state device is preferably constructed with phase state numbers vn instead of actual phase state values 0 ". These numbers vn are with the phase values 0n through the equation

(29)

linked in which \ | / 0 is an arbitrarily selected phase constant. In the following, y0 is chosen as zero.

The I (t) and Q (t) shapes are scanned by a counter Ç at the rate m.l / T, where m is the number of patterns stored per symbol interval T.

For example, the size of the I (t) read-only memory for M = 2, 3RC (L = 3), h = 0.5, m = 10 and 10-bit quantization is 3200 bits. In general, the I (t) read-only memory size is given by

(30)

where mq is the number of bits per pattern. The Q (t) read-only memory is of course the same size. The size s

io

15

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65

5

654 155

of the phase state read only memory is normally only small compared to Rs. The size is in bits

(31)

where [y] means the integer part of y.

The I (t) and Q (t) read-only memory size can be reduced by a factor p by reproducing I (t) and Q (t) as

(33)

One on the equations. (32), (33) based transmitter implementation is given in FIG. 6. For the p-fold read-only memory reduction, four multipliers and two small read-only memories cos (0n) and sin (0 „) of bit size p.mq are accepted.

Another, possibly better transmitter system is based on stored phase values instead of stored cosine and sine data. This system is shown in Fig. 7. The scheme avoids multipliers and double cos-sin read only memories, but adds a cos / sin converting read only memory at the end. The final read-only memory must be able to fold input information values ± (m-l) .h outside the normal ± n range.

The phase path read-only memory contains all possible phase values 0 (t, a.n). The sequential phase state device generates the successive phase state numbers vn. These numbers are converted into actual phase values 0n (t, a.n) in a small converting read-only memory. The phase values 0 (t, a.n) and 0 "are then added in a digital adder and converted into I (t) and Q (t) in a fairly small cos-sin read-only memory.

The total read-only memory size of this transmitter is sometimes smaller than that of previous transmitters. The main reason for this is that only one phase path read-only memory and one read-only memory converting phase states are required, instead of the two in each case in the transmitter according to FIG. 6. The read-only memory size saved in this case should be compared with the size of the converted output read-only memory.

Several authors have considered systems in which the modulation index h changes cyclically from symbol to symbol. It is easy to see that the general transmitter systems described above can be generalized by adding an “h state device” as additional address input information to the phase path and phase state memories.

The current phase branch is then determined by the data symbols 0Ln, the phase state 0 "and the present h-value h". The transitions in the phase state device are of course also dependent on the h value used.

In the past, the h-value was chosen as a rational number h = 2k / p, in which k and p are integers. With cyclically shifted hi, the values are selected from the rational numbers hi = '2ki / p. The number of states is multiplied by the number s | (K) of the ki values used. For example, if the two h values hi = 2/9 and I12 3 4/9 are used alternately for each - '. Of the other data symbol (K = 2),' the number of different branches in the recipient tree is twice: as large as that of the corresponding fixed h-system. io; In general, the number of states can be i

(34)

to be written.

As soon as the receiver has synchronized the cyclic h-sequence 15, the number of possible lattice nodes will be reduced to the normal p.ML_1 at every test interval. This happens thanks to the fact that if the h-value is known, only the normal recipient uncertainty, determined by the data sequence, has to be solved. Consequently, the number of real states in the receiver lattice work for multi-h code and the fixed h-system considered in the foregoing are the same.

In a more general system, in which the h values are not cyclically shifted from the data sequence a.n, the h states are real states.

A schematic transmitter system is shown in FIG. 8. Note that cos, sin read only memory address input information comes from the phase state device of the “h state device” and the data symbols a.n. Note also that for multi-h systems, the h values are generated by a degenerate state device without data dependency. The transmitter in Fig. 8 is based on that in Fig. 5. The transmitters in Figs. 6 and 7 can of course also be easily changed to multi-h transmitters. Only the "h-state device" with additional address inputs has to be added to the read-only memories.

Table 2 shows an example of the phase state read-only memory content for a binary system with a pulse length of L = 2. The pulse is an increased cosine. The phase tree is shown in Fig. 9. The phase numbers vn in Table 2 are converted to phase values (0n) or cos (0n) and sin (0 ") in the same table.

The phase branches are shown in FIG. 10. Table 3 shows the phase state read-only memory contents for a 2RC pulse with h = 2/3.

45 Figure 11 and Table 4 represent the same data for an SRC system; see Fig. 2.

In Table 4 we note that the alternative v "can be generated by a simple state device consisting of an up and down counter controlled by an-i. 50 The phase branches in Fig. 11 are not the same for the alternative definition of v ". These phase branches are shown in FIG. 12. Notice the symmetry between the branches. This symmetry can be used for read-only memory savings if desired.

FORMULA LIST FOR PATENT REQUEST NO. 1050 / 81-0 - ERICSSON (1) 5n • "a-2 ° -1 ®o a1 ° n-1 ° n

(2)

ift.a ^ * cosf2nfQt ♦ ♦ (PQ); nT <t ± tn + 1) t t n

(3) <p (t, a) - 2vh S Z a. gCr-iDck i nT <. t <. (n * 1) T

—1 = - «o

654 155

6

(4)

gCtJ $ 0; 0 <.t <.LT gît) s 0; t <0, t> LT

(5) (pttn + DT, ^) - «pfnT.c ^ î

(n + 1) T n «2irh / £

- i—

(n + 1) T n «2 * h / r nT i« -

nT n a- g (T-iT] dT - 2wh / Z

1 .m

- 1"

a. gCT-îT) dr a- g (x-iT) dT

n (n * 1-i] T

(6) <pC (n + 1) T, a) - <p (nT, a) »2irh I <f- / gfaïda

• Ti "" TI • X / «« «.

i "-" (n-i) T

T 2T

«2wh [an / gCaDda + an-1 / gCaldcr

LT

t / gfa) da]

n "L * 1 tL-DT

CL-i + DT

(7) / gCa) da> 0 i = 0.1, ..., L-.1 (L-i) T ""

L-1 (i + 1) T LT

(8) 2ïh (M-1) E / g (a) da «2 * h (M-1) f g (a) dcr i = 0 iT o

LT

(9j 2sh (M-1) / g (a) dor «(M-1) hir o

LT 1

(10) / gCaîda = y o

(11)

2sh r

I »-«

n-i

(i + 1) T

/ gCcrîda iT

(i + 1) T

(12) f g (ff) da »0; .

iT

i «N ^ .N ^ + 1, ... i« -Nl-1, -Nl-2,

(13)

gCt] = 0; [t | > Nl-T

(14)

q (t) «r g (x) dx

(15)

q (t)

1

7

t <_ 0 t> LT

(16)

(17)

<p (t, a) ■ 2irh Z a- q (t-iT) i «-«. 1

n n-L

2 * h Z a. q (t-iT) ♦ hir Z o. i-n-L + 1 1 i «- a

0R "fhWi« î. Ai1mod-2ir

(18) 0 (t'on, on-1 "** 'an-L + 1)" 2, rh r o.-q (t-iT)

i = n-L + 1 1

~ n * C0n'an-1'an-2 '"" an-L + 13

(19)

(20)

N ■ p * M s

L-1

(21) g (t)

f °

i t <0, t> 3T

(1-cos 1 ^ 5; 0 t ± 3T

(22) Ns - p.2b * L "1-2" Cb "1î

(23)

M = 2

(24) s (t, a) «cas (bi t-npft.a)) o —n o —n

(25) s £ j (t, ctn) «I (t) * cos (uQt) - Q (t) -sinfi ^ tl

(26)

lit) «cos {ip (t.a)} —n

Often) »sin {<p (t, a)} —n

(27) «pft.a) = ect.oj + e„ —n —n n

654 155

n

(28) 0 (t, O - 2irh- I a.-q (t-iT)

i = n-L + 1 1

(29)

6 ■ (hwv ♦ <{») mod (2v) n n To

(30) Rg «Pl-Ng-m-m ^

(32.) R «[1 + 2log (p-t)] '2n-" b + [1+ loB (P "1 ^ 3

55

(32) I (t) »cos (0Ct.n ^) * e)

"Cos (e (t, a))" cos (e ") - sin (0 (t.a))" sinfs) —n n -m n

(33) Q (t) «sin (0 (t # an) -» 0n)

«Cos (0 (t, a)) • sinfe) ♦ sin (0 (t.a)) ^ cos (e) —n n —n n

30th

Table 1 Table 1 (continued)

Number of states Number of states

M 35 M

2 4 8 16 32

1

p = l

1

1

1

1

8th

64

2nd

P-2

2nd

2nd

2nd

2nd

16

128

3rd

p = 3

3rd

3rd

3rd

3rd

40

24th

192

1

4th

p = 4

4th

4th

4th

4th

A

32

256

5

p = 5

5

5

5

5

H

40

320

6

p = 6

6

6

6

6

48

384

7

p = 7

7

7

7

7

56

448

8th

p = 8

8th

8th

8th

8th

45

64

512

2nd

4th

8th

16

32

16

4th

8th

16

32

64

32

6

12

24th

48

96

48

O

8th

16

32

64

128

50

5

64

e.g.

10th

20th

40

80

160

80

12

24th

48

96

192

96

14

28

56

112

224

112

16

32

. 64

128

256

128

4th

16

64

256

1024

ii

32

8th

32

128

512

2048

64

12

48

192

768

3072

96

■ 2

16

64

256

1024

4096

p.

128

i

20th

80

320

1280

5120

60

O

160

24th

96

384

1536

6144

192

28

112

448

1792

7168

224

32

128

512

2048

8192

256

65

7

64 128 192 256

9

654 155

Plate 2

Table 3

Phase state read-only memory contents for a 2RC pulse. L = 2, M = 2, h = 1/2

Phase status read-only memory contents for a 2RC system with h = 2/3, L = 2, M = 2

Vn-1

Otn-l

Cln

Vn en cos (0n)

sin (en)

0

0

0

3rd

3 / 2rc

0

-1

0

0

1

0

0

1

0

0

1

0

0

0

1

0

0

1

1

1

71/2

0

1

1

0

0

0

0

1

0

1

0

1

1

7C / 2

0

1

1

1

0

1

71/2

0

1

1

1

1

2nd

7t

-1

0

2nd

0

0

1

n / 2 "

0

1

2nd

0

1

2 '

7t

-1

0

2nd

1

0

2nd

7t

-1

0

2nd

1

1

3rd

371/2

0

-1

3rd

0

0

2nd

7t

-1

0

3rd

0

1

3rd

3? T / 2

0

-1

3rd

1

0

3rd

3TI / 2

0

-1

3rd

1

1

0

0

1

0

Vn-l

Ctn-l a "

Vn

0n cos (0n)

sin (0n)

0

0

0

2nd

4TI / 3

-1/2

-1/3/2

0

0

1

0

0

1

0

0

1

0

0

0

1

0

0

1

1

1

27t / 3

-1/2

1/3/2.

1

0

0

0

0

1

0

1

0

1

1

2TI / 3

-1/2

1/3/2

1

1

0

1

27t / 3

-1/2

1/3/2

1

1

1

2nd

47t / 3

-1/2

-1/3/2

2nd

0

0

1

2TI / 3

-1/2

I / 3/2

2nd

0

1

2nd

4TI / 3

-1/2

-I / 3/2

2nd

1

0

2nd

4TC / 3

-1/2

-I / 3/2

2nd

1

1

0

0

1

0

Addresses

Read-only memory contents

654 155

10th

Table 4

Phase state read-only memory contents for a 3RC system with h = 1/2, L = 3, M = 2. That through the

7t

Phase state 0 phase interval shown is defined as 0 <q> <-; see Fig. 2. For the alternative vn

2 7t 7t the phase interval represented by phase state 0 is defined as - <(p <-.

2 4

Alternative definition of

Vn-r

O-n-2

an-l

«N vn

0n cos (0 „)

sin (0 ")

vn and 0n

0

0

0

0

3rd

3ti / 2

0 ■

-1

3rd

3n / 2

0

0

0

1

3rd

3ti / 2

0

-1

3rd

"in 2

0

0

1

0

0

0

1

0

1

n / 2

0

0

1

1

1

jt / 2

0

1'

1

n / 2

• 0

1

0

0

0

0

1

0

3rd

3n / 2

. 0

1

0

1

0

0

1

0

3rd

3n / 2

0

1

1

0

0

0

1

0

1

n / 2

0

1

1

1

1

71/2

0

1

1

■ n / 2

1

0

0

0

0

0

1

0

0

0

1

0

0

1

0

0

1

0

0

0

1

0

1

0

1

7t / 2

0

1

2nd

7t

1

0

1

1

2nd

n

-1

0

2nd

7t

1

1

0

0

1

n / 2

0

1

0

0

1

1

0

1

1

.n / 2

0

1

0

0

1

. 1

1

0

1

n / 2

0

1

2nd

7t

1

1

1

1

2nd

n

-1

0

2nd

7t

2nd

0

0

0

1

n / 2

, 0

1

1

n / 2

2nd

0

0

1

1

n / 2

0

1

1

n / 2

2nd

0

1

0

2nd

n

-1

0

3rd

3n / 2

2nd

0

1

1

3rd

3.71 / 2

0

-1

3rd

3n / 2

2nd

1

0

0

2nd

7t

-1

0

1

n / 2

2nd

1

0

1

2nd

7t

-1

0

1

n / 2

2nd

. 1

1

0

2nd

7t

-1

0

3rd

371/2

2nd

1

1

1

3rd

37t / 2

0

-1

3rd

, 3ti / 2

3rd

0

0

0

2nd

7t

-1

0

2nd

7t

3rd

0

0

1

2nd

7t

-1

0

2nd

7t

3rd

0

1

0

3rd

3? T / 2

0

-1

0

0

3rd

0

1

1

0

0

1

0

0

0

3 •

1

0

0

3rd

37t / 2

0

-1

2nd

7t

3rd

1

0

1

3rd

3TI / 2

0

-1

2nd

7t

3rd

1

1

0

3rd

3TI / 2

0

-1

0

0

3rd

1

1

1

0

0

1

0

0

0

5 sheets of drawings

Claims (3)

654 155 2nd PATENT CLAIMS lv converter in a modulator for the phase modulation of data symbols, each of which is received during a time interval and converted into a sequence of phase values by means of a memory arrangement (MA), characterized by a computing device (CU) for calculating a defined phase state from a finite number of Phase states during each time interval, which defined phase state is associated with a first number of previously received symbols and which defines a phase state number, and an access device (ROM) contained in the memory arrangement (MA) for reading out the phase values in succession in digital form by means of an address, which is determined by the current symbol, by a second number of previously received symbols and by the current phase status number obtained from the computing device (CU). 2. Converter according to claim 1, characterized in that the input of the computing device is connected to the output of the memory arrangement and, by means of the phase value obtained at the end of each time interval, calculates that phase status number which is used by the access device during the subsequent time interval. 3. Converter according to claim 1, characterized in that the computing device (CU) consists of a sequential device which calculates the current phase state number from the current symbol, from said second number of previously received symbols and from the preceding phase state number. *