CA1081848A - Multi-line, multi-mode modulator using bandwidth reduction for digital fsk and dpsk modulation - Google Patents

Abstract

MULTI-LINE, MULTI-MODE MODULATOR USING BANDWIDTH
REDUCTION FOR DIGITAL FSK AND DPSK MODULATION
Abstract A multi-line multi-mode modulator uses compatible digital modulation techniques for multifrequency (MF), frequency shift keyed (FSK) and differential phase shift keyed (DPSK) modulation to achieve a multi-line multi-mode modulator which is capable of handling a plurality of lines requiring a dynamic mix of the three modulation techniques. The compatible modulation techniques utilize bandwidth reduction schemes which enable the use of simple RC fil-ters on each output line for the sole purpose of removing the quantizing noise introduced by the digital modulation technique.

Description

Field of the Invention The invention relates to modulators in general and more parti-cularly to novel modulators which directly provide a reduced band-width modulated signal and to a multi-line multi-mode modulator capable of simultaneously, on a time shared basis, modulating mutli-frequency, frequency shift keyed and differential phase shift keyed signals from a plurality of sources for transmission over a plurality of lines.
Summary of the lnvention The invention is directed to novel digital FSK and DPSK
modulators which are compatible with each other and which produce at their output modulated signals in which out of band energy is reduced thus eliminating the need of any filtering except for simple RC filters for removing quantizing Qoise introduced by the digital modulation used. These modulators are combined in a novel multi-line Inulti-mode modulator which is capable of dynamically providing a wide variety of signal modulations on a large number of lines ~Jith a substantial reduction of equipment and cost.
!

.:

~ '' .

:
~' .` : ' ~ ' 1081848 :

1 Brief Description o~ the Drawings

2 Flg. l is a schematic dlagram of a prlor art digital FSK

3 modulator;

4 Figs. lA, lB and lC are graphs illustrating the signals present at several polnts ln the circuit of Fig. l;
6 Fig. 2 is a schematic diagram of a novel FSK modulator 7 according to the invention;
8 Flg. 2A is a graph for illustrating the operation of the 9 modulator illustrated in Fig. 2;
Fig. 3 is a table showing the relationship between the 11 selectlon signals applied to the address generator of Fig. 2 12 and the read only memory contents;
13 Fig. 4 is a schematic diagram of a novel DPSK modulator 14 according to the invention;
Figs. 4A, 4B and 4C are graphs for illustrating the 16 operation of the modulator shown in Fig. 4;
17 Fig. 5 is a table showing the relatlonship between the 18 selectlon slgnals applled to the address generator of Fig. 4 19 and the read only memory contents;
Flg. 6 is a schematlc dlagram of a multifrequency 21 modulator constructed in accordance with the prlor art;
22 Fig. 7 is a table showing the relationshlp between 23 the selectlon slgnals applled to the address generator of Fig. 6 24 and the read only memory contents;
, 25 Flg. 8 is a block diagram of a novel multlline ; 26 multimode modulator const~ucted in accordance with the 27 invention;
28 Flg. 9 ls a schematic diagram, in greater detail, of 29 the clock and line control word memory unit illustrated ln Fig. 8; and , ; RA9-74-002 ., .
; . ' ~
. " . . . ~ .

1 Fiy. 10 is a schematic block diagram of the novel modulator illustrated in Fig. 8. ~ ~-Description of the Prior Art ; :
A technique in current use permits the digital synthesis of a sinusoidal wave by directly computin~ phase angle and performing -a phase to amplitude translation by means of a table look-up of ~ -previously computed digital values. The digital values may then be ¦~
converted to analog form by conventional digital to analog conversion !;
techniques. This general digital technique of tone synthesis has been specifically applied to digitally implemented frequency and phase ¦
shift keyed modulators. Such a prior art frequency shift keyed modulator is illustrated in Fig. 1. In Fig. 1, a memory 11 con-tains two values ~ 00 and ~01. These digital values represent increments of phase of two waves sinO0 and sinOl used to represent in analog form the binary 0 and 1 data. The input data is applied to l;
a controller 12 which, selects, via a switch 14, 400 or ~01 de-pending on the input data applied. This is shown in Fig. lA for a serial input data pdttérn of (010).
The selected value of ~0 is applied via a gate 15, under con- , 1 20 trol of a clock 16 at a frequency fs, to one input of an adder 17 !~- , 3 which adds this value to the contents of a buffer 1~3 which is con-nected to the output of adder 17. The output of adder 17 is illustrated in Fig. lB. The output of adder 17 is applied to a read only memory j,,i, 19 which accepts the digital phase of O(t) and by table-look up pro-vides a digital amplitude signal sin O(t). This signal is applied to a digital to analog converter 20 which supplies a signal to a filter 21 (Fig. lC).
The filter 21 is, of necessity, a complex filter since the signal from the modulator includes significant out of band energy introduced by the step-like frequency shifts. In addition, the ~i , characteristics of filter 21 must be modified to take into account ,~ thç specific frequencies used to transmit the binary 1 and 0 values ,;
h RA9-74-002 -3-. :
' " ' .
. ^ ,, .

-1 and the rate of transmission. Thus, a different filter must be provided for each type or modulator implemented. Similar digital ~`
techniques may be used for both multifre4uency (~lF) and differential phase shift keyed (DPSK) modulation.
; A modulation technique similar to that illustrated in Fig. 1is utilized in the time shared multiline FSK modulator disclosed in L
U.S. Patent 3,697,892 to Lawrence et al which provides a specific type of FSK modulation for d set of lines. The multiline time-shared modulator, however, requires separate digital to analog con-verters for each line and a band pass filter for each line capable of eliminating undesired out of band frequency components generated in the modulation process. Because of these requirements, the multiline modulator is incapable of handling a wide variety of modulation techniques which may be used for any of the output lines.
~his is so because of the specific requirements for the individual output line band pass filters. In the patented device, each out-put line must, of necessity, be l;mited to one type of modulation.
If it is desired to change the modulation characteristics for a given line, it becomes necessary to alter the characteristics of the connected band pass filter. This requirement severely limits the usefulness of the multiline modulator since the lines cannot be dynamically allocated to different modulation techniques.

~.

t~

~0~848 ~
: .
l DescriPtion of the Preferred Embodiment Fig. l described in detail above illustrates the applicatlon of dlgltal tone synthesls technlques in an FSK modulator. A dlgital value of phase ~(t) is accumulated and updated each processing cycle determined by fs where fs is the sampling rate of the resulting modulated digital line signal. The amount by which the phase is incremented each sample time, ~, determines the slope of ~(t)and hence the lnstantaneous frequency of the sine wave generated.
For binary FSK, one of two values of phase increment ~0 and ~1 are selected depending on the data whlch ls to be transmltted. The frequency of the sine wave being generated ls directly proportional to the value of ~ and ~(t) are both digltal signals and the accumulation is performed wlth conventlonal arlthmetlc components. The dlgital phase slgnal ls scaled such that arithmetlc overflow of the accumulator or buffer 18 corresponds to the normal ! modulo 360 property Or the trignometrlc sine function. ~ :
~ . .
The digital representatlon of phase ~t is translated to a digital representation of sin ~t)by means of the read only memory 19. The resulting digital amplitude signal ls converted to analog by conventlonal digital to analog converslon technlques and subsequent analog fllterlng. The quantizing noise resulting from the converslon from digital to analog is removed by the analog filtering along with other unwanted frequency components introduced by the modulating technique, In the FSK modulator illustrated in Flg. l, as well ,~ .

.~ .
,.
~! RA9-74-002 -5-'` ' ' ' '' 1 as in other conventional FSK modulators implemented with 2 either analog or digital circuits, the instantaneous frequency 3 of the transmltted signal ls abruptly sw~ched between two 4 values ln the course of being modulated by the input data slgnal. The abrupt transitlon in frequency causes an increase 6 ln the bandwidth of the transmitted signal over that actually 7 required to communicate the data by the FM modulation 8 process. When FSK data transmission over telephone channels 9 is required, it is necessary to reduce the excessive bandwidth generated in two signlficant appllcation areas. One ln high 11 speed FSK, 1200 to 1800 bits per second transmission, band~idth 12 reduction is necessary to comply with out of band signal 13 regulations imposed by various regulatory agencies and 14 two in full duplex transmission using a single physical channel, the received signal can, in many instances, be 16 significantly smaller in amplitude than the local transmitted 17 signal and the two frequency bands occupied by the two signals 18 may be relatlvely close. Thls requires that the bandwidth of 19 the transmitted signal be sharply reduced in order to prevent i 20 interference with the received signal.
21 Classically, FSK bandwidth reduction has been attained 22 through band pass filtering of the transmitted signal. Some 23 modulators have used premodulation filtering of the data signal;
24 h~wever, this approach has had limited application since it requires a linear FM modulator. Either of the above approaches 26 for reduclng unwanted slgnals introduced in the modulatlon process 27 has a drawback ln a digital implementation of the modulator since 28 the arithmetic requirements of a dlgital fllter greatly increase 1~ 29 the functional complexity of the unit. For this reason, some ;1` 30 digltal modulators have used rather complex analog fllters in 31 their lmplementation.

.`~ ' 1 A significant reduction in bandwidth can be achieved by 2 ellmlnatlng the abrupt frequency transltlons normally present 3 in FSK modulatlon Or blnary data. Thls ~an be done by having 4 the instantaneous frequency make a smooth or continuous transitlon ln changing from one value to another. Thls 6 is pointed out by Bettinger in "Dlgltal Transmisslon for 7 Moblle Radio", Electrlcal Communlcatlons, Vol. 47, No. 4, 8 1972 at page 225. Such an approach has been lmplemented 9 by the use of a premodulatlon filter, as noted earlier, or by the applicatlon of a control slgnal or voltage to 11 a linear modulator. This approach while producing a 12 desirable result is not flexlble in many uses and limlts 13 the utillty of the modulator to a slngle baud rate and set 14 Or frequencies.
In a dlgital FSK modulator constructed according to the 16 inventlon, a smooth transltlon ln frequency is accompllshed 17 by storlng in memory dlgltal values whlch represent a 18 predetermined tra~ectory for the instantaneous frequency to 19 follow and selectlng these values based on the interbaud tlme or time since the last data transition. Such an approach 21 is viable only in a digital FSK modulator where the phase 22 and rate of phase change can be accurately specified.
.
23 The traJectory followed as the frequency is slewed from 24 one value to another is selected to minimize the bandwidth of the modulated signal. Both the shape and the number 26 of intermediate points in the tra~ectory, per blt time, 27 are important parameters in this regard. Analysis and ll ~o experiment has shown that a sinusoldal traJectory with ~, 29 . eight points specified in time over the data hit glve the 3 best performance in terms of minimum transmit signal .
~` RA9-74-002 7 . .

., .

, . , : . . ... .. ... .

~08~848 1 bandwidth and minimum loss in receiver detectability.
2 This does not, however, imply that an eight point sine 3 wave tra~ectory is optimum in general. When this technique 4 is lmplemented as shown in the modulator illustrated in Flg. 2, out of band signallng ls reduced to the point where 6 output filtering is no longer required and the sole filtering 7 requirement is that necessitated by the digital modulation 8 technique employed, that is, the removal of the quantizing g noise. This may be accomplished by a simple RC filter.
The modulator illustrated in Flg. 2 is capable of 11 providing the FSK modulatlon for a single line of a number 12 of different types or frequencies of FSK modulation. It l 13 requires binary input data anq a line control word signal ,~ 14 which in the illustrated embodiment is a slngle line :i designating elther one type of FSK modulator or another.

16 If the one type is designated, the line wlll be at a voltage ~j 17 level indlcating the binary 0 and if the other type is indicated, 18 the line voltage will be at a voltage indicating a blnary 1.

I 19 Thls, of course, could be expanded by providing additional lines for designating the line control word. In addition, 21 the clock generator 30 operating at a frequency fs provides 22 two clock phase signals Cl and C2. These are illustrated 23 graphlcally ln the flgure and are 180 out of phase wlth each 24 other. The data signals, the line control word and the two clock slgnals are applled to an address generator 31. The 1 26 address generator 31 also recelves slgnals from three conductors ;i 27 32A, 32B and 32C. These 3 conductors represent the three hlgh ;~ 28 order blts from a buffer register 32, the functlon of which will `J 29. be described later on. Based on the inputs descrlbed above, address generator 31 logically derives an address which is 1 applied to a read only memory 33 to access during one-half 2 of the clock cycle fs, a value ~l and during the other half 3 of the clock period fs, the value 4 The contents of memory 33 are set out ln the table of Flg. ~. This table ls dlvided lnto two sections. It shows 6 memory address i - i+9 which are associated with line control 7 word 0 for one type Or FSK modulator and memory addresses ~ -8 J+9 which are associated wlth line control word 1, another 9 type of FSK modulator. Obviously, if additional types of FSK
modulators are to be lmplemented, addltlonal sections of memory 11 would be necessary as well as additional lines for the llne 12 control word to distinguish the varlous FSK modulators being 13 implemented. The conditions of the selection signals are 14 indicated in the rlghthand columns of the table underneath the headings "Llne Control Word, Data, T~ cl and c2. During 16 the first half of the clock cycle fs, that is, when cl and c2 ~ 17 are 1, 0 respectively, the contents of addresses i and i+l or j 18 ~ and ~+1 depending on the line control word, will be selected 1 19 if the three high order bits from buffer 32 are all zeroes 1 20 or all ones and the data blt ls O or 1, respectively, the 21 contents from address i+l or ~+1, namely, all zeroes wlll 22 be provided at the output of thé read only memory during 23 that particular fs clock cycle. If the contents of the three 24 high order bits and the data bits are any other value, the ¦~ 25 contents of address i or ~ depending on the line control 26 word will be selected. In this case, this value is an increment 27 dividing thé bit period T into eight different values to 28 provide as shown in Fig. 2A, eight different values of 29. ~ over a slngle bit period for causing the frequency of the output of the modulator to change values smoothly or .

:, .. . . . ..

~8~848 1 sinusoidally as discussed above. For example, if the sampling 2 frequency fs of 18,000 cycles per second ls selected, this 3 would yield 30 samples per bit for a 600'bit per second line.
4 Thus, a value of 120 for t/8 will provide eight substantially ` 5 equal steps if the three high order bits of a 12 bit 6 positlon register are examined. Therefore, the numerical 7 value 120 will be stored in binary form in memory address i ' 8 to implement a FSK modulation for a 600 bit per secon,d data g rate. Durlng the first half of each cycle fs, this value under the conditions described above, that is, data not 11 zero and the three high order bits from buffer 32 not all 12 zero or data not one and the three high order bits from buffer 13 32 not all ones, will be added or subtracted to modify the '' 14 contents of register 36. How this is accomplished will become , l apparent as the descriptlon of the circult shown in Fig. 2 16 contlnues.
~, 17 Durlng the second half cycle of clock fs, that is, Cl(0) '~ 18 and C2(1), the values ~1 through ~8 residing in address 19 locations i+2 through i+9 wlll be added ln a manner simllar 20 to that lllustrated ln Flg. 1 and described below to thus 21 generate the actual output frequencles from the modulator.
¦ 22 The form of the values ~1 through ~3 ls illustrated '~ '' 23 in the graph shown in Fig. 2A. These values are selected 24 to provide a smooth transltion from the one frequency to '~
~, 25 the other. '~' 26 The contents, under the conditions described above, from , 27 read only memory 33 are applied to one input of an adder circuit ~
28 34. The output of the adder circuit is selectively applied ~ , 29 under control of clock 30 and a read write memory control circuit 35 to one of two registers 36 and 37. During the first half ;; .

~ RA9-74-002 -10- - ~

. . .

~08~848 .
1 o~ the clock period fs, the output of adder c~rcuit 34 is 2 inserted in register 36 under control of read write memory 3 control circuit 35 and during the second half of the clock 4 fs, the output o~ adder circuit 34 is lnserted in register 37.
Likewise, the contents of reglster 36 are added in adder 34 6 during the first half of the clock cycle from clock 30 with 7 the output of read only memory 33 and during the second half 8 cycle of clock 30, the contents of register 37 are added in 9 adder 34 wlth the output from read only memory 33. The addition and readback occur under control Or read,wrlte memory control 11 circult 35 at different portions of the output from clock 12 circult 30. Thus, during the flrst portlon of each of the 13 clock cycles, the contents of the reglsters 36 and 37 are 14 added to the output of memory 33 by adder 34. After the addltlon takes place the sum of thls addltlon ls lnserted lnto the 16 reglsters 36 and 37., Read wrlte memory control clrcult 35 may 17 take many forms as ls well known in the prior art for controlllng 18 reading lnto and out of memory devlces and is not shown ln 19 ~reater detall here slnce lt ls well known in the prior art.
The contents of register 36 under control of the clock 30 21 Cl output are transferred to buffer 32 and the three hlgh order 22 blts of thls reglster whlch may, for example, contain 12 bit 23 posltlons are applled vla conductors 32A, 32B and 32C to the 24 address generator 31 and are used as described above for generating the addres~ wlthln read only memory 33 of the 26 data which must be applied during each clock cycle to 27 adder 34.
28 An adder control clrcuit 38 responds to the output of 29 clock 30 and the data input to control the function of adder 3 34; that ls, whether an addltion or subtraction takes place.
31 During the first half of the clock period of clock 30, an .

1 addition or subtraction will take place depending upon the 2 direction of change of the data. If the data changes from 3 a 1 value to a O value, the contents of reglster 36 must be 4 decremented and lf the data changes from a O to a 1, the contents of register 36 must be lncremented. Adder control 6 38 includes an AND circult 39 havlng one input connected to 7 the data line and another input connected to the Cl output 8 of the clock 30. The output of AND circult 39 is connected 9 via an OR clrcuit 40 to a control input of adder 34. When the data is 1 and durlng the first half of the clock period 11 of clock 30, AND clrcult 39 provldes an output vla 12 OR clrcult 40 which causes the adder to increment or add.
13 When the data is zero, the output of AND gate 39 is down 14 and this signal level causes adder clrcult 34 to decrement.
The speclflc lmplementation of thls control ls well known ln 16 the art and ls not further descrlbed here. During the second 17 half of clock 30, the C2 output ls connected vla OR clrcuit 40 18 to the control input of adder 34 and causes the adder to 19 lncrement durlng thls second half of the clock perlod. Buffer ~-32 ls loaded under control of the Cl output of clock 30, thus, 21 after the contents of reglster 36 have been modlfied as 22 descrlbed above, the new value calculated ls loaded into 23 buffer 32 where lt will be available for the next cycle of 24 clock 30 during the next sampllng period.
The output of adder 34 is applied to a 9 to sine 3 26 conversion circult 41 whlch may be a read only memory loaded wlth 27 precomputed values of sine ~ to perform the converslon.
28 Such devices are well known in the prior art and readlly 29 available and are lllustrated throughout this speclflcatlon in block form only. The output of ~ to slne ~ converter 41 31 is applied to a register 42. Register 42 ls strobed under . ' _ ~ , .
., ~ ~ . . . . . ~ .

~081848 1 control Or the C2 clock from clock generator circuit 30 and the contents applied at that time to a conventional digital to 3 analog converter 43. The output of digital to analog 4 converter 43 pulses a simple RC filter 44 which is deslgned solely to remove the quantlzlng nolse introduced by modulatlon 6 process. It ls obvious from the above description that the 7 modulator may be changed from any group of frequencies to some 8 other group of frequencles slmply by changlng the line control g word and storing the appropriate values for that group ln the read only memory 33 since the fllter 44 ls the same for 11 all values, lt need not be changed or swltchable.
12 The baslc processlng tlme ln Flg. 2 ls dlvlded lnto 13 two parts, Cl and C2. Durlng Cl tlme, a runnlng accumulatlon 14 of bit tlme is calculated. Durlng C2 time, a phase accumulatlon is calculated as ls done ln the conventional dlgital modulator 16 lllustrated ln Flg. 1, wlth the exceptlon that the values of 17 ~ are selected from memory on the basls of the blt tlme T
18 from reglster 32. If a data transltlon occurs, during 19 Cl tlme, numerlcal value whlch at the sampllng rate will provide elght substantlally equal detectably dlfferent outputs 21 from reglster 32 ls selected from the ~T memory and 22 added or subtracted dependlng on the data lnput. The 23 baud tlme accumulatlon ls made sharing the same adder 34 as 24 ls used for the phase accumulatlon. The dlgltal value of baud tlme ls prevented from underunnlng, that ls, golng 26 below the all zero state when QT1S subtracted or overrunnlng, 27 that ls, going above the all one state when ~T iS added.
28 This is accomplished by the all zero condltlon stored ln 29 memory locatlon 1+1 or J+l slnce addlng or subtracting all zeroes to any number does not change lt. Thls memory .
.J

.
.' . , .
', ' ' ' , :.

!
10818*~

1 address ls selected on the basis of the conditions shown 2 in the table Or Flg. 3, namely, data 1 and lall one or data 0 and 3 T all zero. In both of these conditlons. an under or over 4 run could occur. Therefore, the zero value is added to the value of T contalned ln reglster 36 durlng each processlng 6 cycle. Wlth this control, the baud tlme value changes from 7 an all zero state to an all one state ln elght equal steps 8 spannlng the complete blt tlme when the data changes from 9 a 0 to a 1. Thereafter, the baud tlme remalns at the all one state untll the data changes back to zero. At whlch 11 tlme, ~T iS subtracted and ~ ls permltted to increment 12 to the all zero state.
13 At the end Or Cl tlme, the hlghest three blts of T . .
14 are transferred to reglster 32 and used to address the ~
memory durlng C2 tlme. The three hlghest bits of T select 16 one Or the 8 values Or ~ to be accumulated as T traverses 17 from one data state to the other. As lndlcated ln Fig. 2A, 18 the values Or ~ addressed by T produce a smooth or 19 slnusoldal traJectory ln the lnstantaneous frequency of the transmltted slgnal. The phase accumulatlon, phase to slne 21 conversion, and dlgital to analog conversion are performed ln 22 the same manner as for the conventlonal modulator lllustrated 23 ln Flg. 1.
24 Flg. 4 ls a schematlc dlagram of a dlrferentlal phase shlft keyed modulator compatible ln lmplementation with the FSK modulator 26 described above wlth respect to Flg. 2. The lmplementation 27 ln Flg. 4 provldes a narrow band modulatlon ln whlch the 28 generated transmit signal spectra are sufflclently narrow 29 as not to require subsequent fllterlng for transmlsslon 3 over telephone llnes or slmllar transmlsslon medla. The .

, : . ~ . . , , . , ~ ... . .

1 only requlrement being a simple RC filter to remove the 2 quantizing noise associated with the dlgital generatlon of 3 the signals and conversion to analog form.
4 The implementatlon of the DPSK modulator illustrated in , 5 Fig. 4 iB structurally similar to the ~SK modulator lllustrated , 6 in Fig. 2. Slnce the two modulation techniques are compatlble , 7 wlth each other, the maJor dlfferences are ln the nature ,, 8 of the slgnals stored ln the read only memory. In view of , 9 this similarity, the reference numerals used in Flg. 2 will ,~ 10 be used in part in connection with the descriptlon of this 11 flgure. In the DPSK modulator, the clock 30-1 operating at l 12 a sampling frequency fs provldes five outputs during each sampllng ,l 13 tlme. These outputs are lllustrated graphlcally in the flgure.
~¦ 14 The flrst output Cl occurs during the first quarter of the ¦ 15 perlod of clock 30. The second output C2 occurs during the : . ~.
16 second quarter, the thlrd output C3 occurs during the third 17 quarter and the fourth and fifth outputs occur during the ,~, 18 fourth quarter. The fourth output C4 occupying the first ¦ 19 half of the fourth quarter and the fifth output, C5, occupying 1 20 the last half of the fourth quarter. The clock outputs Cl-C5 ¦ 21 are applied to the address generator 31-1 along with the 22 three high order bits from the T buffer 32-1. The line control 23 word and one of the two simultaneously provided data bits for 24 a four phase DPSK modulation. The modulation contemplated in 25 this modulator is a conventional four-phase DPSK modulation , 26 in which two bits of a binary digital signal are simultaneously ' ~J 27 encoded. The first bit D0 defining the sign of the differential ' ~ phase change and the second bit Dl deflning the magnitude of the ',l 29 ' change. In this modulator, the magnitude bit is applied to 1 30 address generato,r 31 for selecting along with the other inputs ,, .

;I RA9-74-002 -15-, I .

108184~

1 the appropriate address within the memory 33-1.
2 The output of address generator 31-1 selects an address 3 durlng each of the five processing cycles of clock period 30-1 4 and reads the data stored ln that address from the read only memory 33-1. This data 1B applied to one input of an adder ; 6 34-1. Two feedback reglster 36-1 and 37-1 slmilar to the 7 registers 36 and 37 of Fig. 2 are connected from the output of 8 the adder 34-1 to the other input of the adder 34-1 and selectively 9 entered therein by the clock slgnals from clock generator 30-1 whlch are applied to a read wrlte control clrcult 35~
11 The contents of reglster 36-1 are applled to adder 34-1 durlng 12 clock tlme Cl and added to the contents supplled from read only ¦ 13 memory 33-1 then relnserted lnto reglster 36-1. At the end of 14 thls clock perlod, the contents of reglster 36-1 are also lnserted lnto buffer 32-l and are used as prevlously described , 16 for generatlng the address ln address generator 31-1 along 17 wlth the other lnputs applled thereto. How these partlcular 18 lnp~ts access speclflc data in the memory will be dèscribed 19 later ln connectlon wlth the descrlptlon of Flg. 5 whlch 20 lncludes a table of the memory anA the selection slgnals.
21 Durlng the second clock period, C2, the contents of register 22 37-1 are added to the data supplled from read only memory 23 33-1 and then relnserted ln the reglster 37-1. This step -24 lS repeated durlng the thlrd clock perlod C3. During clock 25 perlod C3, the adder 34-1 wlll either add or subtract 26 dependlng upon the slgn of the D0 data blt applled to 27 the adder control clrcult 38-1. If the slgn blt is negative, 28 adder control circuit 38-1 Wlll provlde an appropriate signal 29 to adder 34-1 causlng a subtractlon to take place. If the slgn blt ls posltlve, an addltlon wlll take place. The ., . ' ~ RA9-74-002 -16-., , ~, .

', ' .
.

1 arrangement of adder control circult 38-1 will be described below.
2 During the fourth clock period C4, the contents 3 of register 37-1 are added to the signal supplled by the read 4 only memory 33-1, passed through ~ to sln ~ conversion read only memory 41-1 and inserted in a buffer 45 whlch ls 6 under control of a read-write and clear control circuit 46.
7 Circuit 46 responds to clock pulses C4, C5 and Cl. During 8 clock pulse C4 the output from ~ to sln ~ conversion circuit ; 9 41-1 is inserted into buffer 45. The contents of register 37-1 are not altered at this time. That is, the summation during 11 the fourth clock perlod C4 does not alter the contents of buffer 12 37-1. Thls ls effected by read/write control circuit 35-1 in 13 response to the C4 clock pulse. During the fifth clock pulse C5, 14 the signals supplied from read only memory 33-1 are subtracted from the contents of reglster 37-1 under control of circuit 38-1.
16 The output of adder 34-1 ls passed through ~ to sln ~ conversion ~, 17 circuit 41-1 and applled to one input of an adder 47. The 18 other input of adder 47 is connected to buffer 45 which during 19 clock time C5 is read into the other input of adder 47 under control of read/write and clear circult 46. The output of 21 adder 47 ls lnserted in register 42-1 whlch at the trailing ;~ 22 edge of clock time C5 is applied to a digital to analog 23 converter 43-1 which has its output connected to fllter 44-1.
24 Adder control clrcuit 38-1 is provlded with an OR gate 48 havlng two inputs connected to the Cl and C2 outputs of clock 26 generator 30-1. The output of OR gate 48 is connected to one 27 lnput of another OR gate 49 whlch has lts output connected ~ 28 to the control lnput of adder 34-1. When thls output is in a 1 29 ~ 1 state, that ls when either clock pulse Cl or C2 are present, adder 34-1 wlll add the contents applled at its two inputs.

: l .
j l When the output of OR c1rcu1t 49 1s 0, the contents appl1ed to the two lnputs wlll be subtracted. An ~ND gate 50 has one 1nput connected to the DO data blt 11ne sa1d a second 1nput connected to the C3 clock output of ;' clock generator 30-l. When the data b1t DO 1s l, dur1ng clock per10d C3, AND gate 50 provides an output wh1ch 1s appl1ed vla OR clrcu1t 49 to cause . .
- I adder 34-l to assume the add1ng mode, 1f the data b1t 1s 0 1nd1cat1ng the ~
negat1ve s1gn, the adder w111 be controlled to perform a subtract10n. A ~ -th1rd 1nput to OR c1rcu1t 49 1s connected to the C4 output of clock gener-ator 30-l and causes an addtt10n to occur dur1ng the C4 clock t1me. Sum- -~
mar1z1ng adder 34-l under control of adder control c1rcult 38-l performs , an add1t10n dur1ng Cl, C2~ and C4 t1mes regardless of the c1rcumstances.
J Dur1ng C3 t1me 1t performs an add1t10n, when the DO b1t 1s pos1t1ve and a subtract10n when the DO b1t 1s negat1ve. Dur1ng C5 t1me, a subtract10n 1s ~ always performed.
I The modulator of F1g. 4 1s spec1f1cally conf19ured to perform the funct10n of a four-phase modulator such as the IBM~ 3~72 and the Bell~
201 modems and 1s based on encod1ng two b1ts of data per baud by the d1fferent1al phase between bauds as 1nd1cated 1n the table below.
DO Dl Phase D1fferent1al l l +45 l 0 ~135 ,l O l -45 , O O - -135 ;l As w1th the FSK modulat10n prev10usly descr1bed, abrupt trans-~, 1t10ns 1n phase between bauds 1n DPSK modulat10n produce modulated output s1gnals conta1n1ng excess1ve out of band frequenc1es. A signif1cant reduct10n 1n the bandwldth of the output signal can be ach1eved by J
"1 - ' ~", , ' . .

I ~Trade Marks - 18 - i -., ~,, i.l . .
.` I' ' ' ~' "
_ . . . .

-` 1081848 1 having the ~ increments between the bauds vary in a 2 smooth manner. Additional reductions in bandwidth can 3 be obtained by combining amplitude modulation wlth the 4 phase modulatlon. The above attributes are obtained through a widely used approach which employs a modulated 6 signal conslsting Or using two phase modulated carriers, 7 each wlth envelope modulation. Abrupt phase changes are 8 made when the envelope of the particular carrier is zero.
9 The equlvalent modulated signal has a smooth phase transition and can be written with the following form.
11 L(t) = E(T) COS [wct + ~m + ~(T)]
12 where Wc = carrler frequency 13 ~m - arbitrary phase angle (not significant since the 14 modulatlon is on a differential phase) E(T) = envelope or amplitude function 16 and ~(T) = Phasing function whlch describes the phase î 17 change between bauds.
18 The direct but straightforward approach to implementing 19 the above line si~nal requires a digital multiplier to accomplish the amplitude modulation. Such an approach would 21 significantly increase the complexity of the transmitter.
22 Multiplication is avoided by taking advantage of the ability i 23 to accurately control phase an~le within the transmitter signal 24 flow. The technique used is described below. Let L(t) = E(T) COS [~(t)]
26 where ~t) = Wct + ~m + ~( T) 27 and assume E(T) is scaled to a maximum level of 1.
28 then E(T) COS ~(t) = 1/2 {cos [~(t)+cos lE(T)]+cos[~(t)-cos lE(T)]}
29 or L(t) - cos [~(t) + ~0( T ) ] + C O S [ ~ ( t) - ~0( T ) ]
where ~0(~) is an offset angle equal to cos 1[1/2 E(~)]

,:
.; .

_., ~081848 1 Amplltude modulation is accompllshed by generatlng 2 two phase modulated sinusoids properly dlsplaced in phase 3 by 2~0(T) and transmitting their vector sum as described -4 above ln connection with the Fig. 4. The processing period as described for the line is segmented into five 6 parts. During the first part, Cl, a rùnning accumulation of lnterbaud tlme ~ ls made. Thls ls similar to the accumulatlon 8 performed with respect to the FSK modulator described above.
g However, in the case of DPSK modulation, T can be allowed to overflow since a phase change is made in each baud time.
11 As in the case of FSK, the three most significant bits of '12 T are used. Thus, E(T) and ~(T) are each deflned by eight 13 dlscrete values per baud. See the graphs in Flgs. 4A, B and C.
14 Durlng the second tlme perlods, C2 of the processlng cycle e(t) ls lncremented by an amount ~c whlch corresponds to that 16 part of the phase accumulatlon due to the carrier frequency l 17 Wct. Durlng the third processing time period, C3, ~(t) is ¦ 18 changed by an amount ~( T ) which generates the smooth transitlon I 19 ~(T) in phase change over the baud time. Again, this may be seen from the graphs in Figs. 4A-C. ~(T) iS determined by T ~d~rthe 21 magnitude of the phase change to be made which is determined by ;
22 the Dl data bit. The sign of ~( T ) iS determlned by the D0 '1 23 data blt which controls the sign of the adder via the adder -24 control circuit 38-1. During the fourth and fifth processing times of each cycle, the offset angle ~O(T) is selected from 26 memory. The particular value selected ls determined by the 27 value of T and the magnitude of the phase change by the data '! 28 bit Dl. The magnitude of ~O(T) is independent of the sign of 29 the change. During the fourth C4 time, the sum ~(t) + ~O(T) 3o is calculated and converted to an amplitude value which is placed . , 108~84~ :
1 ln buffer 45. Durlng the fifth time period, C5, ~(t) - ~O(T) , 2 iS calculated and converte~ to an amplltude value and added to the .
3 contents of buffer 45 ln adder clrcult 47, to thus produce 4 the composlte modulated signal at the end of C5 tlme. The output of adder 47 is inserted in the register 42-1 and gated 6 to the digltal to analog converter 43-1 at the approprlate ~i 7 time by the traillng edge of the c5 clock pulse from clock 8 generator 30-1. the output of the digital analog converter 9 43-1 pulses filter 44-1 to provide the signal on the line.
The filter, a simple RC filter, removes the quantizing noise 11 lntroduced by the digital generatlon process.
12 The memory contents for read only memory 33-1 are ¦ 13 illustrated in Flg. 5. A slngle bit line control word j 14 which may assume two states, 0 and 1. Two sets of values are stored. Each occupy 44 addresses in the memory. The 16 first set 1-i+33 are associated with modulation type 17 LCW = 0. The selection process or logic required in the 18 address generator 31-1 for each of the addresses and the 19 data lnput supplied thereto are illustrated in the table 20 alongside each of the address locations.
21 Address 1 lncludes a value T/8 whlch for the sampling 22 frequency selected will when successively added to the contents 23 ln buffer 36-1, reduce the substantlally equally spaced detectable 24 outputs from buffer 32-1 whlch are applied to the address 25 generator 31-1 during a slngle baud time. The contents of 26 address 1 are obtalned durlng the clock tlme Cl of each sampllng 27 cycle. The data content of the Dl bit and the values from the ~! 28 T buffer 32-1 have no consequence. Thus, during each baud time 29 register 36-1 counts up by the predetermined value T/~ which is selected based on the baud rate of the information and , 'i , , .
. .

108184~
1 the sampling frequency fs by 8 detectably different outputs 2 in the three high order blts Or the I buffer 32-1 substantially 3 equally spaced across the baud time. Address i+l contains a 4 value ~c which in the circuit disclosed in Fig. 4 produces

5 the carrier frequency when incrementally added in the 9(t)

6 register 37-1. Thls partlcular quantity is provided during

7 the second or C2 clock time and the value again of I and

8 the value of the Dl bit are immaterial. The value selected

9 for ~c is dependent upon the carrier frequency of the modulation.
The contents of memory addresses i+2 through i+9 contain 11 the ~( T ) ~ S necessary to provide a smooth transition in eight 12 successlve steps where the phase is to be advanced or retarded by 13 135 as determined by D0 for the selected baud rate and carrier 14 frequency defined by llne control word zero. The particular 15 value selected from these addresses ls determined by the three 16 high order blts from the T buffer 32-1. These are lllustrated 17 ln the table. One of these values is selected durlng the third 18 clock time of each sampling perlod C-3, depending upon the 19 value of the T buffer 32-1. Addresses i+10 through i+l7 20 contain similar values for ~(T) for a smooth transition of 21 + or -45 and are selected on the same basls and during the 22 same clocking period as addresses i+2 through 1+9. These 23 values are selected if the Dl bit is a 1 instead of a 0.
24 A8 previously stated, the values of ~O(T j are the same 25 during the fourth and fifth cycles, therefore a single set 26 of values for ~O(T) is provided in address i+l8 through i+25 27 for a phase change of 135 and another set of values for ~O(T`) 28 is provided ln address 1+26 through 1+33 for a phase change 29 of 45 depending upon the status of bit Dl. One or the other 30 of these groups of values for ~O(T) is selected during the . .

1 C4 and C5 processlng periods. The particular one selected 2 from each Or the groups ls determined by the value of T
3 buffer 32-1. More speclflcally, the three hlgh order blts .4 contalned ln the bufrer. During the C4 period the value read rrom 5 memory 33-1 ls added to the contents Or reglster 37-1 and st~red ln ~ :
6 burrer 45 arter belng converted ln ~ to-sin ~ converslon ~ 7 clrcuit 41-1, and durlng the C5 processing period, the value 8 of ~O(T) read from memory 33-1 18 subtracted from the contents 9 Or reglster 37-1, converted ln 9 to slne ~ converslon clrcult 41-1 and at that tlme added to the contents prevlously 11 stored in buffer 45 in the adder 47.
12 The memory includes another set Or addresses J through ~+33 13 ror a second type Or DPSK.modulator ldentlfled by llne control 14 word one. These values are slmllar to the values descrlbed above in addresses 1 through 1+33, however, the partlcular 16 values stored wlll depend upon the carrler frequency and ~ 17 the baud rate rOr the modulator. If addltlonal modulation ¦ 18 frequencles and baud rates are to be lmplemented, addltlonal 1. 19 blocks of memory addresses will be requlred and the llne ~ 20 control word wlll have to be expanded to unlquely identiry ¦ 21 whlch ls to be selected by the address generator 31-1.
22 Whlle the modulation process has been described in terms 23 of 4-phase modulation, it is extendable to higher levels of l 24 phase modulatlon such as 8-phase by provldlng sultable functions for ~(T) and ~O(T) as wlll be well understood by those 26 skllled ln the art.
27 . In some lnstances such as where low baud rates are used , 28 or where less strlngent out of baud slgnal reductlon requlrements 29 are stlpulated, the amplltude modulatlon described and.lllustrated - 30 may be elimlnated. Thls may be accomplished by ellminating the .

108~

1 processing steps performed furing the c4 and c5 clock times.
2 In this event, the clrcult components following ~/sln ~ `
3 converslon clrcult 41-1 would be ldentlca to those followlng 4 the corresponding circult 41 in Fig. 2.
In addltion, the ci-rcuit illustrated in Fig. 4 and 6 described above may be used to perform an amplltude modulation 7 only. Thls may be accomplished by eliminating the processlng 8 step whlch occurs in the c3 clock time. Thls would elimlnate 9 the additlon of the phase components ~( T ) . In this lnstance, no structural changes are requlred except for the eliminatlon 11 or suppression of the c3 clock tlme and processing steps 12 which occur thereln.
13 The modulator lllustrated in Fig. 6 ls speclflcally 14 arranged to perform a multlfrequency modulatlon slmllar to 1 15 what ls commonly known as touchtone slgnalllng. In thls 16 form of slgnalllng) palrs of selected frequencies are 17 slmultaneously transmltted to convey lnformatlon. If four A and 18 four B frequencles are avallable, and one A and one ~ frequency 19 are slmultaneously transmltted, slxteen different palred frequency combinations are avallable for transmlttlng data. These may 21 typically transmit ten numerlc diglts and six control characters.
22 The modulator has the same general format as 23 modulators prevlously descrlbed. Four parallel data blts 24 are requlred to identlfy two tones, one of whlch ls selected from a group of four and the other of which is selected from 26 another group of four. These are lndlcated ln the drawing as 27 D0 through D3 and are applied dlrectly to the address generator 28 31-2. A clock generator 30-2 provides a sampling frequency 29 fs having two phases Cl, C2. The Cl phase occupies the first 30 half of the clock period and the C2 phase occupies the second :
'"

' ',.: ' ;'. ' ;

1 half of the perlod Or clock 30-2. Both of these signals are 2 applied to address generator 31-2 whlch based on the lnput 3 slgnals generates an address for accessing phase information stored 4 in a read only memory 33-2. Read only memory 33-2 includes two sets Or values ~1 and ~2 whlch are the increments of 6 phase and are simllar to those des¢rlbed in the previous modulators.
7 The value of ~ selected thus determlnes the frequency of thé tone 8 which will be generated by the modulator.
9 The contents of read only memory 33-2 are illustrated in tabular form ln Flg. 7. In address locations i through i+l5, the 11 selectlon slgnals include the line control word, data bits D0 12 through D3, and the two clock phases Cl and C2. The eight 13 addresses i through i+7 are associated with one of A and B
14 frequencies each including four dlfferent frequencies and the addresses i+8 through 1+15 are assoclated wlth another set. These 16 sets are ldentified by the llne control word belng zero or one.
17 The data blts D0 and Dl deflne the A frequency whlch must 18 be generated. The generation of the A frequency occurs during 19 the flrst half of the clock period lndicated by Cl being in a positlve state and C0 ln a negatlve state. The generatlon 21 of the B frequency is accompllshed during the second half 22 of the clock period. Thls may be seen ln the table.
23 The partlcular conflguratlon Or the D0 and Dl blts selects 24 one of four values of ~1 and the conflguration of the D2 and D3 bits selects one Or four values of ~2 , selectlons 26 belng made from addresses i through 1+7 on the basls of 27 the line control word and from the ~1 group on the basls 2~ of the Cl clock pulse and from the ~2 group on the basls 29 of the C2 clock pulse.- As previously stated, the nat~e of the data stored and the locatlon 1+8 through i+l5 is slmilar :`
RA9-74-002 -25_ .

.....
, .

-lOB1848 1 differing only in the values stored. The selectlon signals 2 except for the line control word are substantially slmilar.
3 The contents Or the read only memory 33-2 accessed by the 4 output Or address generator 31-2 are applied to one input o~
an adder clrcuit 34-2. The adder circuit 34-2 in this modulator 6 is always operated in the add mode and the adder control circuit 7 38-2 produces this result since the two clock pulses are applied 8 to an OR clrcult 52 whlch has its output connected to one of 9 two lnputs of an AND circult 53. The other input Or the AND
clrcuit is conne¢ted to a posltlve source of voltage and provides 11 one level at all tlmes slnce the clock pulses Cl and C2 are 12 posltlve ln alternate half-cycles Or the clock generator 30-2.
13 The other control circuit 38-2 was inserted prlmarily to indicate ¦ 14 the compatlbllity with the other modulator forms dlsclosed and ~ 15 descrlbed above.
;' 16 The output of adder 34-2 ls selectively .~ ..
17 applled to one Or two reglsters 36-2 or 37-2 under control 18 of a read/wrlte control clrcult 35-2 whlch responds to ;~ 19 clock pulse8 Cl and C2. When clock pulse Cl ls recelved, 20 reglster 36-2 lS connected to the output of adder circuit 34-2 21 and when clock pulse C2 ls recelved, reglster 37-2 is connected 22 to the output Or adder clrcult 34-2. The outputs of reglsters 1 23 36-2 and 37-2 are connected to the other lnput of adder clrcuit 24 34_2 and are controlled by read/wrlte control clrcult 35-2 ln 25 the same manner as the input from adder 34-2. Thus, durlng the 26 flrst clock cycle, ~1 selected by the lnputs prevlously 27 descrlbed ls added to the contents Or reglster 36-2 and ~i 28 relnserted in register 36-2. Durlng the second half-cycle 29 of the clock perlod, ~ 2 as previously descrlbed, is added j 30 to the contents Or reglster 37-2.

`i` RA9-74-002 -26-, I .

,, "`;' . ` , , , ': . , ' ' . , . ' ' .

~ 0 8 1~k9 1 The output of adder 34-2 is applled to a ~ to sine ~
conversion circult 41-2 identical to the circuits previously 3 described. The output of the conversion circuit is connected 4 to a register 45-1 which is under control of a read/write control circuit 46-1 whlch responds to clock pulses Cl and C2.
During clock pulse Cl, the output of the converter circuit 41-2 7 is inserted in register 45-1. During clock pulse c2, the contents 8 previously stored in register 45-1 is applled-to one input of g an adder circult 47-l. The other lnput of adder circuit 47-1 is connected to converter 41-2 and forms the sum of the two values 11 applied to the two inputs. The output of adder 47-1 is connected 12 to another register 42-2 which ls gated at the tralllng edge 13 Of clock pulse C2 to a digital to analog converter 43-2 which 14 has its output connected to a simple RC rilter 44-2.

The modulator described above in Flg. 6 is useful for 16 multlfrequency or parallel tone generatlon which may be 17 appllcable for data transmisslon or auto dlallng. These appli-18 catlons use sufflciently low baud rates as not to require the 19 bandwldth reductlon technlques used in the two previously 20 descrlbed modulators. If higher baud rates are requlred, 21 the technlque descrlbed ln connectlon wlth Fig. 2 may be used.

22 One of four tones are generated from each of two bands depending 23 on a baud of data conslsting of four blts. The processlng 24 perlod ls dlvlded into two segments Cl and c2. During the 25 Cl segment, bits DO and Dl select one of four values of ~

26 from the memory, the value of ~ determlnes the frequency of 27 the tone which wlll be generated. The value of tone 1, ~ltt) 28 stored in register 36-2, ls lncremented during each Cl time 29 and converted to an amplltude value sin ~l(t) and placed in the buffer register 45-1. During C2 time, the phase of the 1 second tone, 02(t) is incremented by a value ~0 deter-mined by input bits D2 and D3. The amplitude of the second tone sin ~2(t) stored in register 37-2 is added to the con-tents of buffer register 45-l to produce the next two tone transmitted signal at the end of C2 time.
Fig. 8 discloses an overall block diagram for a multi-line multimode modulator which is capable of servicing n input and n output lines substantially simultaneously by a time sharing technique of the modulator. The modulator is capable of providing different varieties of three major , types of modulations for any mix of the n lines. The modu-lation types provided are multifrequency, frequency shift keyed and differential phase shift key modulation. A num-ber of different varieties of each of the types of modula-tors may be implemented as will become apparent as the des-cription continues.
The multiline multimode modulator includes an input multiplexer 60 connected to n multiwire input lines or cables Ll through Ln. The multiplexer outputs are con-1 20 nected via an OR circuit 61 to a multimode modulator 62 where the signals from each of the n lines are sequentially modulated as required for the particular line. The modu-lated signals from the multimode modulator 62 are applied to a second multiplexer 63 which distributes the modulated signals to the appropriate output lines l-n via individual RC filters 64-l through 64-n. Filters 64-1 through 64-n are identical and each are simple RC filters whose sole 1~ function is to remove the quantizing noise from the digital to analog conversion process. A master clock circuit 65 ,~ 30 provides control signals to multiplexers 60 and 63 as well as to the multimode modulator 62. In addition, master clock circuit 65 provides control signals to a line control word :! ` . - . . - . . . . ;
~ . ~ . ... . . .. . ` .

108~848 1 memory unit 66 which provides signals to the multimode modulator 2 62 and the master clock circuit 65 Multiplexers 60 and 63 3 operate in synchronism under control of master clock circuit 4 65, thus lnput lines l-n are sequentially connected through the multlmode modulator 62 to output lines l-n, respectlvely.
6 The line control word memory unlt 66 lncludes n address each 7 identifled with one of the lnput lines Ll-n and ln whlch ls 8 stored a llne control word identifylng the preclse modulatlon 9 requlred for that line. That ls, which type of modulator it is and which varlety of modulator of that type ls belng serviced for 11 that llne at that tlme. The llne control words may be changed as 12 requlrements for modulatlon for any line are changed. This 13 may be done manually or automatically as wlll become apparent 14 as the descrlptlon continues.
The master clock 65 and the llne control memory unit 66 16 are lllustrated ln detall ln Flg. 9 slnce these unlts provlde 17 all of the control signals for the multiplexers 60 and 63 and 18 the multimode modulator 62.
19 A clock generator 67 operates at a frequency nfs where fs ls the sampling frequency per line and n is the number of 21 llnes which must be sampled. Except for the actual frequency 22 utllized, this clock ls slmllar to clock 30-1 of Flg. 4 and 23 provldes durlng each clock perlod, flve outputs lllustrated 24 below the clock ln graphic form. The flrst output ls posltlve during the first quarter of the period and negative during the 26 remalnder of the period. The second output ls positive only 27 during the second quarter of the period. The third output is 28 positive only durlng the third quarter of the period. The 29 fourth and fifth outputs are positlve during the first and .j .
~ 30 second halves of the fourth quarter, respectively. The one :, ' .' ,' ' :

108~

1 output from clock generator 67 is applied to a binary counter 2 68 which is arranged to count as high as n and recycle thus 3 incrementlng one count durlng each period of clock generator 4 67. The output of binary counter 68 are applled to a decoder -~
clrcuit 69 whlch provldes the enabllng outputs for operatlng multlplexers 60 and 63 slnce the outputs of decoder 69 sequentially 7 identlfy one of the n llnes. The outputs of blnary counter 68 are also applled vla gate circuits 70 to latches 71 to 9 provlde a blnary output ldentlfying the lines. The output of latches 71 are applled dlrectly to the multimode modulator 62 11 and the use Or thls output will be de~cribed later.
12 In addlton, the outputs of blnary counter 68 are utillzed 13 as addresses for accesslng the random access line control word 14 memory 72. Thus, each tlme blnary counter 68 lncrements to a new value, a new word is read out of random access llne control ~ 16 word memory 72 and provlded on the data output bus 73. Random ¦ 17 access line control word memory 72 ls also provided with a data ~ 18 lnput bus and write control circults whereby line control words ;~ 19 may be lnserted into the random access memory as needed or desired from some external source such as a computer 74 lllustrated ~ 21 in the drawlngs. Typically, computer 74 may also be the source i 22 of the data which ls belng transmltted over lines Ll through 23 Ln. Alternatively, the llne control words may be inserted 1 24 from a locally associated termlnal connected to the data bus and the wrlte control circuits and need only supply the address 3 26 location and the data to be stored therein.
` 27 The data output on bus 73 from random access line control 28 word memory 72 ls applied to a decoder circuit 75 whlch provldes 29 one of three outputs identlfying the modulation type. The ~
30 outputs are labeled MTl, MT2 and MT3. The outputs of MTl-MT3 are -.', I ~ .

RA9-74-002 _3o_ .

:. ' ., .
,, , - ,.. . . . : . , .

... . . : . . , 1 applied to the multimode modulator 62 as will be apparent in 2 connection with the descrlption of Fig. 10. The data output bus 3 73 ls also applied to the multimode modulator 62 and the use of 4 these signals will be described in connection with the description of Flg. 10.
6 The MTl output from decoder 75 is connected to two AND
7 gates 76-1 and 76-2. The output MT2 ls connected to two AND
8 gates 77-1 and 77-2 and the output MT3 is connected to flve 9 AND gates 78-1 through 78-5. Gates 78-1 through 78-5 are connected to outputs 1-5 respectlvely rrom clock generator 67 and provide 11 flve sequentlal outputs when the llne control word decoded 12 lndlcates a dlfferentlal phase shift keyed modulatlon functlon 13 must take place for that llne. The outputs of the gate 78-1 14 through 78-5 for convenlence have been labeled A, B, C, Dl and D2, respectively. These pulses ln the descriptlon which follows will 16 be consldered clock pulses appearlng during a single sampllng 17 period for processlng purposes ln the clrcult of Flg. 10 18 whlch is a detalled block dlagram of the multlmode mcdulator 19 62. These slgnals are applled to the modulator 62 as seen ln Flg. 10 ln the places lndlcated by the above alphabetic labels.
21 Outputs 1 and 2 of clock generator 67 are connected to an OR
22 circult 79 whlch has lts output connected to AND gates 67-1 and 23 77-1. Outputs 3, 4 and 5 from clock generator 67 are -24 connected to OR clrcult 80 whlch has lts output connected to AND gates 76-2 and 77-2. AND gates 77-1 and 77-2 provlde 26 outputs Al and Bl respectlvely when the modulatlon required 27 is FSK while AND gates 76-1 and 76-2 provlde outputs A2 and B2 28 when the modulatlon required is multlfrequency. The tlmlngs 29 provlded by the signals from these AND gates may be determined 3 from the graphs shown below clock generator 67. ~ l ' , . .

':
,,:

':. ~' ' --` 1081848 1 Clocks Al and Bl occupy the first and second halves of 2 a sampling perlod, and are active durlng a FSK modulation. ' '~
3 Clocks A2 and B2 occupy the first and second halves 4 of a sampling perlod and are provided when a multi- ' frequency modulatlon takes place for a glven line.
6 Clocks A, B, C, Dl, and D2 are provided when a DPSK
7 modulation ls taking place for a glven llne and are ldentlcal 8 ln tlming during a single clock perlod as shown ln the graphs , '~
9 below clock generator 67.

10 The multlmode modulator illustrated in Fig. 10 is slmilar ,~

11 in many respects to the DPSK modulator illustrated in Flg. 4. `''

12 However, lt utlllzes three separate address generators, each

13 slmilar to those previously described and three adder control

14 clrcults slmilar to those previously described and selectlon, gates under control of the signals MTl through MT3 illustrated 16 in Fig. 9 and previously described.
17 A three sectlon address generator 80 having a 18 first sectlon 80-1 for generating addresses based on the inpu,t 19 data for the selection of slgnals from the memory sultable for produclng multlfrequency,tone palrs; a section 80-2 for 21 generating addresses s'uitable for the selectlon of data 22 for generatlng dlfferentlal phase shlft keyed slgnals; and `-23 a sectlon 80-3 sultable for generatlng addresses for accesslng 24 data sultable for generating frequency shlft keyed slgnals is connected to the output as lndicated of OR circuit 61 whlch 26 provides up to four data lines in parallel. The sectlons are 27 also connected to the Al, Bl, A2, B2, A, B, C, Dl and D2 clock 28 signals from the master clock 65; to the line control words f,rom 29 the data output bus 73 of random access llne control word memory 3 72; and to a T register 32-2 simllar to the I registers previously ' ~ ' .

.; .

....... . . ; , . . . . . . . ..
. . , , ~ . , .

1 described in connection with the descrlptlon of Figs. 2 and 4 2 and which wlll be described in detail below. Section 80-1 may 3 be ldentical to the address generator 31-2 illustrated ln Flg. 6.
4 Section 80-2 may be identlcal to the address generator 31-1 illustrated in Fig. 4 and section 80-3 may be identical to the 6 address generator 31 lllustrated ln Flg. 2. The outputs of 7 sectlons 80-1 through 80-3 are connected by gates 81-1 through 81-3 - 8 to the control lnput of a read only memory 82 which contains g all the informatlon in read only memories 33, 33-1 and 33-2 Or Figs. 2, 4 and 6, respectlvely.
11 The three sectlon adder control clrcuit 83 provldes adder 12 control for each o~ the three modulation modes, and includes 13 a Pirst sectlon 83-1 ~or provldlng the adder control function j 14 ror dl~ferential phase ~hlft keyed modula~lon, a second sectlon 83-2 Sor provldlng adder control ror frequency shift keyed 16 modulatlon and a third sectlon 83-3 for performing adder control 17 for multifrequency modulatlon. The lnputs to each of these 18 sectlons are ldentlcal to the correspondlng adder control 19 clrcuits 8hown ln Flgs. 2, 4 and 6. Each of the sectlons is ; 20 connected by a swltch 84 under control o~ the MTl through MT3 21 outputs from decoder 75 to the control input of an adder 34-3 -22 which i8 slmllar to adders 34-1 through 34-2 shown ln the ¦~ 23 previous rlgures.
¦~ 24 The output of read only memory 82 ls connected to one o~
~ 25 the lnput8 of adder 34-3. The output of adder 34-3 ls .
~26 connected to the data lnput bus Or a random access memory 85 and 27 the output bus oS random access memory 85 ls connected to the other ` 28 ~ input Or adder 34 and to a T burrer 32-2 slmilar to the T
;~ 29 buffers 32 and 32-1 shown ln Flgs. 2 and 4, respectlvely.
Random access memory 85 contalns two address locatlons ~or -~RA9-74-002 -33-' ', ' "'~
'' ., -... . .... ... . - . . ~ . ... ., .. , . ~ .... , . . . . : . . . . .
. . ~ . ,, , ., . . . . . - . . . .: . , . , . , . . ., , . . .: . .

~08184B

1 each of the n llnes serviced by the multiline, multifrequency 2 modulator. Which Or these addresses ls selected is controlled 3 by an address generator and read/write control circuit 35-3~
4 which responds to the LC output from latches 71 and the clock signals Al, Bl, A2, B2, A, B, C, Dl and D2 from master clock 6 cirCUit 65.
7 For example, lf the multlllne, multlmode modulator is 8 serving four lines, the output of blnary counter 68 wllI be g provlded on two llnes whlch may be 00, 10, 01 and 11 dependlng upon whlch line is belng serviced. These two llnes may be used 11 as the high order blts of the address in random access memory 85.
12 The low order blt for the address wlll be selected as a functlon 13 Of the clock slgnals, Al, A2, and A lndlcatlng a 0 low order blt 14 and the other clock pulses lndlcatlng a 1 low order bit. Durlng clock tlmes Dl and D2, a read operatlon only takes place.
16 The output of random access memory 85 ln addltlon to belng 17 connected to the other lnput of adder clrcuit 34-3 ls connected 18 to a T buffer 32-2 whlch is loaded during the A and the Al clock 19 pulse tlmes. The three high order blts from buffer 32-2 are applied to address generators 80-2 and 80-3 and perform the 21 same functions in these address generator sections as they 22 performed ln the slngle llne verslons described in Figs. 2 and 23 4. The output of adder 34-3 is applied to a ~/sin ~converslon 24 clrcult 41-3 slmllar to all of the prevlously described a~sin~
conversion circults. The remalnder of the circuit is functionally 26 similar to that of Fig. 4 and includes a register 45-2 connected 27 to the output of ~/sin ~ conversion circuit 41-3 for receiving 28 the output therefrom under control of a read/wrlte and clear 29 clrcult 46-2 and supplylng an lnput to a second adder clrcult 47-2 which ls also connected to the output of circult 41-3. A

. ' ' "

108~

register 42-3 is connected to adder 47-2 and supplles when gated 2 a digital to analog converter circult 433. Read/write and clear 3 control clrcuit 462 is responsive to clock pulses A, Al, A2, B2, 4 Dl and D2. During clock pulses A and Al, the register is cleared to thus cause adder circuit 472 to dlrectly pass the output of 6 conversion clrcuit 41-3 to the register 42-3 without alteration 7 since in these instances, the function performed by the adder 8 circult 47-2 ls not needed or desired. During the Dl and A2 9 clock times, the contents from converslon circuit 41-3 are read into the register 45-2 and durlng the D2 and B2 clock pùlses, 11 the contents of reglster 45-2 are read into the adder clrcuit`:
12 47-2 where they are added to the then available contents from 13 conversion circuit 41-3. The output from digital to analog 14 converter circult 43-3 is applied to the lnput of multiplexer 63 111ustrated in Fig. 8 and under control of the master 16 alock slgnals from clock 65, it ls distributed to the 17 appropriate output line l-n via the simple RC fllters 64-1 18 through 64-n.
19 The three ma~or modulatlon technlques implemented in Flg. 10 are identical to the three modulation techniques 21 illustrated and described with respect to Figs. 2, 4 and 6.
; 22 The only dlfference beln~ that the address generator for ~ 23 accesslng read only memory 82 is expanded to encompass all `I 24 of the varlous modulation types, the clock is expanded to provide each of the clocking signals, the adder control circuit 83 26 is expanded to provlde the three different types of addition , 27 control prevlously descrlbed and the switch 84 ls provlded 1 28 to connect the appropriate adder control signals as lndicated 29 by the signals from the master clock 65. The only other-additlon is the expanslon of random access memory 85 to include `.
RA9-74-002 _35_ .. ..

- . . . .

108'1848 l two address pos1t~ons for each of the 11nes handled by the mult111ne, mult1mode modulator. 51nce only two address pos~t10ns are requ1red for each 11ne, random access memory 85 1s general purpose and the only s19nals needed to select the appropr1ate addresses are those s19nals from master clock 65 wh1ch ldent1fy the llne currently be1ng serv1ced and those clock1ng I slgnals necessar~ to control the funct10n of the memory 85. The rema1n1ng c1rcu1ts are, as prev10usly stated, ldentlcal to those of F1gs. 4 and 6.
Insofar as the modulat10n techn1que descrlbed 1n Flg. 2 ls concerned, the adder 47-2 and the reg1ster 45-2 and control 46-2 are superfluous and the ; lO reason for prov1d1ng the reset s1gnal as stated above, 1s to remove these c1rcu1ts 1n those 1nstances where the frequency sh1ft key modulat10n 1s be1ng 1mplemented. S1nce 1n those 1nstances, zero 1s 1nserted ln the reg1ster 45-2 and an add~t10n of zero to the d1g1tal slgnals prov1ded by the converter c1rcu1t 45-3 passes those s1gnals on through to reg1ster 42-3 unchanged.
It 1s obv10us that th1s c1rcu1t prov1des substantlal savlngs ln l~ cost s1nce expand1ng 1t to 16 or more 11nes merely requ1red mlnor add1t10ns to the read/only memory 82 to store the factors of the dlfferent types of ~; modulat10n requlred and the expans10n of the random access memory 85 I 20 to 1nclude two reg1sters for each of the 11nes serv1ced.
`~I Whlle the 1nvent10n has been part1cularly shown and descr1bed w1th reference to preferred embod1ments thereof, 1t w111 be understood by those sk111ed 1n the art that var10us changes 1n form and deta11s may be made there1n w1thout depart1ng from the sp1r1t and scope of the 1nvent10n.
.

. ~ ,

Claims (8)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A multiline multimode modulator for substantially simultaneously modulating a plurality of different signals onto a plurality of dif-ferent output lines and in which one of n different modulations of m types may be selected for any of the output lines comprising:
a master clock means operating at a clock frequency substantially higher than the baud rate for any of the modulations to be performed and providing a first clock output at the said frequency and selec-tively one of m multiphase clock output signals during each period of said clock frequency, a line control word memory including read and write control means and a number of addresses at least equal to the number of lines to be serviced for storing line control words which uniquely define the modulation to be performed for the line corresponding to the address location and responsive to said first clock output for providing line control words in a predetermined seuqence;
a digital multimode modulator including a memory for storing digital numerical values representing the modulation parameters for each of the said n different modulations, digital processing circuits connected to said memory for receiving the stored digital numerical values provided thereby and responsive to the data to be modulated, the line control word signals and the selected one of m multi-phase clock output signals for generating a modulated output signal as a function of the above said signals, and an address generator responsive to the data signals to be modulated, the line control and word signals, the digital processing circuits and the selected one of m multiphase clock output signals for generating a predetermined plurality of sequential address signals for supplying the memory contents of the associated addresses to the said digital processing circuits; and multiplexing means responsive to said first clock output for supplying in sequence signals from one of a plurality of sources to said digital multimode modulators and supplying the output from said multimode modulator in sequence to one of a plurality of lines.

2. A multiline multimode modulator as set forth in claim 1 in which the modulation performed for any line may be changed by writ-ing a new line control word defining the new modulation into the address in the line control word memory associated with the line.

3. A multiline multimode modulator as set forth in claim 2 in which said m multiphase clock outputs is at least two and one provides two clock phases for controlling as FSK modulation and the other provides at least three clock phases for controlling a DPSK modulation.

4. A multiline multimode modulator as set forth in claim 3 in which said digital processing circuits includes common circuits for each of the m modulation types and a read/write memory including a pair of registers for each line for storing calculated parameters and selectively during each cycle of operation by the said line control word signals and clock phase signals.

5. A multiline multimode modulator for substantially simultaneously modulating a plurality of different signals onto a plurality of dif-ferent output lines and in which one of n different modulations of m types may be selected for any of the output lines comprising:
a master clock means operating at a first clock frequency (nfs) in which fs is substantially higher than the baud rate for any of the modulations to be performed and n is equal to the number of output lines and providing a first clock output at the said clock frequency and selectively one of m multiphase clock output signals during each period of said clock frequency;
a line control word memory including read and write control means and a number of addresses at least equal to the number of lines to be serviced for storing line control words which uniquely define the modulations to be performed for the line corresponding to the address location and responsive to said first clock frequency for providing line control words in a predetermined sequence;
a digital multimode modulator including a memory for storing digital numerical values representing the modulation parameters for each of the said n different modulations, said parameters for each of said n different modulators including a plurality of numerical values for each of the possible signal transitions which are selected at least once within each interbaud time in which a transition occurs to cause said transition to follow substantially reduced out of band frequency components, digital processing circuits connected to said memory for receiving the stored digital numerical values provided thereby and responsive to the data to be modulated, the line control word signals and the selected one of m multiphase clock output signals for generat-ing a modulated output signal as a function of the above said signals, and an address generator responsive to the data signals to be modulated, the line control word signals, the digital processing circuits and the selected one of m multiphase clock output signals for generating a predetermined plurality of sequential address signals for supplying the memory contents of the associated addresses to the said digital processing circuits; and multiplexing means responsive to said first clock output for supplying in sequence signals from one of a plurality of sources to said digital multimode modulators and supplying the output from said multimode modulator in sequence to one of a plurality of lines.

6. A multiline multimode modulator as set forth in claim 5 in which the modulation performed for any line may be changed by writing a new line control word defining the new modulation into the address in the line control word memory associated with the line.

7. A multiline multimode modulator as set forth in claim 6 in which said m multiphase clock outputs is at least two and one provides two clock phases for controlling as FSK modulation and the other provides at least three clock phases for controlling a DPSK modulation.

8. A multiline multimode modulator as set forth in claim 7 in which said digital processing circuits includes common circuits for each of the m modulation types and a read/write memory including a pair of registers for each line for storing calculated parameters and selectively during each cycle of operation by the said line control word signals and clock phase signals.