CN85103949B - Multilevel signal monitor circuit - Google Patents
Multilevel signal monitor circuit Download PDFInfo
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- CN85103949B CN85103949B CN85103949A CN85103949A CN85103949B CN 85103949 B CN85103949 B CN 85103949B CN 85103949 A CN85103949 A CN 85103949A CN 85103949 A CN85103949 A CN 85103949A CN 85103949 B CN85103949 B CN 85103949B
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Abstract
A kind of multilevel signal monitor circuit in data transmission system, this system transmissions converts the mass data behind the multi-level signal to, and, the multi-level signal that receives obtains original long numeric data by being carried out analog-to-digital conversion, in this multilevel signal monitor circuit, when carrying out analog-to-digital conversion, receiving terminal carries out the judgement meticulousr than data bits with multidigit bit log certificate, and utilize above-mentioned extra bits to detect the convergence of signal on quantization level that receives, thereby can monitor the error rate apace, exactly with simple circuit.
Description
The present invention relates to a kind of signal monitor device, this device is provided for system receiving terminal, is used for converting long numeric data to multi-level signal, or rather, the present invention relates to a kind of multilevel signal monitor circuit, this circuit utilizes an A/D converter to produce data again.
People proposed various systems and are used for transmitting them after converting long numeric data to multi-level signal.For example, in utilizing the digital radio transmission system of quadrature amplitude modulation (qam), I channel data and Q channel data are converted into multi-level signal respectively, carrier wave to two phase differences, 90 degree carries out Modulation and Amplitude Modulation respectively, synthetic then the transmission utilizes the new exalted carrier quadrature detection of received signal to go out above-mentioned received signal.In order to obtain initial data, resulting I passage becomes digital signal with Q passage multi-level signal from analog signal conversion.
In such transmission system, if reason causes the inefficacy on wireless radio transmission circuit road owing to signal is weak etc., the error rate that then receives data will be very high, therefore, when if the error rate that records has surpassed particular value, this transmission line will be switched to another standby transmission line, and perhaps the deviation for fear of equalizer resets equalizer.
In order to measure the error rate that receives data, utilize following a kind of method, send out a kind of special data model at transmitting terminal, detect the accuracy of this data model that receives then at receiving terminal., this method has following shortcoming.
A) reduced transmission capacity, the amount of this minimizing is transmitted the quantity of above-mentioned particular module just.
B) need complicated circuit to detect above-mentioned special model.
C) error rate is very little usually, and the time that therefore need get than length needs a bigger integration time constant as measuring period or in order to measure accurately, and therefore, detection will be done same big time-delay.
The error rate of the data that receive in order to measurement as another kind of method, need many comparator and many logical circuits that are used for the output of above-mentioned comparator is carried out logical calculated that are used to distinguish quantization level and other level, constantly to the judgement of the multi-level signal that receives, the number of times of offset quantizing level will be measured as pseudo-error rate, and this can correspondingly use as the error rate., this method has following problem.
D) need a lot of comparators, and when the figure place of the data that will transmit and quantization level increase, be used to calculate the logical circuit that above-mentioned comparator exports and become very complicated.
Another method that is used for obtaining receiving the error rate of data is: judge constantly and judge that normal front and back constantly carry out analog-to-digital conversion very among a small circle normal; Measure being used as pseudo-error rate, and it is used as corresponding error rate numerical value at the number of times that departs from normal judgement moment decision level.Yet there is following shortcoming in this method.
E) need another analog to digital converter to detect pseudo-error rate, increased the scale of circuit.
F) when the correct damage that can cause the quantization level convergence when judging some deviation constantly, this situation because of the circuit transmission failure is different (for example, because the multichannel that reflected wave causes decline, because the signal attenuation rainy and component failure causes), the error rate that therefore can not accurately be conformed to.
An object of the present invention is to provide a kind of multilevel signal monitor circuit, this circuit comes to detect apace, exactly the error rate by a small-scale adjunct circuit, does not cause reducing simultaneously transmission capacity again.
Briefly, the invention provides an A/D converter, this A/D converter is judged the multidigit bit subtly, they transmit more than the data bit number, when the scope shown in this multidigit bit and quantization level are had any different, then it is construed to pseudo-error code, and monitors a multi-level signal by pseudo-error rate.
It below is brief description of drawings.
Figure 1A and Figure 1B are the transmitting terminal of 16 used level quadrature amplitude modulation (qam) radio transmission systems of the present invention and the block diagram of receiving terminal.
Fig. 2 A to Fig. 2 C is about not limiting 4 level signals of high fdrequency component, the oscillogram of conditional 4 level signals of high fdrequency component and clock signal.
Fig. 3 A and Fig. 3 B are an image figure who is used for explaining embodiments of the invention.
Fig. 4 A to Fig. 4 G is the block diagram of the embodiment of the invention.
In the transmitter of 16 level quadrature amplitude modulation (qam) radio transmission systems shown in Figure 1A, D/A 101,102 respectively with 2 bit data DI of in-phase channel (I-cha-nnel) and orthogonal channel (Q-channel) two systems, and DQ converts 4 level signals among Fig. 2 A to.In Fig. 2 A, V
0～V
3The expression quantization level. Low pass filter 103 and 104 has limited the high fdrequency component of described 4 value signals, and has formed the waveform shown in Fig. 2 B.Simultaneously, one 90 ° blender 105 is divided into a pair of carrier wave with 90 ° of phase differences with the carrier wave of output in the oscillator 106, then this is delivered to frequency mixer 107 to carrier wave, in 108, this frequency mixer carries out Modulation and Amplitude Modulation with a pair of described 4 level signals to above-mentioned two carrier waves, and the high fdrequency component of this signal has been limited.Described two modulated signals are synthetic in blender 109, launch from antenna 111 by transmitter 110 then.
Among the receiving equipment 10B in Figure 1B, receiver 113 receives the signal that arrives by antenna 112.By blender 114 signal that is received is divided into two-way and enters I channel and Q channel.Simultaneously, 90 ° mixing arrangement 115 makes by carrier recovery circuit 116 regenerated carrier signals, be divided into two carrier waves by 90 degree blenders with 90 degree phase differences, respectively these signals are exported to frequency mixer 117 then, 118, utilize above-mentioned a pair of regenerated carrier signal the signal of described I channel and the reception of Q channel to be separated and transfer to obtain respectively 4 original level signals by frequency mixer.When line work just often, a pair of 4 level signals of above-mentioned demodulation are similar to the transmitting terminal modulation signal among Fig. 2 B.Even line work lost efficacy, but as long as inefficacy is less, signal energy quilt is balanced, then the signal similar shown in signal and Fig. 2 B.This class carrier wave produces circuit and equalizer and once disclosed in the European Patent Convention application number is 84306977.4 application documents.4 level signals that I channel and Q channel demodulation go out are judged respectively by A/D converter 120 and 121.That is, in the rising moment of the clock signal shown in Fig. 2 C, I channel and Q channel are respectively by 4 bit (b
0～b
3) and 2 bit (b
0～b
1) judge.High two outputs of two channels as decision data (DI, DQ), low two (b of I channel
2～b
3) output on the pseudo-error rate mensuration circuit 122.Scope and quantization level (V when these low two bit representations
0～V
3) not simultaneously, pseudo-error rate is measured circuit 122 and judged pseudo-error code, and the frequency of this pseudo-error code measured be used as pseudo-error rate.
As shown in Figure 3A, utilize above-mentioned low two (b
2, b
3) will judge that the scope in quantization level is divided into 4 zones.In the drawings with r represent by low two (b
2, b
3) the scope of " 00 " and " 11 " appointment break away from quantization level, the frequency that enters such scope is considered to pseudo-error rate.
Shown in Fig. 4 A, pseudo-error rate testing circuit 122 roughly is made up of following parts: pseudo-Error detection circuit 123, it receives low two (b of A/D converter 120
2, b
3) and detect pseudo-error rate and a mensuration circuit 124, and measure the detecting signal of circuit reception from above-mentioned pseudo-Error detection circuit 123, and measure the number of times of its detection.Pseudo-Error detection circuit 123 is by a "AND" circuit 125, inverter 126 and 127, and "AND" circuit 128 and OR circuit 129 compositions, and wherein "AND" circuit 125 obtains above-mentioned two (b
2, b
3) " with ", inverter 126 and 127 make respectively above-mentioned two anti-phase, "AND" circuit 128 obtain inverter 126 and 127 output " with ", OR circuit 129 obtain "AND" circuit 125 and 128 outputs " or ", when above-mentioned low two these Error detection circuit 123 during for " 00 " or " 11 " are output as " 1 ".Measuring circuit 124 is made up of a counter 130 and a timer 131, wherein the output " 1 " of 130 pairs of pseudo-Error detection circuit 123 of counter is counted, and timer 131 makes above-mentioned counter 130 that each interior count value of fixing time is exported as pseudo-error rate.If convergence is owing to line out of service worsens, then low two of A/D converter 120 just become " 00 " or " 11 " more continually, and when above-mentioned count value has surpassed predetermined value, only need carry out specific processing procedure.
Shown in Fig. 4 B, the puppet testing circuit 123 of makeing mistakes only is made of an anticoincidence circuit 132.But, because above-mentioned low two (b
2, b
3) when being " 00 " or " 11 ", this circuit is with " 0 " output, the counter 130 that then requires to measure circuit 124 is counted the number of times that is input as " 0 ".
Shown in Fig. 4 C, measure circuit 124 and form, and pseudo-error rate can be exported with an analogue value by the integrating circuit that a resistance R and a capacitor C constitute.When pseudo-Error detection input high level, measure the poor of integration output and low level, and as pseudo-error rate.When pseudo-Error detection input low level, then measure the poor of integration output and high level, and with this as pseudo-error rate.
Shown in Fig. 3 B, can make the judgement more accurate with 3 bits than the data bit figure place, and with these 3 (b
2, b
3, b
4) be used for pseudo-Error detection, then might be with r
1Shown in like that narrow or r
2Shown in like that wide scope as the scope of pseudo-error code.
Shown in Fig. 4 D, detect r
1The pseudo-Error detection circuit of scope is made up of 133, one NOR circuits 134 of a "AND" circuit and an OR circuit 135; Wherein, "AND" circuit 133 obtains above-mentioned 3 (b
2～b
4) " and with ", NOR circuit 134 obtains above-mentioned 3 nondisjunction, OR circuit 135 obtain that "AND" circuit 133 outputs and NOR circuit export " or ".When being " 000 " or " 111 " for described 3, this puppet Error detection circuit is output as " 1 ".
Shown in Fig. 4 E, detect r
2The pseudo-Error detection circuit of scope is by an inverter 136, one "AND" circuits 137 and a NOR circuit 138, and a NOR circuit 139 is formed; Wherein, inverter 136 makes the significance bit (b in above-mentioned 3
2) anti-phase, "AND" circuit 137 obtains output and other two (b of inverter 136
3, b
4) " with ", NOR circuit 138 is finished the output of inverter 136 and other nondisjunction of two, the nondisjunction of the output of NOR circuit 139 acquisition "AND" circuits 137 and the output of NOR circuit 138.When described 3 output was not " 011 " and " 100 ", this testing circuit was output as " 1 ".
When needs accurately determine pseudo-error code scope, then need to judge more accurately.
Among Figure 1B, only the I channel is monitored,, just can realize as long as in the Q channel, also provide with a same analog to digital converter and the pseudo-Error detection circuit of I channel if must monitor the Q channel time.Shown in Fig. 4 F, when needs monitored simultaneously to I channel and Q channel, pseudo-Error detection circuit 123 can be by "AND" circuit 140 and 141, and NOR circuit 142 and 143 and one OR circuit 144 are formed; Wherein, "AND" circuit 140 and 141 acquisitions detect 2 (b of the pseudo-error code of I channel and Q channel respectively
2, b
3) " and with ", NOR circuit 142 and 143 obtains 2 nondisjunction separately, OR circuit 144 realize to the output of the output of above-mentioned "AND" circuit 140 and 141 and above-mentioned NOR circuit 142 and 143 " or ".Circuit shown in Fig. 4 G can be realized similar logical operation.In Fig. 4 G, shown pseudo-Error detection circuit 123 is finished 2 distances of I channel and Q channel by anticoincidence circuit 145,146, and NAND circuit obtains the NAND of the output of above-mentioned anticoincidence circuit 145 and 146.When 2 of I channel are " 00 " or " 11 " or Q channel 2 during for " 00 " or " 11 ", this circuit is output as " 1 ".This output inputs to measures circuit 124.
In these embodiments, the present invention is applied in the 16 level quadrature amplitude modulation (qam) radio transmission systems, but the present invention also is applicable to data transaction is become behind the multi-level signal from transmitting terminal to launch and obtain by analog-to-digital conversion any system of data at receiving terminal.
As explained above, the present invention judges the data meticulousr than data bits at receiving terminal with the multidigit bit, thus, only need from above-mentioned multidigit bit, can detect pseudo-error code, thereby only just can detect pseudo-error code with simple adjunct circuit, even when data bits increased, this circuit can be very not complicated yet.In addition, owing to only in the judgement moment of data data are monitored, so can access the accurate error rate.As long as it is suitable that the scope of pseudo-error rate is determined, the frequency that then produces pseudo-error code will reach enough precision, and can detect pseudo-error rate soon.In addition, owing to do not need to launch the particular module that pseudo-error rate detects, transmission capacity can not reduce.
Claims (39)
1, in a kind of transmission system that is used for, utilize a plurality of bits with the multi-level signal that data transaction becomes to have particular number of bits, at transmitting terminal it is sent then; And by the judgement of above-mentioned multi-level signal being produced these data again, be used for the multilevel signal monitor circuit of this kind transmission system, it is characterized in that it comprises at receiving terminal:
One analog to digital converter, it is used than the more a plurality of bits of described data bits and fine judges above-mentioned multi-level signal, thus the additional bits that described trickle judgement obtained comprises at least two bits;
One pseudo-error rate testing circuit, it is measured the frequency of above-mentioned additional bits and represents how far the quantization level of the described multi-level signal of incoming level distance of described analog to digital converter has.
2, according to the multilevel signal monitor circuit of claim 1, wherein said pseudo-error rate testing circuit comprises:
One pseudo-Error detection circuit, it detects a plurality of bits that indicate above-mentioned particular range;
One measures circuit, measures the frequency that detects in the above-mentioned pseudo-Error detection circuit.
3, according to the multilevel signal monitor circuit of claim 1, wherein said transmission system transmits the data of two systems with the method for multilevel quadrature amplitude modulation, and has a described analog to digital converter of system disposition and described pseudo-error rate testing circuit in above-mentioned two data systems at least.
4, according to the multilevel signal monitor circuit of claim 3, wherein said pseudo-error rate testing circuit comprises:
One pseudo-Error detection circuit detects the specific scope of described multidigit;
One measures circuit, measures the frequency that detects in the above-mentioned pseudo-code testing circuit.
5, according to the multilevel signal monitor circuit of claim 3, all provide described analog to digital converter one by one, and above-mentioned pseudo-error rate testing circuit comprises to two data systems:
One pseudo-Error detection circuit detects in the long numeric data that sends from above-mentioned two analog to digital converters and has at least a multidigit bit to indicate described particular range;
One measures circuit, detects the frequency of the judgement in the above-mentioned pseudo-Error detection circuit.
6, according to the multilevel signal monitor circuit of claim 2 or claim 4, wherein said pseudo-Error detection circuit comprises:
One first "AND" circuit, obtain above-mentioned a plurality of bits " with ";
A plurality of inverters make above-mentioned a plurality of bit anti-phase;
One second "AND" circuit, obtain above-mentioned a plurality of inverters output " with ";
An OR circuit, obtain above-mentioned first and second "AND" circuits output " or ".
7, according to the multilevel signal monitor circuit of claim 2 or claim 4, wherein said pseudo-Error detection circuit comprises:
A "AND" circuit, obtain above-mentioned multidigit " with ";
A NOR circuit obtains the nondisjunction of upper multidigit;
An OR circuit, obtain the output of above-mentioned "AND" circuit and OR circuit output " or ".
8, according to the multilevel signal monitor circuit of claim 2 or 4.Wherein said pseudo-Error detection circuit comprises:
An inverter makes the Must Significant Bit in the described multidigit anti-phase;
One with " circuit, obtain in the above-mentioned multidigit except the output of the remaining multidigit of Must Significant Bit and above-mentioned inverter " with ";
One first NOR circuit obtains to remove in the above-mentioned multidigit the remaining multidigit of Must Significant Bit and the nondisjunction of this inverter output;
One second NOR circuit obtains the nondisjunction of the output of the output of above-mentioned "AND" circuit and above-mentioned first NOR circuit;
9, according to the multilevel signal monitor circuit of claim 2 or 4, wherein said multidigit is 2, and described pseudo-Error detection circuit comprises that a realization is to above-mentioned 2 anticoincidence circuits that carry out exclusive-OR operation.
10, according to the multilevel signal monitor circuit of claim 5, wherein said pseudo-Error detection circuit comprises:
First and second "AND" circuits, they obtain described two analog to digital converters multidigit separately " with ";
First and second NOR circuits, they obtain the nondisjunction of the multidigit separately of described two analog to digital converters;
An OR circuit, obtain the output of above-mentioned first and second "AND" circuits and above-mentioned first and second NOR circuits output " or ".
11, according to the multilevel signal monitor circuit of claim 5, wherein, described multidigit is 2, and described pseudo-Error detection circuit comprises:
First and second anticoincidence circuits obtain their described 2 distances to described two analog to digital converters;
A NAND circuit obtains the NAND of the output of above-mentioned anticoincidence circuit.
12, according to the multilevel signal monitor circuit of claim 2 or 4, wherein said mensuration circuit comprises:
A counter is counted " 1 " or " 0 " of described testing circuit;
A timer makes above-mentioned counter export a count value during each is constant and makes this counter reset.
13, according to the multilevel signal monitor circuit of claim 2 or 4, wherein said mensuration circuit comprises an integrating circuit that the output of above-mentioned testing circuit is carried out integration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN85103949A CN85103949B (en) | 1985-05-22 | 1985-05-22 | Multilevel signal monitor circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN85103949A CN85103949B (en) | 1985-05-22 | 1985-05-22 | Multilevel signal monitor circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN85103949A CN85103949A (en) | 1986-11-19 |
| CN85103949B true CN85103949B (en) | 1988-09-21 |
Family
ID=4793543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN85103949A Expired CN85103949B (en) | 1985-05-22 | 1985-05-22 | Multilevel signal monitor circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN85103949B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI669918B (en) * | 2017-10-31 | 2019-08-21 | 北京集創北方科技股份有限公司 | Transmission circuit with adaptive sender equalizer adjustment function and communication device using the same |
-
1985
- 1985-05-22 CN CN85103949A patent/CN85103949B/en not_active Expired
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| Publication number | Publication date |
|---|---|
| CN85103949A (en) | 1986-11-19 |
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