CN85101533A - The integrated circuit (IC)-components that is used for digitallijed electronic apparatus - Google Patents

Abstract

This device comprises: a) polynary input.B) switching circuit that links to each other with said polynary input, be used for selecting any input signal by said polynary input.C) be used to control the ON-OFF control circuit of said switching circuit, select any input signal according to received selection signal.D) be used for will selected input signal being transformed into the A/D converter of corresponding serial digital signal from said switching circuit.And e) digital signal that links to each other that is used for that links to each other with said internal bus is delivered to said internal bus also selecting signal to deliver to the bus interface circuitry of said ON-OFF control circuit from said internal bus from said A/D converter.

Description

The integrated circuit (IC)-components that is used for digitallijed electronic apparatus

The present invention relates generally to can be used for internal circuit is by numerically controlled integrated circuit (IC) device such as electronic equipments such as television set, video tape recorder (VTR) and tape recorders, particularly relates to being applicable to that it regulates operation is externally to operate realization with the intrinsic internal bus of this system by computer.

Video and audio equipment, as digitized television set, video tape recorder (VTR) and tape recorder etc., all commercializations now.Most these digitizers use and CPU(CPU), memory and the common internal bus of other control circuit.The CPU normal operation period from memory, as the read only memory (ROM), for each circuit taking-up control signal valve of electronic equipment, is delivered to suitable circuit to the data of taking out by bus, so that the operation of control internal circuit again.In addition, CPU can also pass through the direct control instrument circuit of manual input signal with external keyboard or remote controller.

Above-mentioned internal bus normally twin-core or three cores.The twin-core internal bus comprises a data line and a clock transfer line.This twin-core type bus can be used for not examining and the clear 57-106 of disclosed Japanese patent application NO 262 communication systems of being announced.And three core buses comprise a data line, a clock transfer line and a so-called identification signal, and the latter is used for discerning the character from each data block of data line.

If in the combination of these electronic equipments that internal bus is housed and between turn(a)round, might make testing standardization, centralization and simplification, comprise that the minimizing of the total cost of producing cost can realize.

The purpose of this invention is to provide an integrated circuit, it is applicable in combination and inspection operation time test electronic equipment internal circuit internal bus system.

For electronic equipment provides an integrated circuit (IC)-components that can realize above-mentioned purpose.This distinctive integrated circuit (IC)-components comprises: a) polynary input, b) select a switching circuit of any individual signals that above-mentioned said polynary input imports respectively, c) ON-OFF control circuit of selecting an input signal according to the said switching circuit of selection signal controlling, d) A/D converter and e who selected input signal is converted to corresponding serial digital signal from said switching circuit) bus interface circuitry that is connected to said internal bus is delivered to the signal that is converted to numeral said internal bus and the signal of selecting is delivered to said ON-OFF control circuit from said internal bus from said A/D converter.

Used integrated circuit (IC)-components of the present invention on the electronic equipment of internal bus having, can control the single or multiple circuit of the integrated circuit (IC)-components of having packed into outer computer, the device of commanding behind the scenes.Therefore when combination and maintenance, can carry out test easily to the circuit of integrated circuit (IC)-components.Be effective when carrying out circuit judges.In addition, polynary electronic equipment can be with the test of common computer or pilot valve, thereby can realize the standardization of test macro and integrated.

By the description of the drawings, can have one to understand more completely to the present invention below, the reference number among the figure indicates corresponding element.

Fig. 1 is the simple block diagram that can adopt a kind of electronic equipment of the present invention;

Fig. 2 is a simple block diagram of the preferred plan of test television set;

Fig. 3 is the simple connection layout of the preferred plan of various electronic equipments being tested according to the present invention;

Fig. 4 has shown twin-core serial bus rules;

Fig. 5 has shown three core serial bus rules;

Fig. 6 is the simple block diagram of a bus transducer;

Fig. 7 is a sequential chart of explaining circuit working shown in Figure 6.

Can understand the present invention easily with reference to accompanying drawing.

Fig. 1 is the block diagram that can adopt a kind of electronic equipment of the present invention.

In Fig. 1,3, one CPU(CPU of 2, the second integrated circuit (IC)-components of first integrated circuit (IC)-components) 4 and memories 5 are installed in the electronic equipment 1.These circuit blocks are connected to each other by a bus 6.Bus 6 connector 7 outer with guiding to electronic equipment 1 is connected.The outer computer 8 that is used for testing equipment 1 is connected with connector 7 by another one bus 22.Computer 8 is linked display unit 9, for example a CRT monitor that shows test results.

Above-mentioned first integrated circuit (IC)-components 2 comprises bus interface 10, D/A (D/A) transducer 11, analog circuit A-E, switching circuit 12, control circuit 13 and mould/number (A/D) transducer 14.Bus interface 10 is delivered to D/A converter 11 and ON-OFF control circuit 13 to the digital controlled signal that receives from CPU4 by bus 6.Two kinds of control signals, promptly the control signal of circuit under test A-E and physical circuit A-E are the control signals of how to work, and all can discern.D/A converter 11 is analog signal with the conversion of signals of receiving and analog signal is guided into physical circuit A-E.ON-OFF control circuit 13 pushes corresponding contact position a-e with switch 2, and the output of physical circuit A-E is connected to A/D converter 14.A/D converter 14 is converted to corresponding serial digital to simulation output then, by bus interface 10 serial digital signal is turned back to bus 6 again.Foregoing circuit A-E is the object of CPU4 control and computer 8 tests.In these schemes, five kinds of different control circuits have been installed in integrated circuit (IC)-components 2.

Second integrated circuit (IC)-components 3 comprises bus interface 15, mould/number (A/D) transducer 16, switching circuit 17, the input 19,20,21 that ON-OFF control circuit 18 and switching circuit link to each other with external circuit.Above-mentioned bus interface 15 is connected with bus 6. Input 19,20,21 is connected with the output of three peripheral circuit F, G, H.These peripheral circuits F, G, H are split circuits, rather than integrated circuit and not controlled by CPU4.Input signal from peripheral circuit F, G, H is selected by switch 17 and on-off controller, is added on the bus 6 by A/D converter 16 and bus interface 15 again.

Below several sections explained the electronic equipment Assemble Duration and the maintenance period this system work.To come usefulness as test at the computer 8 that separates between Assemble Duration and turn(a)round, this point can be seen clearlyer.

Under the situation of combined test, operate a keyboard, to produce the numerical data of representing control signal as computer 8 manual input signals.These data are by bus 22, and connector 7 and bus 6 are delivered to first and second integrated circuit (IC)- components 2 and 3.

These data are latched in first integrated circuit (IC)-components 2 by bus interface 10.The data that are latched are converted to corresponding analog control signal by D/A converter 11, and deliver to circuit A-E.Circuit A-E is controlled to the output signal feature of control signal necessary operations state by the control signal that links.Output signal is converted to digital signal as a result, sends computer 8 back to by bus interface 10 and bus 6 and 22 again.Display unit 9 is presented at the test result of circuit A-E on the screen.These results can come comparison by the operator, so that know design specification, the operator can regulate input control signal by keyboard if necessary, so that draw desired output signal.

Confirm that with the image explicit representation circuit A-E is in after the operate as normal, operator's operation keyboard deposits the controlling value of circuit A-E at memory 5, uses as the reference value during the normal running.When electronic equipment 1 work, CPU4 reads the reference value that is write down from memory 5, and each circuit A-E carries out desired operation according to the data of being read.

On the other hand, peripheral circuit F, G, H must be controlled by the outside, to produce these signals of variation that output signal indicates their operating states, promptly received by contact point f, g, the h of switching circuit 17 respectively by input 19,20,21 by second integrated circuit (IC)-components 3.

ON-OFF control circuit 17 in turn, is at random selected contact point f, g, h according to the control signal of computer 8.The chosen input signal from circuit F-H converts digital signal to by A/D converter 16, delivers to computer 8 by bus interface 15 and bus 6,22 again.Then, display unit 9 is presented at the test result of peripheral circuit F, G, H on the screen.

Under the failure diagnosis situation between turn(a)round, directed maintenance computer 8 is connected with bus 22.The operator is by keyboard, and write at each circuit A-H that a specific address selects is which circuit of circuit A-H actually.The requirement of answering circuit to select, computer 8 from being stored in memory 5, takes out suitably input controlling value at Assemble Duration as mentioned above, exports a control signal again to physical circuit (referring to circuit A-E) and switching circuit 13 or 18.Yet by keyboard, order computer 8 is by the electric current output sampling of 22,6 pairs of definite circuit of bus.Computer 8 is keeping the output level pattern of the indication related circuit A-H proper operation that has been equipped with in advance in the software kit that links.Computer 8 will be compared with corresponding stored level mode from the circuit output that bus 22 receives, so that the state of the circuit that diagnosis is determined.Result relatively is presented on the display unit 9.If all circuit have all been carried out aforesaid operations, faulty circuit both made, and also can be positioned.

Though in the scheme of being lifted, computer 8 is used to test circuit A-H between combination and turn(a)round, one stored test program and all necessary reference data memory can with combine by remote control and memory 5 apparatus operating, and circuit A-H can be peeked by bus 6 by this specific remote-controlled test device according to above-mentioned program.

Fig. 2 can adopt the television set frame circuit diagram that internal bus is arranged of the present invention.Among Fig. 2, that identical with number among Fig. 1 is CPU4, memory 5, bus 6,22 and computer 8.

In scheme shown in Figure 2, be audio frequency processing circuit 25 with respect to Be Controlled circuit A-F shown in Figure 1, video control circuit 26, video processing circuits 27 and deflection control circuit 28.In normal running, CPU4 controls a PLL(phase-locked loop) circuit, make above-mentioned each circuit 25-28 and tuner 31 synchronous according to the instruction of sending by keyboard 29 or remote controller.Frequency tuning, volume adjusting, image adjustment or the like manually selective value can show on display unit 33.In Fig. 2, remote signal receiver of digital 34 expressions, intermediate frequency amplifier of digital 35 expressions, the deflecting coil of digital 36,37 expression cathode ray tubes 40, digital 38 expression audio-frequency power amplifiers, digital 39 expression video power amplifiers, and digital 40 expression cathode ray tube (CRT)s.

Computer 8 or controller 30 can be used to make up and test between turn(a)round or adjusting, and be described with reference to Fig. 1.The operations factor of require regulating comprises with the electron beam parameter being example the linearity, width and fixed point distortion that level and vertical both direction are just arranged or the like, and adjustment of color comprises that white balance and R(are red), G(is green), B(indigo plant) cut-off point of signal and the grid offset of driving and CRT40 save.

In addition, the various data of testing gained between turn(a)round can be recorded in the memory, peripheral hardware recording medium, perhaps can also deliver to concentrate by telephone wire and compile the control computer.This central computer is then formulated file according to the data of each inspecting state, and these files are offered departments such as design, exploitation, production, material and maintenance.

Fig. 3 represents to adopt winding diagram of the present invention, comprising television set 45, and video tape recorder (VTR) 46, and tape recorder 47.They all have one as shown in Figure 1 internal bus 6 be connected with being used to test with the computer 8 of possible adjusting.In such cases, used computer 8 is exactly commercially available personal computer.According to the kind of equipment to be measured 45,46,47, can select tv test cassette tape unit 48, video measurement cassette tape unit 49 and/or tape recorder boxlike test magnetic tape station 50 to be connected with computer 8.Each cassette tape unit 48,49,50 comprises a data-medium, as tape, diskette or keep storing specially and satisfying a cover program of each testing of equipment and adjusting and the ROM of data.In addition, having covered 52,53,54 special equipment keyboard can be used as the keyboard of computer 8 and is equipped with.Do not draw among computer 8 bus 6(Fig. 3 by bus 22 and connector 7 and each equipment) be connected.

Because of in these schemes, as long as change software, just can test multiple different electronic equipment with computer 8 according to device category, its test and adjusting operation are estimated and can also can be accomplished standardization fully as computer hardware and interconnection.

Explained test operation above, the data transaction between twin-core bus rules and the three core bus rules will be described below.As mentioned above, twin-core and three core serial buses have been used as internal bus usually recently.

Fig. 4 represents the data packet form by twin-core bus transmission signals.First transmission line of twin-core bus transmits serial data (Bits Serial) D ₂, second transmission line be transmission clock signal CL then ₂Each packet comprises: a) designation data is unwrapped the first signal of beginning; B) seven bit address signals of a distribution control circuit specific address; C) data are delivered to definite control circuit or the Be Controlled circuit peek from determining below the R/W(read/write) signal, indication; D) signal ACK(acknowledge character), the Be Controlled circuit that the notice computer is determined has been received data; E) represent 8 bit data of regulated value; F) desired n sub data packets, each subdata bag are 8 ack signals that add; G) a bit stop signal of one one.

Fig. 5 represents by three core buses signal form to be transmitted.

Its first transmission line transmits serial data D ₃, second transmission line transmits a clock signal C L ₃, and the 3rd transmission line transmits identification signal ID, discerns the existing serial data D that is encoded to ₃Information, the type of address or data.

Each packet begins with one initial signal, and it drives identification signal ID and becomes the following D that passes through line of low (level) indication ₃8 bit data represent an address.8 bit address back are immediately following the data of two octets.During whole back sixteen bit data transmitted, identification signal was high (level), then, becomes low (level) once more of short durationly.At last, the D of warp ₃Obtain the position of rest that an expression packet is ended, turn back to its high level again.

Fig. 6 represents that the conversion of signals that will transmit by the twin-core bus is the scheme according to qualifications of the bus conversion of signal that can be compatible with three core bus rules.Fig. 7 is the time diagram of bus transducer shown in Figure 6.

In Fig. 6 and Fig. 7, serial data D ₂Be connected with an input 61, and clock line CL as shown in Figure 4 ₂Be connected with another input 62.At first, as data D ₂In an initial signal by initial/when stopping detection circuit 63 and detecting, then the output Q of circuits for triggering (FF) 64 rises to " H " (height) level.The reset terminal (R) of shift register 65 sum counters 66 is connected with the Q of circuits for triggering 64 output, resets in response to the rising edge of Q output.When these circuit 65,66 were reset, shift register 65 was at data terminal and clock CL ₂Synchronously, begin to read the serial bit D that receives through door 67 ₂, unison counter 66 beginning counting clock pulse CL ₂Encoder 68 receives the parallel count value and the designation data bag D of one 5 bit wide from counter 66 ₂The output pulse of important position-counting position specifically is exactly 8-, 9-, and 17-and 18-digit pulse correspond respectively to the output pulse of R/W position, first ACK position, second ACK position and position of rest.These four output lines are connected with each logical circuit in the bus transducer.Particularly, control circuit 69 directly receives the 8th digit pulse, receives the 9th and the 18th digit pulse by door 70.Control circuit 69 produces a gating signal S ₀, 67 pairs of the 9th and the 18th digit pulse conductings of its feasible door, and to the 8th not conducting of digit pulse.This is for from packet D ₂In, R/W and first ACK position are screened, will describe in detail below.

Be sent to and door 72 from the 17th digit pulse of encoder 68, it also receives the inverted phase clock pulse CL of the phase inverter 71 that links to each other from the clock end c with shift register 65 ₂Output signal through " with " is sent to the set end of latch 73, as an asserts signal S ₁Asserts signal hereto, 15 significant positions of latch 73 locking serial datas, just, seven bit address and eight bit data remain in the shift register 65.Then, these 15 by the data transaction ROM(read only memory) 74 be converted into 16 forms that are used for three core buses.

18 digit pulses from encoder 68 are added to another and door 75, and it also receives the inverted phase clock pulse CL from phase inverter 71 ₂From being sent to the set end S and the clock signal CL of another shift register 76 through the output pulse of " with " with door 75 ₃With the generator 77 of identification id signal, as they asserts signal S ₂Shift register 76 obtains asserts signal S ₂, just take out the data changed from ROM74.

When initial/when stopping detection circuit 63 and detecting stop signal, the Q of circuits for triggering 64 output dropping to " L " (low) level.Above-mentioned signal generator 77 produces clock pulse (string) CL for three core buses ₃With an identification signal ID.Clock pulse frequency on request is from output 79 output, and is used for reading successively the content of shift register 76.Identification signal ID is by another output 80 outputs of directly drawing from signal generator 77.At last, the content of shift register 76, just 8 address and 8 bit data are exported serially by another output 78.

Except above-mentioned being used for is transformed into data the example of form bus transducer of three core systems from the twin-core system, also can select other the bus transducer that is used for data are transformed into from three core systems the form of twin-core system for use.Should notice that the bus 22 that is connected with outer computer 8 and the internal bus 6 of each electronic equipment must be twin-cores simultaneously, perhaps be three cores simultaneously.In addition, be used for the signal generator of twin-core system as shown in Figure 4, and be as shown in Figure 5 this generator that is used for three core systems can be arranged in computer 8 and the electronic equipment that adopted as requested between.The computer of a top grade can be used for optionally extracting the signal of twin-core, three cores and other system.Can certainly be with being that the signal converter that the conversion of twin-core/three cores designs replaces.Above-mentioned bus transducer can be installed within the electronic equipment.

Claims (5)

1, the integrated circuit (IC)-components that is used for electronic equipment is characterized in that integrated circuit (IC)-components comprises:

A) polynary input;

B) being used to of linking to each other with said polynary input selected the switching circuit of any input signal of said polynary input;

C) be used to control the ON-OFF control circuit of selecting the said switching circuit of any input signal according to received selection signal;

D) be used for will selected input signal being converted to the A/D converter of corresponding serial digital signal from said switching circuit;

E) link to each other with said internal bus, be used for the digital signal that connects is delivered to said internal bus from said A/D converter, will select signal to deliver to the bus interface circuitry of ON-OFF control circuit from said internal bus.

2, according to the integrated circuit (IC)-components of claim 1, it is characterized in that a polynary circuit is connected with the said polynary input of integrated circuit (IC)-components respectively, so that the output signal of each said polynary circuit is delivered to said switching circuit by corresponding input.

3,, it is characterized in that said polynary circuit is the split circuit that can use manual adjustments to its output signal according to the integrated circuit (IC)-components of claim 2.

4,, it is characterized in that computer is connected with the said internal bus that is used for testing by said bus interface circuitry the concrete function of said polynary circuit according to the integrated circuit (IC)-components of claim 2.

5, according to the integrated circuit (IC)-components of claim 2, combine with various types of said electronic equipments, the said internal bus that it is characterized in that computer and each electronic equipment links together all, is used for testing by said bus interface circuitry the concrete function of said polynary circuit.

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