CN2912120Y

CN2912120Y - Data discriminating circuit for clock data restoring circuit

Info

Publication number: CN2912120Y
Application number: CN 200620074786
Authority: CN
Inventors: 陈莹梅; 王志功
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2006-07-10
Filing date: 2006-07-10
Publication date: 2007-06-13
Anticipated expiration: 2016-07-10

Abstract

The utility model relates to a data discrimination circuit in clock data recovery circuit, in particular in clock data recovery circuit of optical fiber communication network and modern data communication system, the circuit is a lead lag discrimination circuit (2) of composite structure, which comprises a first exclusive-or gate (21), a second exclusive-or gate (22), a third exclusive-or gate (23), a fourth exclusive-or gate (24), a first 2: 1 selector (25) and a second 2: 1 selector (26); wherein, an output terminal of the first exclusive-or gate (21), the fourth exclusive-or gate (24) is connected with an input terminal of the second 2: 1 selector (26), an output terminal of the second exclusive-or gate (22), the third exclusive-or gate (23) is connected with input terminal of the first 2: 1 selector (25), an output terminal of the first 2: 1 selector (25) is output terminal (E) of the leading signal, output terminal of the second 2: 1 selector (26) is output terminal (L) of the lag signal. The circuit has the advantages of simple overall circuit structure, few components, low cost and low overall power consumption.

Description

Be applied to the data discriminator circuit of clock data recovery circuit

Technical field

The utility model is the data discrimination method that is applied in the clock data recovery circuit of fiber optic communication network and modern data communication systems, is based on a kind of data discrimination method of the over-sampling clock and data recovery technology of widely used phase-locked ring type recently.

Background technology

The world strides forward to informationized society, and telecommunications network, computer network and Internet net develop explosively, and the Large scale construction of information superhighway is extremely urgent.Optical fiber communication is because plurality of advantages such as its capacity is big, long transmission distance, saving resource, anti-interference, radioresistance are obtaining application more and more widely.Under these circumstances, the research of optical fiber communication integrated circuit has become focus.At present, extensively build in worldwide and use based on the SDH (Synchronous Digital Hierarchy) (SDH) and the Synchronous Optical Network (SONET) of optical fiber transmission network, the research of optical fiber communication integrated circuit is to the integrated level development of higher speed and Geng Gao.

Along with the lifting of system's speed, technology can not satisfy the designing requirement of ultrahigh speed circuit, and especially high-speed clock and data recovery circuit is the design bottleneck of optical communication receiver and modern data communication systems.Therefore in recent years, the oversampling technique of phase-locked loop structures has obtained extensive use in the clock and data recovery circuit, the clock of its employing half frequency or 1/4th frequencies, leggy is surveyed the phase place of input data and the variation of frequency, the clock of employing leggy can reduce the operating frequency of circuit such as phase discriminator, oscillator, brings the more freedom degree for circuit structure, process choice.

Implementation method for over-sampling lead-lag discriminator circuit 2 had multiple in the past, document [1-3] sees reference, the common configuration complexity, bring difficulty to circuit design, the more important thing is that lead-lag discriminator circuit structure is asymmetric, between clock that recovers and data, introduce the systematic phase error that to eliminate, and strengthened the overall power of circuit.

Summary of the invention

Technical problem: the purpose of this utility model just provides a kind ofly can eliminate data discriminator circuit that is applied to clock data recovery circuit and the data discrimination method thereof that device is few, cost is low, overall power consumption is low that the clock that recovers and the systematic phase error between the data, overall circuit are simple in structure, use.

Technical scheme: the data discriminator circuit that is applied to clock data recovery circuit of the present utility model, by the lead-lag discriminator circuit of first XOR gate, second XOR gate, the 3rd XOR gate, the 4th XOR gate, the one 2: 1 selector and the 22: 1 selector formation combining structure; Wherein, the input of output termination the 22: 1 selector of first XOR gate, the 4th XOR gate, the input of output termination the one 2: 1 selector of second XOR gate, the 3rd XOR gate, the output of the one 2: 1 selector is the anticipating signal output, and the output of the 22: 1 selector is the delay signal output.

The data discrimination method that is applied to the data discriminator circuit of clock data recovery circuit adopts first XOR gate, second XOR gate, the 3rd XOR gate, the 4th XOR gate, the one 2: 1 selector and the 22: 1 selector to constitute the lead-lag discriminator circuit of combining structure, i.e. the six tunnel input data " a.b.c that obtain with the leggy sample circuit over-sampling of front end ₁.c ₂.d.e " as the data input pin of first XOR gate, second XOR gate, the 3rd XOR gate, the 4th XOR gate; clock is as the input end of clock of the one 2: 1 selector and the 22: 1 selector; by the one 2: 1 selector output anticipating signal, the 22: 1 selector lag output signal.The working clock frequency of the one 2: 1 selector and the 22: 1 selector is to import 1/2nd of data bit-rate in the system.

The speed of clock is decided to be half of data rate, and promptly clock C0 and the C90 with two-way phase phasic difference 90 degree samples to data data.To the data " a.b.c that samples out ₁.c ₂.d.e " differentiate that combination draws the lead-lag logic, and the position middle data a.c that samples out can be used as the result of data decision, as the data that recover, realizes 1: 2 tap simultaneously.

The present invention adopts the lead-lag discriminator circuit of first XOR gate, second XOR gate, the 3rd XOR gate, the 4th XOR gate, the one 2: 1 selector and the 22: 1 selector formation combining structure, i.e. the six tunnel input data " a.b.c that obtain with leggy sample circuit over-sampling ₁.c ₂.d.e " as the data input pin of XOR gate, wherein data are imported data " d, c ₁" as the data input pin of first XOR gate, data " d, e " are as the data input pin of second XOR gate, data " c ₂, b " as the data input pin of the 3rd XOR gate, data " a, b " are as the data input pin of the 4th XOR gate.

Beneficial effect:

A) because circuit structure of the present utility model is symmetrical fully, eliminated systematic phase error fully, promptly ideally, the clock that recovers and the phase place of data are aimed at fully, and phase difference is zero.

B) over-sampling phase discriminator lead-lag discriminator circuit of the present utility model and comparing in the past, not only the data that sampling is obtained are carried out logical combination, and introduced selector with clock control, and clock is the original generation of oscillator in the system, through new like this invention, circuit structure is simplified greatly, simplified annexation, reduced the device that uses, made to be easy to the whole system compact conformation realize.As with list of references 1 (Jonathan E.Rogers and John R.Long. " A 10Gb/s CDR/DEMUX With LC Delay Line VCOin 0.18-um CMOS " IEEE Journal of Solid-State Circuits, VOL.37, NO.12, DEC 2002) in the lead-lag discriminator circuit of the labyrinth that in the past adopted, the circuit that is Fig. 4 is compared, this circuit has adopted 21 modular units, and the present invention has only adopted 6 modular units.List of references 2 (Mario Reinhold, Claus Dorschky, and Eduard Rose et al. " A Fully Integrated 40-Gb/s Clock and DataRecovery IC With 1:4 DEMUX in SiGe Technology " IEEE Journal of Solid-State Circuits, VOL.36, NO.12, DEC 2001) in discriminator circuit more complicated too, list of references 3 (GeorgeGeorgiou et al. " Clock and Data Recovery IC for 40-Gb/s Fiber-Optic Receiver " IEEE Journal of Solid-State Circuits, VOL.37, NO.9, SEP 2002) in adopt what be that the clock sampling of full range goes out is 3 data, 6 data if the employing semi-frequency clock is sampled out do not have advantage equally on the structure.

C) owing to making the speed of circuit clock Ck reduce half, according to dynamic power consumption P _d=C _LFV ² _Dd(C _LBe load capacitance, f is a clock frequency, V _DdBe supply voltage), this structure has reduced power consumption, selects to bring more freedom to circuit structure simultaneously, has reduced the requirement to device, can select more cheap technology, has reduced cost.

The utility model through the flow checking, is tested respond well.

Description of drawings

Fig. 1 is the general charge pump phase lock loop structural representation with leggy sampling function, and leggy sample circuit 1, lead-lag discriminator circuit 2, charge pump 3, oscillator 4 are wherein arranged.

Fig. 2 is the sample waveform figure of the clock of half rate to data, adopts the clock C0 and the C90 of two-way phase phasic difference 90 degree that data Data is sampled.

Fig. 3 is half rate clock C0 and the C90 sample circuit figure to data Data, and comprising 16 latchs, Data is a data input pin, and C0 and C90 are input end of clock, the data output end that a, b, c1, c2, d, e obtain for sampling.

Fig. 4 is the lead-lag discriminator circuit example of the labyrinth that adopts in the list of references 1, and the inverter that adds data terminal is totally 21 unit.

Fig. 5 is the electrical schematic diagram of lead-lag discriminator circuit 2 of the present utility model, wherein has: first XOR gate 21, second XOR gate 22, the 3rd XOR gate 23, the 4th XOR gate the 24, the 1: 1 selector the 25 and the 22: 1 selector 26, anticipating signal output E, delay signal output L.The first anticipating signal E1, the second anticipating signal E2, the first delay signal L1, the second delay signal L2.

Specific implementation

The data discriminator circuit that is applied to clock data recovery circuit of the present utility model is made of the lead-lag discriminator circuit 2 of combining structure first XOR gate 21, second XOR gate 22, the 3rd XOR gate 23, the 4th XOR gate the 24, the 1: 1 selector the 25 and the 22: 1 selector 26; Wherein, the input of output termination the 22: 1 selector 26 of first XOR gate 21, the 4th XOR gate 24, the input of output termination the one 2: 1 selector 25 of second XOR gate 22, the 3rd XOR gate 23, the output of the one 2: 1 selector 25 is anticipating signal output E, and the output of the 22: 1 selector 26 is delay signal output L.

The data discrimination method that is applied to the data discriminator circuit of clock data recovery circuit adopts first XOR gate 21, second XOR gate 22, the 3rd XOR gate 23, the 4th XOR gate the 24, the 1: 1 selector the 25 and the 22: 1 selector 26 to constitute the lead-lag discriminator circuit 2 of combining structures, i.e. the six tunnel input data " a.b.c that obtain with leggy sample circuit 1 over-sampling of front end ₁.c ₂.d.e " as the data input pin of first XOR gate 21, second XOR gate 22, the 3rd XOR gate 23, the 4th XOR gate 24; clock Ck is as the one 2: 1 selector the 25 and the 22: the input end of clock of 1 selector 26; by the one 2: 1 selector 25 output anticipating signals, the 22: 1 selector 26 lag output signals.The one 2: 1 selector the 25 and the 22: the working clock frequency of 1 selector 26 is to import 1/2nd of data bit-rate in the system.

Wherein Data and Ck are the input of leggy sample circuit 1, the speed of Ck is 1/2nd of input data Data speed, and the data a that samples out, b, c, d, e offer that lead-lag discriminator circuit 2 draws anticipating signal E and delay signal L offers charge pump.

More than all circuit can adopt deep submicron integrated circuit technology, for example adopt 0.25 micrometre CMOS integrated circuit technology to realize.

Claims

1, a kind of data discriminator circuit that is applied to clock data recovery circuit is characterized in that this circuit is made of the lead-lag discriminator circuit (2) of combining structure first XOR gate (21), second XOR gate (22), the 3rd XOR gate (23), the 4th XOR gate (24), the one 2: 1 selector (25) and the 22: 1 selector (26); Wherein, the input of output termination the 22: 1 selector (26) of first XOR gate (21), the 4th XOR gate (24), the input of output termination the one 2: 1 selector (25) of second XOR gate (22), the 3rd XOR gate (23), the output of the one 2: 1 selector (25) is anticipating signal output (E), and the output of the 22: 1 selector (26) is delay signal output (L).

2, clock data recovery circuit data discrimination method according to claim 1, the working clock frequency that it is characterized in that the one 2: 1 selector (25) and the 22: 1 selector (26) are to import 1/2nd of data bit-rate in the system.