CN101562490B - Method for clock synchronization as well as equipment frame and system thereof - Google Patents
Method for clock synchronization as well as equipment frame and system thereof Download PDFInfo
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Abstract
The invention discloses a method for clock synchronization, an equipment frame and a system thereof and pertains to the field of communication. The method comprises the steps of: receiving a first interconnection message sent by a clock synchronization peripheral node equipment frame through an inter-frame interconnecting interface of the equipment frame, determining a uniform clock synchronization reference message according to the first interconnection message and sending the uniform clock synchronization reference message to the clock synchronization peripheral node equipment frame by the inter-frame interconnecting interface of the equipment frame. The first interconnection message comprises first business data and the clock synchronization reference message inside the clock synchronization peripheral node equipment frame. The system comprises the clock synchronization peripheral node equipment frame and a clock synchronization central node equipment frame. The invention utilizes an existing inter-frame interconnecting channel to carry the clock synchronization reference message while sending business data, so as to realize the clock synchronization among a plurality of equipment frames without arranging special circuits additionally, thus getting rid of the defect that clock synchronization is limited by hardware and being more flexible for realization.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a method, an apparatus frame, and a system for clock synchronization.
Background
With the rapid development of broadband telecommunication networks towards full IP (Internet Protocol), large message routing switching devices, such as: gigabit routers, Terabit routers, etc., have begun to evolve from single-frame systems to multi-frame cluster systems.
Multi-box cluster systems typically interconnect using Full Mesh or Multi-Star architectures. However, in the clock synchronization process, a star logic structure is generally adopted, and one or two device blocks are designated as clock synchronization central nodes, and the other device blocks are designated as clock synchronization peripheral nodes. At present, there are two main methods for realizing clock synchronization among multiple frames:
the first method is that the equipment frame as the clock synchronization center node is interconnected to the equipment frames of all other clock synchronization peripheral nodes in the system by using special external synchronization output and input interfaces, and then the equipment frame of the clock synchronization center node transmits clock synchronization information to the equipment frames of all clock synchronization peripheral nodes. When the number of the device frames in the multi-frame cluster system increases, the device frame of the clock synchronization center node needs to provide a large number of special external synchronization input and output interfaces for connecting the device frames of the clock synchronization peripheral nodes.
The second method is that all the device frames in the multi-frame cluster system are connected to the same BITS synchronous device by using special external synchronous output and input interfaces, and each device frame in the system acquires clock synchronous signals from the BITS synchronous device. When the number of device frames in the multi-frame cluster system increases, the BITS synchronization device needs to provide a dedicated external synchronization input and output interface with increased synchronization for interconnecting all the device frames in the system.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
clock synchronization in the multi-frame cluster system needs special external synchronous input and output interfaces, when the number of equipment frames increases, the number of special external synchronous output and input interfaces also increases synchronously, and hardware is difficult to realize.
Disclosure of Invention
In order to enable clock synchronization in a multi-frame cluster system to get rid of hardware limitation, the embodiment of the invention provides a clock synchronization method, an equipment frame and a system. The technical scheme is as follows:
a method of clock synchronization, the method comprising:
receiving first interconnection information sent by a clock synchronization peripheral node device frame through an inter-frame interconnection interface of the device frame, wherein the first interconnection information comprises: the first service data and clock synchronization reference information inside the clock synchronization peripheral node equipment frame;
according to the clock synchronization reference information in the clock synchronization peripheral node equipment frame, unified clock synchronization reference information is determined; sending second interconnection information to the clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the equipment frame, wherein the second interconnection information comprises second service data and the unified clock synchronization reference information;
or,
according to the clock synchronization reference information in the clock synchronization peripheral node equipment frame and the clock synchronization reference information in the equipment frame, unified clock synchronization reference information is determined, the unified clock synchronization reference information is sent to equipment in the equipment frame, second interconnection information is sent to the clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the equipment frame, and the second interconnection information comprises second service data and the unified clock synchronization reference information.
A method of clock synchronization, the method comprising:
through the inter-frame interconnection interface of the equipment frame, first interconnection information is sent to the clock synchronization center node equipment frame, and the first interconnection information comprises: the first service data and clock synchronization reference information inside the equipment frame;
receiving, by an inter-frame interconnection interface of the local equipment frame, second interconnection information sent by the clock synchronization center node equipment frame, where the second interconnection information includes second service data and unified clock synchronization reference information, where the unified clock synchronization reference information is determined by the clock synchronization center node equipment frame according to clock synchronization reference information inside the local equipment frame and clock synchronization reference information inside the clock synchronization center node equipment frame in the first interconnection information, or determined by the clock synchronization center node equipment frame according to clock synchronization reference information inside the local equipment frame in the first interconnection information;
and acquiring unified clock synchronization reference information in the second interconnection information.
A device box, the device box comprising:
a receiving unit, configured to receive, through an inter-frame interconnection interface of the device frame, first interconnection information sent by a clock synchronization peripheral node device frame, where the first interconnection information includes: the first service data and clock synchronization reference information inside the clock synchronization peripheral node equipment frame;
a determining unit, configured to determine unified clock synchronization reference information according to the clock synchronization reference information in the device frame and the clock synchronization reference information in the clock synchronization peripheral node device frame in the first interconnection information received by the receiving unit, or determine unified clock synchronization reference information according to the clock synchronization reference information in the clock synchronization peripheral node device frame in the first interconnection information received by the receiving unit;
and the sending unit is used for sending second interconnection information to the clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the equipment frame, wherein the second interconnection information comprises second service data and the unified clock synchronization reference information determined by the determining unit.
A device box, the device box comprising:
a sending unit, configured to send first interconnection information to a clock synchronization center node device frame through an inter-frame interconnection interface of the device frame, where the first interconnection information includes: the first service data and clock synchronization reference information inside the equipment frame;
a receiving unit, configured to receive, through an inter-frame interconnection interface of the device frame, second interconnection information sent by the clock synchronization center node device frame, where the second interconnection information includes second service data and unified clock synchronization reference information, where the unified clock synchronization reference information is determined by the clock synchronization center node device frame according to clock synchronization reference information inside the device frame and clock synchronization reference information inside the clock synchronization center node device frame in the first interconnection information, or determined by the clock synchronization center node device frame according to clock synchronization reference information inside the device frame in the first interconnection information;
and the acquisition unit is used for acquiring the unified clock synchronization reference information in the second interconnection information received by the receiving unit.
A system for clock synchronization, the system comprising: clock synchronization peripheral node equipment frames and clock synchronization central node equipment frames;
the clock synchronization peripheral node device frame is configured to send first interconnection information to the clock synchronization center node device frame through an inter-frame interconnection interface of the clock synchronization peripheral node device frame, where the first interconnection information includes: the first service data and clock synchronization reference information inside the clock synchronization peripheral node equipment frame;
the clock synchronization center node equipment frame is used for receiving the first interconnection information sent by the clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the clock synchronization center node equipment frame, determining unified clock synchronization reference information according to the first interconnection information, and sending second interconnection information to the clock synchronization peripheral node equipment frame through the inter-frame interconnection interface of the clock synchronization center node equipment frame, wherein the second interconnection information comprises second service data and the unified clock synchronization reference information;
when the clock synchronization central node equipment frame determines unified clock synchronization reference information according to the first interconnection information, the clock synchronization central node equipment frame is used for determining the unified clock synchronization reference information according to the clock synchronization reference information in the clock synchronization peripheral node equipment frame; or, the method is used for determining unified clock synchronization reference information according to the clock synchronization reference information inside the clock synchronization peripheral node equipment frame and the clock synchronization reference information inside the clock synchronization central node equipment frame.
The technical scheme provided by the embodiment of the invention has the beneficial effects that: the clock synchronization center node equipment frame receives the interconnection information which is sent by the clock synchronization peripheral node equipment frame and comprises the service data of the equipment frame and the clock synchronization reference information in the equipment frame through an inter-frame interconnection interface of the clock synchronization center node equipment frame, determines the unified clock synchronization reference information according to the interconnection information, and sends the unified clock synchronization reference information to the clock synchronization peripheral node equipment frame, so that the purpose of clock synchronization among multiple equipment frames is achieved by utilizing an existing interconnection channel and carrying the clock synchronization reference information when the service data is transmitted, a special line does not need to be additionally arranged, the defect that the clock synchronization is limited by hardware is overcome, and the clock synchronization is more flexible to achieve.
Drawings
Fig. 1 is a flowchart of a clock synchronization method provided in embodiment 1 of the present invention;
fig. 2 is a flowchart of a method for clock synchronization according to embodiment 2 of the present invention;
fig. 3 is a schematic diagram of a Full Mesh architecture provided in embodiment 3 of the present invention;
FIG. 4 is a schematic diagram of a Multi-Star architecture provided in embodiment 3 of the present invention;
fig. 5 is a flowchart of a method for inter-frame clock synchronization under the Full Mesh architecture according to embodiment 3 of the present invention;
fig. 6 is a schematic diagram of a SERDES structure provided in embodiment 3 of the present invention;
fig. 7 is a schematic diagram of internal functional logic of a clock synchronization peripheral node device block suitable for all devices in a Full Mesh cluster and a Multi-Star cluster according to embodiment 3 of the present invention;
fig. 8 is a schematic diagram of internal functional logic of a clock synchronization center node device block in a Multi-Star cluster according to embodiment 3 of the present invention;
FIG. 9 is a block diagram of an apparatus according to embodiment 4 of the present invention;
FIG. 10 is a schematic diagram of a determining unit structure provided in embodiment 4 of the present invention;
fig. 11 is a schematic structural diagram of a sending unit provided in embodiment 4 of the present invention;
FIG. 12 is a block diagram of an apparatus provided in embodiment 5 of the present invention;
FIG. 13 is another schematic structural diagram of an apparatus block provided in embodiment 5 of the present invention;
fig. 14 is a schematic diagram of a system structure for clock synchronization provided in embodiment 6 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example 1
Referring to fig. 1, the present embodiment provides a clock synchronization method, including:
101: receiving first interconnection information sent by a clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the equipment frame, wherein the first interconnection information comprises: the first service data and clock synchronization reference information inside the clock synchronization peripheral node equipment frame;
102: determining unified clock synchronization reference information according to the first interconnection information;
103: and sending the unified clock synchronization reference information to the clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the equipment frame.
According to the method provided by the embodiment, the clock synchronization center node equipment frame receives the interconnection information which is sent by the clock synchronization peripheral node equipment frame and comprises the service data of the equipment frame and the clock synchronization reference information in the equipment frame through the inter-frame interconnection interface of the clock synchronization center node equipment frame, determines the unified clock synchronization reference information according to the interconnection information, and sends the unified clock synchronization reference information to the clock synchronization peripheral node equipment frame, so that the purpose of clock synchronization among multiple equipment frames is achieved by utilizing the existing inter-frame interconnection channel and carrying the clock synchronization reference information when the service data is transmitted, a special line does not need to be additionally arranged, the defect that the clock synchronization is limited by hardware is overcome, and the realization is more flexible.
Example 2
Referring to fig. 2, the present embodiment provides a clock synchronization method, including:
201: through the inter-frame interconnection interface of the equipment frame, first interconnection information is sent to the clock synchronization center node equipment frame, and the first interconnection information comprises: the first service data and clock synchronization reference information inside the equipment frame;
202: receiving second interconnection information sent by the clock synchronization center node equipment frame through an inter-frame interconnection interface of the equipment frame, wherein the second interconnection information comprises second service data and unified clock synchronization reference information, and the unified clock synchronization reference information is determined by the clock synchronization center node equipment frame according to the first interconnection information;
203: and acquiring unified clock synchronization reference information in the second interconnection information.
According to the method provided by the embodiment, the clock synchronization peripheral node equipment frame receives the interconnection information which is sent by the clock synchronization central node equipment frame and comprises the service data and the unified clock synchronization reference information of the equipment frame through the inter-frame interconnection interface of the clock synchronization peripheral node equipment frame, and obtains the unified clock synchronization reference information in the interconnection information, so that the purpose of clock synchronization among multiple equipment frames is achieved by utilizing the existing inter-frame interconnection channel and carrying the clock synchronization reference information when the service data is transmitted, a special line does not need to be additionally arranged, the defect that the clock synchronization is limited by hardware is overcome, and the clock synchronization peripheral node equipment frame is more flexible to realize.
Example 3
The embodiment provides a clock synchronization method, which is mainly used for clock synchronization among equipment frames in a multi-frame cluster system.
Multi-box cluster systems typically interconnect using Full Mesh or Multi-Star architectures. In the Full Mesh architecture, as shown in fig. 3, there is a direct interconnection path between any device block and other device blocks. In the Multi-Star architecture, as shown in fig. 4, the central device frame and the peripheral device frame are divided into two types, a direct interconnection path exists between the peripheral device frame and the central device frame, and the peripheral device frames are only indirectly interconnected through the central device frame.
No matter a Full Mesh Multi-box architecture or a Multi-Star Multi-box architecture is adopted, in terms of clock synchronization processing, the embodiment adopts a Star-shaped logic structure, one or two device boxes are used as clock synchronization central nodes (if two device boxes are used as clock synchronization central nodes at the same time, the two device boxes are generally used for reliability and are redundant and backup with each other), and other device boxes are used as clock synchronization peripheral nodes. In the Multi-Star Multi-frame architecture, the embodiment selects a center device frame as a clock synchronization center node device frame, and all peripheral device frames as clock synchronization peripheral node device frames. In this embodiment, the clock synchronization center node device box and the clock synchronization peripheral node device box both refer to device boxes logically located at the center and the periphery.
Taking the Full Mesh multi-frame cluster system as an example, referring to fig. 5, the specific flow of clock synchronization is as follows:
301: the clock synchronization peripheral node equipment frame acquires clock synchronization reference information inside the equipment frame;
specifically, clock synchronization information from the service interface of the equipment frame is received, and one of the clock synchronization information is selected as clock synchronization reference information inside the equipment frame.
302: carrying the clock synchronization reference information in serial clock information;
303: forming first interconnection information by the serial clock information and first service data of the serial clock information;
304: sending the first interconnection information to a clock synchronization center node equipment frame through an inter-frame interconnection interface of the clock synchronization center node equipment frame;
the high-speed interconnect interface is an existing interface for transmitting high-speed service data, and the embodiment uses the interface to transmit the first interconnect information.
If there are multiple clock synchronization peripheral node device frames in the multi-frame cluster system, each sends the clock synchronization reference information inside the device frame to the clock synchronization center node device frame in the manner of step 301 and step 304.
305: the clock synchronization center node equipment frame receives first interconnection information sent by a clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the clock synchronization center node equipment frame;
306: acquiring serial clock information according to the first interconnection information;
307: dividing the serial clock information to obtain clock synchronization reference information inside the clock synchronization peripheral node equipment frame;
through step 305 and step 307, the clock synchronization center node device frame obtains the clock synchronization reference information of all clock synchronization peripheral node device frames in the multi-frame cluster system.
308: a clock synchronization center node equipment frame acquires clock synchronization reference information inside the equipment frame;
309: according to clock synchronization reference information inside the equipment frame and clock synchronization reference information inside the clock synchronization peripheral node equipment frame, unified clock synchronization reference information is determined;
specifically, according to a preset strategy, one of the clock synchronization reference information in the device frame and the peripheral node device frame is selected as the unified clock synchronization reference information of the cluster system.
Through step 305 and step 309, the clock synchronization center node equipment box determines the unified clock synchronization reference information of the cluster system. Then, the clock synchronization center node device block needs to distribute the unified clock synchronization reference information to the whole cluster system, not only to the devices in the device block (if the Multi-Star Multi-frame cluster system is adopted, the clock synchronization center node device block does not need this step), but also to other clock synchronization peripheral node device blocks, and the specific process is as follows:
310: carrying the unified clock synchronization reference information in the serial clock information;
311: forming second interconnection information by the serial clock information and second service data of the serial clock information and the serial clock information;
312: sending the second interconnection information to all clock synchronization center node equipment frames in the cluster system through self inter-frame interconnection interfaces;
313: the clock synchronization peripheral node equipment frame receives second interconnection information sent by the clock synchronization central node equipment frame through an inter-frame interconnection interface of the equipment frame;
314: acquiring serial clock information according to the second interconnection information;
315: dividing the serial clock information to obtain unified clock synchronization reference information
And after the clock synchronization peripheral node equipment frame obtains the unified clock synchronization reference information, the unified clock synchronization reference information is distributed to the equipment in the equipment frame.
Through step 301 and step 315, all device boxes and their internal devices in the Full Mesh cluster system are synchronized to a clock reference source, i.e., unified clock synchronization reference information.
The specific flow of clock synchronization of the Multi-Star Multi-frame cluster system is substantially the same as that of the Full Mesh cluster system. The difference is that the Multi-Star Multi-frame cluster system generally selects a central equipment frame because of the clock synchronization central node equipment frame, and the central equipment frame has no service interface. Therefore, in the Multi-Star Multi-frame cluster system, the clock synchronization center node device frame does not need to execute step 308, and accordingly, the content of step 309 becomes: and determining unified clock synchronization reference information according to the clock synchronization reference information in the clock synchronization peripheral node equipment frame. In addition, when the unified clock synchronization reference information is distributed, the unified clock synchronization reference information is only distributed to other clock synchronization peripheral node device frames. Other steps are the same as the clock synchronization process of the Full Mesh multi-frame cluster system, and are not described herein again.
Further, steps 302, 303 and steps 310, 311 may be implemented using SERDES technology. See the SERDES structure diagram shown in fig. 6.
In the sending direction, parallel data and a parallel clock (collectively called service data, in this embodiment, including first service data and second service data) with the frequency of fparallel and the bit width of n are converted into parallel balanced data with the bit width of m and the frequency of fparallel through a balanced coding module (in this embodiment, n: m balanced coding, commonly used 8b:10b balanced coding, 64b:66b balanced coding and the like); converting the data into high-speed serial service data with frequency fseral (fseral) by a parallel-serial conversion module; the sending side is also provided with a clock frequency multiplication and phase locking module which superimposes clock synchronization reference information and a local reference clock fRxref on the serial clock information, forms the serial clock information and the serial service data into interconnection information (including first interconnection information and second interconnection information in the embodiment) and sends the interconnection information out.
In the receiving direction, the interconnect information with frequency fseral first goes through a Clock Data Recovery (CDR) module, which recovers serial Clock information and serial traffic Data from the received interconnect information based on a locally provided reference Clock fRxref. The recovered serial service data is converted into parallel balanced data with bit width of m and frequency of fparallel (fparallel/m) through a serial-to-parallel conversion module, and then the parallel balanced data is converted into service data with bit width of n and frequency of fparallel through a balanced decoding module (m: n balanced decoding in the figure); and the high-speed serial clock information recovered by the receiving side is subjected to frequency division processing to output clock synchronization reference information.
The information interaction process between the device frames when the clocks in the cluster system are synchronized is introduced above. When clock synchronization is implemented, the functional logic structure inside the device frame is shown in fig. 7, and includes a plurality of service interface modules (N are provided), two central processing modules (one of which is used for backup), and an inter-frame interconnection module (M are provided). The logical structure is applicable to all device boxes in the Full Mesh Multi-box architecture and clock synchronous peripheral node device boxes in the Multi-Star Multi-box cluster.
When the device frame is used as a clock synchronization peripheral node, the clock synchronization is processed as follows:
at the service interface module, the input line clock synchronization signal from the service interface is extracted by the interface chip (as shown in step a1), and then is sent to the clock processing center of the central processing module as an alternative clock synchronization reference source after two-stage selection processing of line reference clock selection (as shown in step B1) located inside the service interface module and line reference clock selection (as shown in step C1) located on the central processing module. The clock processing center (as shown in step D1) only needs to make further selection of the clock synchronization reference source inside the device frame according to the line clock synchronization signal input inside the device frame, and distributes the selected clock synchronization reference signal to the inter-frame interconnection interface chips on the inter-frame interconnection module step by step through the interconnection reference clock distribution (as shown in step E1) located on the central processing module and the interconnection reference clock distribution (as shown in step F1) located on the inter-frame interconnection module step by step, so that the inter-frame interconnection interface chips send the clock synchronization reference signal inside the device frame through the inter-frame interconnection interface (as shown in step G1), thereby sending the clock synchronization reference signal selected by the device frame to the adjacent device frame through the inter-frame interconnection interface. Since the destination of the transmission of the clock synchronization reference signal of the device block as the clock synchronization peripheral node is clear and the device block as the clock synchronization center node, the steps E1, F1, and G1 are not broadcast but have purposeful distribution. When the clock synchronization peripheral node device frame receives the unified clock synchronization reference signal sent by the clock synchronization central node device frame, the data flow is exactly opposite to the sending flow, and only the following is briefly described here: the inter-frame interconnection interface chip receives the unified clock synchronization reference signal through the inter-frame interconnection interface (as shown in step a2), receives the interconnection reference clock through the inter-frame interconnection module (as shown in step B2) and the interconnection reference clock through the central processing module (as shown in step C2), transmits the unified clock synchronization reference signal to the clock processing center step by step (as shown in step D2), receives the line reference clock through the central processing module (as shown in step E2) and the line reference clock through the service interface module (as shown in step F2), distributes the signals to the interface chip of the service module step by step (as shown in step a2), and finally distributes the unified clock synchronization reference signal to the devices in the device frame through the service interface. The inter-frame interconnection interface chip and the interface chip may be implemented by using the SERDES technology.
When the device frame is used as a clock synchronization center node, the clock synchronization process is basically the same as that of the clock synchronization peripheral node. The difference is that the clock processing center (corresponding to step D1) needs to determine the unified clock synchronization reference signal in the cluster according to the clock synchronization reference signal inside the device frame and the received clock synchronization reference signal of the clock synchronization peripheral device frame. In addition, when distributing the unified clock synchronization reference signal, the unified clock synchronization reference signal is distributed to not only the interface chip of the service interface module of the device frame but also other clock synchronization peripheral node device frames.
In specific implementation, the device frame can be selected to work in a clock synchronization center node or a clock synchronization peripheral node through software or logic configuration.
Referring to fig. 8, the functional logic structure inside the clock synchronous center node device block of the Multi-Star Multi-block cluster includes: two central processing modules (one of which is used for backup) and an inter-frame interconnection module (M is provided). The clock synchronization center node equipment frame of the Full Mesh multi-frame cluster system mainly differs from the clock synchronization center node equipment frame of the Full Mesh multi-frame cluster system in that: the clock synchronization center node equipment block in the Multi-Star Multi-block cluster system is a center equipment block, and the center equipment block has no service interface. Therefore, in the processing flow of clock synchronization, the clock synchronization center node device block of the Multi-Star Multi-frame cluster system does not need to execute step 308, and accordingly, the content of step 309 becomes: and determining unified clock synchronization reference information according to the clock synchronization reference information in the clock synchronization peripheral node equipment frame. In addition, when the unified clock synchronization reference information is distributed, the unified clock synchronization reference information is only distributed to other clock synchronization peripheral node equipment frames. The other steps are the same as the clock synchronization process of the Full Mesh multi-frame cluster system.
The method provided by the embodiment achieves the purpose of clock synchronization among multiple equipment frames by using the existing inter-frame interconnection channel and carrying clock synchronization reference information when transmitting service data, does not need to additionally arrange a special line, overcomes the defect that the clock synchronization is limited by hardware, can be realized through software configuration, and is more flexible to implement. In addition, the existing interconnection channel between frames is usually realized by adopting optical fibers, and compared with the prior art, the reliability is higher.
Example 4
Referring to fig. 9, the present embodiment provides an apparatus box, including:
a receiving unit 401, configured to receive, through an inter-frame interconnection interface of the device frame, first interconnection information sent by a clock synchronization peripheral node device frame, where the first interconnection information includes: the first service data and clock synchronization reference information inside the clock synchronization peripheral node equipment frame;
a determining unit 402, configured to determine unified clock synchronization reference information according to the first interconnection information received by the receiving unit 401;
a sending unit 403, configured to send the unified clock synchronization reference information determined by the determining unit 402 to the clock synchronization peripheral node device frame through an inter-frame interconnection interface of the device frame.
Further, referring to fig. 10, the determining unit 402 includes:
an obtaining subunit 402a, configured to obtain clock synchronization reference information inside the clock synchronization peripheral node device frame in the first interconnection information;
a determining subunit 402b, configured to determine unified clock synchronization reference information according to the clock synchronization reference information inside the clock synchronization peripheral node device frame acquired by the acquiring subunit 402 a.
Further, in the above-mentioned case,
the obtaining subunit 402a is further configured to obtain clock synchronization reference information inside the device frame;
the determining subunit 402b is further configured to determine unified clock synchronization reference information according to the clock synchronization reference information inside the clock synchronization peripheral node device frame acquired by the acquiring subunit 402a and the clock synchronization reference information inside the device frame.
Further, the obtaining subunit 402a is specifically configured to obtain serial clock information according to the first interconnection information, divide the frequency of the serial clock information, and obtain clock synchronization reference information inside the clock synchronization peripheral node device frame.
Further, referring to fig. 11, the sending unit 403 includes:
a serial clock forming subunit 403a, configured to carry the unified clock synchronization reference information in serial clock information;
an interconnection information forming subunit 403b, configured to form, by the serial clock information generated by the serial clock forming subunit 403a and second service data pre-sent by the device frame, second interconnection information;
a sending subunit 403c, configured to send, through the inter-frame interconnection interface of the device frame, the second interconnection information generated by the interconnection information forming subunit 403b to the clock synchronization peripheral node device frame.
The device frame provided in this embodiment and the clock synchronization center node device frame in the method embodiment belong to the same concept, where a receiving unit 401 and a sending unit 403 included in the device frame and an inter-frame interconnection module in the method embodiment belong to the same concept, and a determining unit 402 included in the device frame and a center processing module in the method embodiment belong to the same concept, and a specific implementation process thereof is detailed in the method embodiment and is not described herein again.
The device frame provided by the embodiment realizes the purpose of clock synchronization among multiple device frames by using the existing inter-frame interconnection channel and carrying clock synchronization reference information when transmitting service data, does not need to additionally arrange a special line, gets rid of the defect that the clock synchronization is limited by hardware, and is more flexible to realize.
Example 5
Referring to fig. 12, the present embodiment provides an apparatus box including:
a sending unit 501, configured to send first interconnection information to a clock synchronization center node device frame through an inter-frame interconnection interface of the device frame, where the first interconnection information includes: the first service data and clock synchronization reference information inside the equipment frame;
a receiving unit 502, configured to receive, through an inter-frame interconnection interface of the device frame, second interconnection information sent by the clock synchronization center node device frame, where the second interconnection information includes second service data and unified clock synchronization reference information, where the unified clock synchronization reference information is determined by the clock synchronization center node device frame according to the first interconnection information;
an obtaining unit 503, configured to obtain the rtc reference information in the second interconnect information received by the receiving unit 502.
Further, the obtaining unit 503 is specifically configured to obtain serial clock information according to the second interconnection information, and frequency-divide the serial clock information to obtain unified clock synchronization reference information.
Further, referring to fig. 13, the device frame further includes:
a serial clock forming unit 504, configured to carry clock synchronization reference information inside the device frame in serial clock information;
an interconnection information forming unit 505, configured to form the serial clock information generated by the serial clock forming unit 504 and the first service data into the first interconnection information.
The device frame provided in this embodiment and the clock synchronization peripheral node device frame in the method embodiment belong to the same concept, wherein the device frame includes a sending unit 501, a receiving unit 502, and an obtaining unit 503, as well as a serial clock forming unit 504 and an interconnection information forming unit 505, which belong to the same concept as the inter-frame interconnection module in the method embodiment, and a specific implementation process thereof is detailed in the method embodiment and is not described herein again.
The device frame provided by the embodiment realizes the purpose of clock synchronization among multiple device frames by using the existing inter-frame interconnection channel and carrying clock synchronization reference information when transmitting service data, does not need to additionally arrange a special line, gets rid of the defect that the clock synchronization is limited by hardware, and is more flexible to realize.
Example 6
Referring to fig. 14, the present embodiment provides a system for clock synchronization, including: a clock synchronization peripheral node device frame 601 and a clock synchronization center node device frame 602;
the clock synchronization peripheral node device frame 601 is configured to send first interconnection information to the clock synchronization central node device frame 602 through an inter-frame interconnection interface of the device frame, where the first interconnection information includes: the first service data and clock synchronization reference information inside the equipment frame;
the clock synchronization center node device frame 602 is configured to receive the first interconnection information sent by the clock synchronization peripheral node device frame 601 through the inter-frame interconnection interface of the device frame, determine unified clock synchronization reference information according to the first interconnection information, and send the unified clock synchronization reference information to the clock synchronization peripheral node device frame 601 through the inter-frame interconnection interface of the device frame.
Further, in the above-mentioned case,
the clock synchronization center node device frame 602 is further configured to send second interconnection information to the clock synchronization peripheral node device frame 601 through an inter-frame interconnection interface of the device frame, where the second interconnection information includes second service data and unified clock synchronization reference information;
the clock synchronization peripheral node device frame 601 is further configured to receive the second interconnection information through an inter-frame interconnection interface of the device frame, and acquire unified clock synchronization reference information in the second interconnection information.
Further, in the above-mentioned case,
the clock synchronization peripheral node device frame 601 is further configured to carry clock synchronization reference information inside the device frame in serial clock information, and compose the serial clock information and the first service data into the first interconnection information.
Further, in the above-mentioned case,
the clock synchronization center node device frame 602 is further configured to carry the unified clock synchronization reference information in serial clock information, and combine the serial clock information and second service data pre-sent by the device frame into second interconnection information.
The clock synchronization center/peripheral node device frame related to the system provided in this embodiment belongs to the same concept as the clock synchronization center/peripheral node device frame in the method embodiment, and the specific implementation process thereof is detailed in the method embodiment and is not described herein again.
The system provided by the embodiment realizes the purpose of clock synchronization among multiple equipment frames by using the existing inter-frame interconnection channel and carrying clock synchronization reference information when transmitting service data, does not need to additionally arrange a special line, overcomes the defect that the clock synchronization is limited by hardware, and is more flexible to realize.
All or part of the technical solutions provided by the above embodiments may be implemented by software programming, and the software program is stored in a readable storage medium, for example: hard disk, optical disk or floppy disk in a computer.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (20)
1. A method of clock synchronization, the method comprising:
receiving first interconnection information sent by a clock synchronization peripheral node device frame through an inter-frame interconnection interface of the device frame, wherein the first interconnection information comprises: the first service data and clock synchronization reference information inside the clock synchronization peripheral node equipment frame;
according to the clock synchronization reference information in the clock synchronization peripheral node equipment frame, unified clock synchronization reference information is determined; sending second interconnection information to the clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the equipment frame, wherein the second interconnection information comprises second service data and the unified clock synchronization reference information;
or,
according to the clock synchronization reference information in the clock synchronization peripheral node equipment frame and the clock synchronization reference information in the equipment frame, unified clock synchronization reference information is determined, the unified clock synchronization reference information is sent to equipment in the equipment frame, second interconnection information is sent to the clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the equipment frame, and the second interconnection information comprises second service data and the unified clock synchronization reference information.
2. The method of claim 1, wherein prior to determining unified clock synchronization reference information from clock synchronization reference information within the clock synchronization peripheral node device box, further comprising:
and acquiring clock synchronization reference information inside the clock synchronization peripheral node equipment frame in the first interconnection information.
3. The method as claimed in claim 1, wherein before determining unified clock synchronization reference information according to the clock synchronization reference information inside the clock synchronization peripheral node device frame and the clock synchronization reference information inside the local device frame, further comprising:
clock synchronization reference information inside the clock synchronization peripheral node equipment frame in the first interconnection information is obtained;
and acquiring clock synchronization reference information inside the equipment frame.
4. The method of claim 2 or 3, wherein said obtaining clock synchronization reference information inside the clock synchronized peripheral node device box in the first interconnect information comprises:
acquiring serial clock information according to the first interconnection information;
and dividing the frequency of the serial clock information to obtain clock synchronization reference information inside the clock synchronization peripheral node equipment frame.
5. The method as claimed in claim 1, wherein before sending the second interconnect information to the clock-synchronized peripheral node device frame through the inter-frame interconnect interface of the device frame, the method further comprises:
carrying the unified clock synchronization reference information in serial clock information;
and forming second interconnection information by the serial clock information and second service data pre-sent by the equipment frame.
6. A method of clock synchronization, the method comprising:
through the inter-frame interconnection interface of the equipment frame, first interconnection information is sent to the clock synchronization center node equipment frame, and the first interconnection information comprises: the first service data and clock synchronization reference information inside the equipment frame;
receiving, by an inter-frame interconnection interface of the local equipment frame, second interconnection information sent by the clock synchronization center node equipment frame, where the second interconnection information includes second service data and unified clock synchronization reference information, where the unified clock synchronization reference information is determined by the clock synchronization center node equipment frame according to clock synchronization reference information inside the local equipment frame and clock synchronization reference information inside the clock synchronization center node equipment frame in the first interconnection information, or determined by the clock synchronization center node equipment frame according to clock synchronization reference information inside the local equipment frame in the first interconnection information;
and acquiring unified clock synchronization reference information in the second interconnection information.
7. The method as claimed in claim 6, wherein before sending the first interconnection information to the clock synchronization center node device frame through the inter-frame interconnection interface of the device frame, the method further comprises:
carrying the clock synchronization reference information inside the equipment frame in serial clock information;
and forming the first interconnection information by the serial clock information and the first service data.
8. The method of claim 6, wherein the obtaining unified clock synchronization reference information in the second interconnect information comprises:
acquiring serial clock information according to the second interconnection information;
and dividing the frequency of the serial clock information to obtain the synchronous reference information of the unified clock.
9. An equipment box, comprising:
a receiving unit, configured to receive, through an inter-frame interconnection interface of the device frame, first interconnection information sent by a clock synchronization peripheral node device frame, where the first interconnection information includes: the first service data and clock synchronization reference information inside the clock synchronization peripheral node equipment frame;
a determining unit, configured to determine unified clock synchronization reference information according to the clock synchronization reference information in the device frame and the clock synchronization reference information in the clock synchronization peripheral node device frame in the first interconnection information received by the receiving unit, or determine unified clock synchronization reference information according to the clock synchronization reference information in the clock synchronization peripheral node device frame in the first interconnection information received by the receiving unit;
and the sending unit is used for sending second interconnection information to the clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the equipment frame, wherein the second interconnection information comprises second service data and the unified clock synchronization reference information determined by the determining unit.
10. The apparatus box of claim 9, wherein the determining unit comprises:
an obtaining subunit, configured to obtain clock synchronization reference information inside the clock synchronization peripheral node device frame in the first interconnection information;
and the determining subunit is used for determining the unified clock synchronization reference information according to the clock synchronization reference information in the clock synchronization peripheral node equipment frame acquired by the acquiring subunit.
11. The apparatus box of claim 10,
the acquiring subunit is further configured to acquire clock synchronization reference information inside the device frame;
the determining subunit is further configured to determine unified clock synchronization reference information according to the clock synchronization reference information inside the clock synchronization peripheral node device frame acquired by the acquiring subunit and the clock synchronization reference information inside the device frame;
correspondingly, the sending unit is further configured to send the second interconnection information to the device in the device frame.
12. The device frame according to claim 10 or 11, wherein the obtaining subunit is specifically configured to obtain serial clock information according to the first interconnection information, and divide the serial clock information to obtain clock synchronization reference information inside the clock synchronization peripheral node device frame.
13. The apparatus box of claim 9, wherein the transmitting unit comprises:
the serial clock forming subunit is used for carrying the unified clock synchronization reference information in serial clock information;
the interconnection information forming subunit is used for forming the serial clock information generated by the serial clock forming subunit and second service data pre-sent by the equipment frame into second interconnection information;
and the sending subunit is configured to send, to the clock synchronization peripheral node device frame, second interconnection information generated by the interconnection information forming subunit through an inter-frame interconnection interface of the device frame.
14. An equipment box, comprising:
a sending unit, configured to send first interconnection information to a clock synchronization center node device frame through an inter-frame interconnection interface of the device frame, where the first interconnection information includes: the first service data and clock synchronization reference information inside the equipment frame;
a receiving unit, configured to receive, through an inter-frame interconnection interface of the device frame, second interconnection information sent by the clock synchronization center node device frame, where the second interconnection information includes second service data and unified clock synchronization reference information, where the unified clock synchronization reference information is determined by the clock synchronization center node device frame according to clock synchronization reference information inside the device frame and clock synchronization reference information inside the clock synchronization center node device frame in the first interconnection information, or determined by the clock synchronization center node device frame according to clock synchronization reference information inside the device frame in the first interconnection information;
and the acquisition unit is used for acquiring the unified clock synchronization reference information in the second interconnection information received by the receiving unit.
15. The equipment frame of claim 14, wherein the obtaining unit is specifically configured to obtain serial clock information according to the second interconnection information, and divide the serial clock information to obtain unified clock synchronization reference information.
16. The device frame of claim 14, wherein the device frame further comprises:
a serial clock forming unit, configured to carry clock synchronization reference information inside the device frame in serial clock information;
and the interconnection information forming unit is used for forming the serial clock information generated by the serial clock forming unit and the first service data into the first interconnection information.
17. A system for clock synchronization, the system comprising: clock synchronization peripheral node equipment frames and clock synchronization central node equipment frames;
the clock synchronization peripheral node device frame is configured to send first interconnection information to the clock synchronization center node device frame through an inter-frame interconnection interface of the clock synchronization peripheral node device frame, where the first interconnection information includes: the first service data and clock synchronization reference information inside the clock synchronization peripheral node equipment frame;
the clock synchronization center node equipment frame is used for receiving the first interconnection information sent by the clock synchronization peripheral node equipment frame through an inter-frame interconnection interface of the clock synchronization center node equipment frame, determining unified clock synchronization reference information according to the first interconnection information, and sending second interconnection information to the clock synchronization peripheral node equipment frame through the inter-frame interconnection interface of the clock synchronization center node equipment frame, wherein the second interconnection information comprises second service data and the unified clock synchronization reference information;
when the clock synchronization central node equipment frame determines unified clock synchronization reference information according to the first interconnection information, the clock synchronization central node equipment frame is used for determining the unified clock synchronization reference information according to the clock synchronization reference information in the clock synchronization peripheral node equipment frame; or, the method is used for determining unified clock synchronization reference information according to the clock synchronization reference information inside the clock synchronization peripheral node equipment frame and the clock synchronization reference information inside the clock synchronization central node equipment frame.
18. The system of claim 17,
and the clock synchronization peripheral node equipment frame is further used for receiving the second interconnection information through an inter-frame interconnection interface of the clock synchronization peripheral node equipment frame and acquiring unified clock synchronization reference information in the second interconnection information.
19. The system according to claim 17 or 18, wherein the clock synchronization peripheral node device frame is further configured to carry clock synchronization reference information inside the clock synchronization peripheral node device frame in serial clock information, and compose the serial clock information and the first service data into the first interconnection information.
20. The system according to claim 17 or 18, wherein the clock synchronization center node device frame is further configured to carry the unified clock synchronization reference information in serial clock information, and compose the serial clock information and second service data pre-sent by the clock synchronization center node device frame into second interconnection information.
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| CN 200910145717 CN101562490B (en) | 2009-05-31 | 2009-05-31 | Method for clock synchronization as well as equipment frame and system thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105897366A (en) * | 2016-04-01 | 2016-08-24 | 浪潮电子信息产业股份有限公司 | Method and system for ensuring time consistency of computer cluster nodes |
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| WO2013097092A1 (en) * | 2011-12-27 | 2013-07-04 | 中兴通讯股份有限公司 | Global synchronization method and system based on packet switching system |
| CN107579779B (en) * | 2017-09-13 | 2019-11-26 | 中国电子科技集团公司第四十一研究所 | A kind of coding circuit design method for optical fiber transmission |
| CN107483138B (en) * | 2017-09-22 | 2019-04-16 | 烽火通信科技股份有限公司 | Cluster Clock management system and management method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101267251A (en) * | 2008-04-30 | 2008-09-17 | 中兴通讯股份有限公司 | Distributed base station clock synchronization method and system |
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| CN101267251A (en) * | 2008-04-30 | 2008-09-17 | 中兴通讯股份有限公司 | Distributed base station clock synchronization method and system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897366A (en) * | 2016-04-01 | 2016-08-24 | 浪潮电子信息产业股份有限公司 | Method and system for ensuring time consistency of computer cluster nodes |
| CN105897366B (en) * | 2016-04-01 | 2018-09-04 | 浪潮电子信息产业股份有限公司 | Method and system for ensuring time consistency of computer cluster nodes |
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