CN2901696Y - Inductive load driving circuit - Google Patents
Inductive load driving circuit Download PDFInfo
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- CN2901696Y CN2901696Y CNU2006200066283U CN200620006628U CN2901696Y CN 2901696 Y CN2901696 Y CN 2901696Y CN U2006200066283 U CNU2006200066283 U CN U2006200066283U CN 200620006628 U CN200620006628 U CN 200620006628U CN 2901696 Y CN2901696 Y CN 2901696Y
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Abstract
The utility model discloses an inductive load drive circuit, which comprises an input loop, a control loop and an output loop, wherein the control loop comprises a first control loop which provides a first output driving voltage minimum value and a first output driving voltage maximum value when the input voltage signal is negative and forms dynamic range of the first output driving voltage; when the input voltage signal is positive, the first control loop does not work, but the second control loop provides a second output driving voltage minimum value and a second output driving voltage maximum value, which forms dynamic range of the second output driving voltage. When the input voltage signal is negative, the second control loop does not work. Technical strategy employed with the utility model, effectively extends dynamic output range and improves working stability of negative feedback amplifying circuit by employing two control loops who alternate work automatically according to the polarity of the input and output signal.
Description
Technical field
The utility model relates to the drive circuit field, more particularly, relates to Perceptual Load Drive Circuit.
Background technology
When driving inductive load, adopt BTL circuit structure as shown in Figure 1 to drive inductive load usually.Be input to the positive-negative input end of the BTL amplifier that constitutes by two power amplifier A2 and A3 behind the input signal process first order amplification A1, and obtain opposite polarity output voltage V o (+) and Vo (-) at output.The driving voltage phase place is 90 ° because the drive current phase place that produces on the inductive load can lag behind, simultaneously, the voltage output range of common power amplifier is limited, can cause the inductive load electric current not release and causes driving voltage out of control, thereby make The whole control loop instability.Therefore, must design a kind of novel Perceptual Load Drive Circuit and come controlling and driving electric current and voltage, guarantee the precision of the stable and control of loop.
Media players such as modern electronic product such as CD, CD-ROM, DVD-ROM adopt micro-machine (inductive load) to realize the focusing of laser light in a large number, tracking, the feeding of laser head, functions such as disc drives and turnover storehouse.How to realize the driving of inductive load and accurately control are directly connected to the broadcast performance and the reliability of these products.
From the principle, the control of inductive load is by data-signal is gathered and computing, and produces error controling signal and be input to Perceptual Load Drive Circuit, amplifies the back and realizes control to inductive load.Typical Perceptual Load Drive Circuit such as Fig. 1, input signal Vin is based on focusing, the control signal of tracking, amplify by negative feedback amplifier, on inductive load, produce exciting current IA or IB, and lag behind respectively 90 ° of corresponding driving voltage Vo of the phase place that obtains driving voltage Vo. exciting current IA or IB.
The output-stage circuit of base amplifier as shown in Figure 2.It is broadly divided into input circuit, comprises transistor Q11 and constant-current source I11; Control loop comprises constant-current source I12, diode D11, D12, and transistor Q12, Q13; Output loop comprises transistor Q14 and Q15.Its outputting drive voltage Vo is subjected to the control of Vin, flows through lag behind respectively 90 ° in corresponding driving voltage Vo phase place of the electric current I A of inductive load and IB phase place.As shown in Figure 2, positive incentive electric current I A flows into inductive load, and negative incentive electric current I B flows out inductive load.And the transistor Q14 of output loop and Q15 form push-pull configuration, and when exciting current IA inflow inductive load, transistor Q14 opens, and transistor Q15 closes.Otherwise exciting current IB flows out inductive load, and transistor Q15 opens, and transistor Q14 closes.When exciting current IA flows out, a little higher than outputting drive voltage Vo of the collector potential of transistor Q11.Otherwise, when exciting current IB flows into, the B-E knot pressure drop sum of connecting between the forward conduction voltage drop sum of two diode D1, D2 and transistor Q12, Q13 equates, the collector potential of transistor Q11 equals outputting drive voltage Vo, simultaneously, transistor Q15 quilt is by diode D1, D2, and the loop that constant-current source I2 and transistor Q12, Q13 form is opened.That is to say, when the collector potential of transistor Q11 during greater than outputting drive voltage Vo transistor Q12, Q13 close, and transistor Q12, Q13 open when the collector voltage of transistor Q11 equals outputting drive voltage Vo, at this moment, transistor Q15 is in opening, and exciting current IB flows out from inductive load L.
In this design, owing between power Vcc and output out, have current source I2 and diode D1, D2, therefore by diode D1, D2, the maximum output voltage Vo that the loop driving transistors Q15 that constant-current source I2 and transistor Q12, Q13 form obtains is " Vcc-V
SAT (I2)-2V
F" (V
SAT (12): the saturation voltage drop of current source I2).When exciting current IB flowed into, transistor Q14 closed in addition, and the dynamic range maximum of outputting drive voltage Vo is greater than " Vcc ".Therefore, this may make transistor Q15 wayward, thereby the instability that becomes is used in negative feedback.That is, corresponding driving voltage Vo phase place is 90 ° because the current phase that flows through inductive load L lags behind, essential turn-on transistor Q15, so that underexcitation electric current I B can flow in the time shown in Fig. 3 A, the 3B dash area, therefore, if outputting drive voltage Vo is too big, it is unstable that the negative feedback application can become.
So, just need a kind of novel Perceptual Load Drive Circuit that can overcome above-mentioned defective.
The utility model content
The purpose of this utility model provides a kind of Perceptual Load Drive Circuit job stability and that effectively enlarge dynamic output area that can improve negative feedback amplifier.
According to the utility model, a kind of Perceptual Load Drive Circuit is provided, comprise input circuit, control loop and output loop, the control loop of described Perceptual Load Drive Circuit comprises: first control loop, voltage signal in input is worked during for negative polarity, the first outputting drive voltage minimum value and the first outputting drive voltage maximum are provided, form the first outputting drive voltage dynamic range; When the voltage signal of input was positive polarity, first control loop was not worked; Second control loop is worked during for positive polarity at the voltage signal of input, provides second output to drive the minimum value and the second outputting drive voltage maximum, forms the second outputting drive voltage dynamic range; When the voltage signal of input was negative polarity, second control loop was not worked.
Preferable, described first control loop comprises, the 3rd diode and the series connection of the 4th diode, the positive pole of the 3rd diode links to each other with the 7th transistorized base stage, also connect power supply by the 4th constant-current source, the 7th transistorized collector electrode connects power supply, and the 7th transistorized emitter links to each other with the 8th transistorized emitter; The 8th transistorized collector electrode is connected to second control loop, and the negative pole of the 4th diode is connected to output loop; Described second control loop comprises, first diode and the series connection of second diode, the negative pole of second diode links to each other with the tenth transistorized base stage, also by the 3rd constant-current source ground connection, the tenth transistorized collector electrode links to each other with the 8th transistorized collector electrode in first control loop, be also connected to output loop, the tenth transistorized emitter links to each other with the 9th transistorized emitter; The 9th transistorized base stage connects output, and collector electrode connects power supply.
Preferable, described input circuit comprises, the base stage of the first transistor positive input terminal that links to each other, and the base stage of the transistor seconds negative input end that links to each other, the first transistor and transistor seconds are formed a differential pair, the emitter first constant-current source ground connection that was connected mutually; The 3rd transistorized emitter links to each other with power supply, the 4th transistorized emitter links to each other with power supply, three, link to each other with the 4th transistorized collector electrode again after the 4th transistorized base stage is connected with each other, form a current mirror, simultaneously, the collector electrode of the first transistor links to each other with the 3rd transistorized collector electrode, and the collector electrode of transistor seconds links to each other with the 4th transistorized collector electrode.
Preferable, described output loop comprises, the push-pull configuration that the 11 transistor and the tenth two-transistor are formed, wherein the 11 transistorized collector electrode is connected to power supply, the grounded emitter of the tenth two-transistor, the 11 transistorized emitter are connected to the collector electrode of the tenth two-transistor and as the output of output loop.
Preferable, in described first control loop, the negative pole of the 4th diode is connected to the collector electrode of the tenth two-transistor in the output loop; In described second control loop, the tenth transistorized collector electrode is connected to the base stage of the tenth two-transistor in the output loop.
Preferable, described Perceptual Load Drive Circuit also comprises: the darlington structure that the 5th transistor and the 6th transistor are formed, wherein the collector electrode of the first transistor in the 5th transistorized base stage and the input circuit links to each other, the 5th transistorized grounded collector, the 5th transistorized emitter links to each other with the 6th transistorized base stage, the 6th transistorized emitter links to each other with power supply, the 6th transistor collector is by the second constant-current source ground connection, the 6th transistorized collector electrode again with output loop in the 11 transistorized base stage, the 8th transistorized base stage in first control loop and the positive pole of second diode in second control loop link to each other.
Preferable, when the voltage signal of input is negative polarity, the first control loop work, the minimum value of first outputting drive voltage is the saturation voltage drop of the tenth two-transistor, and the maximum of first outputting drive voltage is: supply voltage-Di four constant-current source saturation voltage drops-2 * diode forward conducting voltage (VF); When the voltage signal of input is positive polarity, the second control loop work, the minimum value of second outputting drive voltage is: the transistorized saturation voltage drop of B-E knot pressure drop+tenth+the 9th transistor B-E of the tenth two-transistor ties pressure drop; The maximum of second outputting drive voltage is: supply voltage-Di 11 transistorized B-E knot pressure drop-Di six transistorized saturation voltage drops.
Preferable, the tenth transistor in second control loop is the PNP pipe, the 9th transistor is the NPN pipe.
Adopted the technical solution of the utility model, by adopting the polarity of two control loops according to input/output signal, alternation has automatically effectively enlarged dynamic output area, has improved the job stability of negative feedback amplifier.
Description of drawings
The above and other feature of the present utility model, character and advantage will become more obvious by the description below in conjunction with drawings and Examples, identical in the accompanying drawings Reference numeral is represented identical feature all the time, wherein,
Fig. 1 is the circuit theory diagrams of Perceptual Load Drive Circuit in the prior art;
Fig. 2 is the circuit structure diagram of Perceptual Load Drive Circuit in the prior art;
Fig. 3 A and 3B are the work waves of Perceptual Load Drive Circuit shown in Figure 2;
Fig. 4 is the circuit structure diagram according to the Perceptual Load Drive Circuit of an embodiment of the present utility model;
Fig. 5 A-5D is the work wave of Perceptual Load Drive Circuit shown in Figure 4.
Embodiment
Further specify the technical solution of the utility model below in conjunction with drawings and Examples.
Basic design philosophy of the present utility model provides a kind of Perceptual Load Drive Circuit, comprises input circuit, control loop and output loop, and the control loop of described Perceptual Load Drive Circuit comprises,
First control loop is worked during for negative polarity at the voltage signal of input, and the first outputting drive voltage minimum value and the first outputting drive voltage maximum are provided, and forms the first outputting drive voltage dynamic range; When the voltage signal of input was positive polarity, first control loop was not worked;
Second control loop is worked during for positive polarity at the voltage signal of input, provides second output to drive the minimum value and the second outputting drive voltage maximum, forms the second outputting drive voltage dynamic range; When the voltage signal of input was negative polarity, second control loop was not worked.
In order to realize technique scheme of the present invention, for first control loop wherein, can adopt following structure: the 3rd diode and the series connection of the 4th diode, the positive pole of the 3rd diode links to each other with the 7th transistorized base stage, also connect power supply by the 4th constant-current source, the 7th transistorized collector electrode connects power supply, and the 7th transistorized emitter links to each other with the 8th transistorized emitter; The 8th transistorized collector electrode is connected to second control loop, and the negative pole of the 4th diode is connected to output loop.
For second control loop wherein, can adopt following structure: first diode and the series connection of second diode, the negative pole of second diode links to each other with the tenth transistorized base stage, also by the 3rd constant-current source ground connection, the tenth transistorized collector electrode links to each other with the 8th transistorized collector electrode in first control loop, be also connected to output loop, the tenth transistorized emitter links to each other with the 9th transistorized emitter; The 9th transistorized base stage connects output, and collector electrode connects power supply.
For input circuit wherein, can adopt following structure: the base stage of the first transistor positive input terminal that links to each other, the base stage of the transistor seconds negative input end that links to each other, the first transistor and transistor seconds are formed a differential pair, the emitter first constant-current source ground connection that was connected mutually; The 3rd transistorized emitter links to each other with power supply, the 4th transistorized emitter links to each other with power supply, three, link to each other with the 4th transistorized collector electrode again after the 4th transistorized base stage is connected with each other, form a current mirror, simultaneously, the collector electrode of the first transistor links to each other with the 3rd transistorized collector electrode, and the collector electrode of transistor seconds links to each other with the 4th transistorized collector electrode.
For output loop wherein, can adopt following structure: the push-pull configuration that the 11 transistor and the tenth two-transistor are formed, wherein the 11 transistorized collector electrode is connected to power supply, the grounded emitter of the tenth two-transistor, the 11 transistorized emitter are connected to the collector electrode of the tenth two-transistor and as the output of output loop.And in first control loop, the negative pole of the 4th diode is connected to the collector electrode of the tenth two-transistor in the output loop; In second control loop, the tenth transistorized collector electrode is connected to the base stage of the tenth two-transistor in the output loop.
Perceptual Load Drive Circuit of the present utility model, also can comprise: the darlington structure that the 5th transistor and the 6th transistor are formed, wherein the collector electrode of the first transistor in the 5th transistorized base stage and the input circuit links to each other, the 5th transistorized grounded collector, the 5th transistorized emitter links to each other with the 6th transistorized base stage, the 6th transistorized emitter links to each other with power supply, the 6th transistor collector is by the second constant-current source ground connection, the 6th transistorized collector electrode again with output loop in the 11 transistorized base stage, the 8th transistorized base stage in first control loop and the positive pole of second diode in second control loop link to each other.
Thus, can reach following purpose, when the voltage signal of input is negative polarity, the first control loop work, the minimum value of first outputting drive voltage is the saturation voltage drop of the tenth two-transistor, and the maximum of first outputting drive voltage is: supply voltage-Di four constant-current source saturation voltage drop-2VF (please illustrate that what voltage VF is); When the voltage signal of input is positive polarity, the second control loop work, the minimum value of second outputting drive voltage is: the transistorized saturation voltage drop of B-E knot pressure drop+tenth+the 9th transistor B-E of the tenth two-transistor ties pressure drop; The maximum of second outputting drive voltage is: supply voltage-Di 11 transistorized B-E knot pressure drop-Di six transistorized saturation voltage drops.
According to an embodiment, adopt the PNP pipe for the tenth transistor in second control loop, the 9th transistor adopts the NPN pipe.
With reference to figure 4, Fig. 4 is the circuit structure diagram according to the Perceptual Load Drive Circuit of an embodiment of the present utility model, and the work wave in conjunction with Fig. 5 A-5D is Perceptual Load Drive Circuit shown in Figure 4 is described as follows:
Shown in Figure 4, in the Perceptual Load Drive Circuit of this embodiment, input voltage signal anode Vin+ links to each other with the base stage of transistor Q1, and negative terminal Vin-links to each other with the base stage of transistor Q2.Transistor Q1, Q2 form a differential pair, the emitter constant-current source I1 ground connection that was connected.The collector electrode of transistor Q1 links to each other with the collector electrode of transistor Q3, and the emitter of transistor Q3 links to each other with power Vcc.Another side, the collector electrode of transistor Q2 links to each other with the collector electrode of transistor Q4, and the emitter of transistor Q4 links to each other with power Vcc.After being connected with each other, the base stage of transistor Q3, Q4 links to each other with the collector electrode of transistor Q4 again.That is, transistor Q3, Q4 form a current mirroring circuit.
The collector electrode of transistor Q1 links to each other with the base stage of transistor Q5, the grounded collector of transistor Q5.The emitter of transistor Q5 links to each other with the base stage of transistor Q6, and promptly transistor Q5, Q6 form darlington structure.The emitter of transistor Q6 links to each other with power Vcc, and collector electrode is by constant-current source I2 ground connection.The collector electrode of transistor Q6 links to each other with the base stage of transistor Q11, Q8 and the positive pole of diode D1 again.
Diode D3, D4 and transistor Q7, Q8 and constant-current source I4 form first control loop, driving transistors Q12.
Diode D1, D2 series connection, the negative pole of diode D2 links to each other with the base stage of transistor Q10, also by constant-current source I3 ground connection, and the base stage of the collector electrode of transistor Q10 and transistor Q12, the collector electrode of transistor Q8 links to each other, and its emitter links to each other with the emitter of transistor Q9.The base stage of transistor Q9 connects output, and collector electrode connects power supply.Diode D1, D2 and transistor Q9, Q10 and constant-current source I3 form second control loop, driving transistors Q12.
As Fig. 4, suppose to connect a predetermined DC reference voltage at negative terminal Vin-, the alternating voltage that connects a correspondence at anode Vin+, therefore, the base current of transistor Q5 changes with variation of AC voltage, produce a collector voltage that has with the alternating voltage same phase at the collector electrode of transistor Q6 thus, otherwise the collector electrode of transistor Q6 produces a collector voltage that has with the alternating voltage opposite phase.The emitter voltage of transistor Q11, i.e. driving voltage Vo changes with the variation of the collector voltage of transistor Q6.Because the phase place of driving voltage Vo is shown in Fig. 5 A or Fig. 5 B, so the end voltage of inductive load L changes shown in Fig. 5 C, and the exciting current that phase lag counterpart terminal voltage Vo phase place is 90 ° flows through inductive load L, the variation of this exciting current such as Fig. 5 D.Electric current I A represents that exciting current flows out to inductive load L from transistor Q11, and electric current I B represents that exciting current flow into transistor Q12 from inductive load L.
With reference to Fig. 5 A-5D, if exciting current IA flows through inductive load L when the end voltage of inductive load L is negative polarity, then the collector voltage of transistor Q6 can become higher slightly than driving voltage Vo, and therefore, transistor Q11 opens, and transistor Q12 closes.The emitter current of transistor Q11 flows out from output out as exciting current IA.In addition, because this moment, transistor Q12 closed, the dynamic range minimum value of driving voltage Vo may be lower than ground.
If exciting current IB flows through inductive load L when the end voltage of inductive load L is negative polarity, then the collector voltage of transistor Q6 can become equal with driving voltage Vo, therefore, transistor Q7, Q8 open, the emitter current of transistor Q7 flow into the base stage of transistor Q12, transistor Q12 opens then, so exciting current IB flows to ground by transistor Q12.In addition, since this moment driving voltage Vo the dynamic range minimum value become the saturation voltage drop of transistor Q12.Therefore, when driving voltage Vo was negative polarity, the dynamic range minimum value of driving voltage Vo was with the unlatching of transistor Q12 or close and change.
When the end voltage of inductive load L is negative polarity, by transistor Q10, Q9, the current channel of forming with constant-current source I3 is blocked, even therefore driving voltage Vo eases down to the saturation voltage drop of transistor Q12, first control loop also can make transistor Q12 open suitably.Or rather, when first control loop can work suitably, the minimum value of driving voltage Vo is the saturation voltage drop of transistor Q12, the minimum value of driving voltage Vo equals the minimum value of driving voltage Vo dynamic range when exciting current IB flows into, therefore, first control loop can work suitably.In addition, when first control loop can work suitably, the maximum of driving voltage Vo was " Vcc-V
SAT (I4)-2VF ", wherein Vcc is a supply voltage, V
SAT (I4)Be the saturation voltage drop voltage of constant-current source I4, VF is the diode forward conducting voltage.
On the other hand, when the end voltage of inductive load was positive polarity, second control loop was activated.When exciting current IA flow through inductive load L, it is higher slightly than driving voltage Vo that the collector electrode of transistor Q6 becomes, and at this moment, transistor Q11 opens.Because second control loop comprises two diode D1, D2, the B-E that its forward conduction voltage sum equals to connect between transistor Q10, Q9 ties the pressure drop sum, so when transistor Q11 opens, transistor Q10, Q9 close, transistor Q12 is keeping closed condition, at this moment, the dynamic range maximum of driving voltage Vo is " Vcc-V
BE (Q11)-V
SAT (Q6)" (V
BE (Q11): the B-E knot pressure drop of transistor Q11; V
SAT (Q6): the saturation voltage drop of transistor Q6).
On the contrary, when exciting current IB flow through inductive load L, the collector current of transistor Q6 became and equates with driving voltage Vo, and at this moment, transistor Q12, Q10, Q9 work.Just, exciting current IB flow into ground by transistor Q12.In addition, this moment, transistor Q11 became closed condition, and the dynamic range maximum of driving voltage Vo may be bigger than " Vcc ".
Because second control loop comprises transistor Q12, Q10, Q9, when second control loop can work suitably, the minimum value of driving voltage Vo is the B-E knot pressure drop of transistor Q12, the saturation voltage drop of transistor Q10, the B-E knot pressure drop sum of transistor Q9, and the dynamic range minimum value that this saturation voltage drop than transistor Q12 is driving voltage Vo is big.On the other hand, when second control loop can make transistor Q12 open suitably, the maximum of driving voltage Vo was greater than " Vcc ", and equates with the dynamic range maximum of driving voltage Vo when exciting current IB flows into.Because second control loop is activated when driving voltage Vo is positive polarity, so second control loop can be worked suitably.
Adopted the technical solution of the utility model, by adopting the polarity of two control loops according to input/output signal, alternation has automatically effectively enlarged dynamic output area, has improved the job stability of negative feedback amplifier.
The foregoing description provides to being familiar with the person in the art and realizes or use of the present utility model; those skilled in the art can be under the situation that does not break away from invention thought of the present utility model; the foregoing description is made various modifications or variation; thereby protection range of the present utility model do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.
Claims (8)
1. a Perceptual Load Drive Circuit comprises input circuit, control loop and output loop, it is characterized in that, the control loop of described Perceptual Load Drive Circuit comprises
First control loop is worked during for negative polarity at the voltage signal of input, and the first outputting drive voltage minimum value and the first outputting drive voltage maximum are provided, and forms the first outputting drive voltage dynamic range; When the voltage signal of input was positive polarity, first control loop was not worked;
Second control loop is worked during for positive polarity at the voltage signal of input, provides second output to drive the minimum value and the second outputting drive voltage maximum, forms the second outputting drive voltage dynamic range; When the voltage signal of input was negative polarity, second control loop was not worked.
2. Perceptual Load Drive Circuit as claimed in claim 1 is characterized in that,
Described first control loop comprises, the 3rd diode and the series connection of the 4th diode, the positive pole of the 3rd diode links to each other with the 7th transistorized base stage, also connect power supply by the 4th constant-current source, the 7th transistorized collector electrode connects power supply, and the 7th transistorized emitter links to each other with the 8th transistorized emitter; The 8th transistorized collector electrode is connected to second control loop, and the negative pole of the 4th diode is connected to output loop;
Described second control loop comprises, first diode and the series connection of second diode, the negative pole of second diode links to each other with the tenth transistorized base stage, also by the 3rd constant-current source ground connection, the tenth transistorized collector electrode links to each other with the 8th transistorized collector electrode in first control loop, be also connected to output loop, the tenth transistorized emitter links to each other with the 9th transistorized emitter; The 9th transistorized base stage connects output, and collector electrode connects power supply.
3. Perceptual Load Drive Circuit as claimed in claim 2 is characterized in that, described input circuit comprises,
The base stage of the first transistor positive input terminal that links to each other, the base stage of the transistor seconds negative input end that links to each other, the first transistor and transistor seconds are formed a differential pair, the emitter first constant-current source ground connection that was connected mutually;
The 3rd transistorized emitter links to each other with power supply, the 4th transistorized emitter links to each other with power supply, three, link to each other with the 4th transistorized collector electrode again after the 4th transistorized base stage is connected with each other, form a current mirror, simultaneously, the collector electrode of the first transistor links to each other with the 3rd transistorized collector electrode, and the collector electrode of transistor seconds links to each other with the 4th transistorized collector electrode.
4. Perceptual Load Drive Circuit as claimed in claim 3 is characterized in that, described output loop comprises,
The push-pull configuration that the 11 transistor and the tenth two-transistor are formed, wherein the 11 transistorized collector electrode is connected to power supply, the grounded emitter of the tenth two-transistor, the 11 transistorized emitter are connected to the collector electrode of the tenth two-transistor and as the output of output loop.
5. Perceptual Load Drive Circuit as claimed in claim 4 is characterized in that,
In described first control loop, the negative pole of the 4th diode is connected to the collector electrode of the tenth two-transistor in the output loop;
In described second control loop, the tenth transistorized collector electrode is connected to the base stage of the tenth two-transistor in the output loop.
6. Perceptual Load Drive Circuit as claimed in claim 5 is characterized in that, described Perceptual Load Drive Circuit also comprises:
The darlington structure that the 5th transistor and the 6th transistor are formed, wherein the collector electrode of the first transistor in the 5th transistorized base stage and the input circuit links to each other, the 5th transistorized grounded collector, the 5th transistorized emitter links to each other with the 6th transistorized base stage, the 6th transistorized emitter links to each other with power supply, the 6th transistor collector is by the second constant-current source ground connection, the 6th transistorized collector electrode again with output loop in the 11 transistorized base stage, the 8th transistorized base stage in first control loop and the positive pole of second diode in second control loop link to each other.
7. Perceptual Load Drive Circuit as claimed in claim 6 is characterized in that,
When the voltage signal of input is negative polarity, the first control loop work, the minimum value of first outputting drive voltage is the saturation voltage drop of the tenth two-transistor, and the maximum of first outputting drive voltage is: supply voltage-Di four constant-current source saturation voltage drops-2 * diode forward conducting voltage;
When the voltage signal of input is positive polarity, the second control loop work, the minimum value of second outputting drive voltage is: the transistorized saturation voltage drop of B-E knot pressure drop+tenth+the 9th transistor B-E of the tenth two-transistor ties pressure drop; The maximum of second outputting drive voltage is: supply voltage-Di 11 transistorized B-E knot pressure drop-Di six transistorized saturation voltage drops.
8. Perceptual Load Drive Circuit as claimed in claim 7 is characterized in that, the tenth transistor in second control loop is the PNP pipe, and the 9th transistor is the NPN pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200066283U CN2901696Y (en) | 2006-02-23 | 2006-02-23 | Inductive load driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2006200066283U CN2901696Y (en) | 2006-02-23 | 2006-02-23 | Inductive load driving circuit |
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| Publication Number | Publication Date |
|---|---|
| CN2901696Y true CN2901696Y (en) | 2007-05-16 |
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| CNU2006200066283U Expired - Lifetime CN2901696Y (en) | 2006-02-23 | 2006-02-23 | Inductive load driving circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105022440A (en) * | 2014-04-25 | 2015-11-04 | 奇景光电股份有限公司 | Voltage buffer |
-
2006
- 2006-02-23 CN CNU2006200066283U patent/CN2901696Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105022440A (en) * | 2014-04-25 | 2015-11-04 | 奇景光电股份有限公司 | Voltage buffer |
| CN105022440B (en) * | 2014-04-25 | 2017-04-12 | 奇景光电股份有限公司 | Voltage buffer |
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