CN2888737Y - Duplicated-frequency single-phase sine wave pulse width modulated output IP core - Google Patents
Duplicated-frequency single-phase sine wave pulse width modulated output IP core Download PDFInfo
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- CN2888737Y CN2888737Y CN 200520066734 CN200520066734U CN2888737Y CN 2888737 Y CN2888737 Y CN 2888737Y CN 200520066734 CN200520066734 CN 200520066734 CN 200520066734 U CN200520066734 U CN 200520066734U CN 2888737 Y CN2888737 Y CN 2888737Y
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Abstract
The utility model relates to a field of the inverse power supply technology, the programmable logic technology, the micro-control technology, in particular to a second-harmonic single-phase sine wave output pulse wide modulation IP-core, which comprises a bus controller, a pre-frequency dividing parameter setting unit, a modulation wave power supply frequency controller, a modulation wave phase control unit, a sine wave generating unit, a regular triangular wave generating unit, an inverse triangular wave generating unit, a PWM wave generating unit, a pulse deleting unit, a pulse delay unit, and a pulse blockade unit. The utility model inside generates the SPWM sequence by the sine wave generating unit, the inverse triangular wave generating unit, the pulse deleting unit, the PWM wave generating unit; so the control process is greatly simplified.
Description
[technical field]
The utility model relates to inverter technology, FPGA (Field Programmable Gate Array) technology and microcontroller technical field, relates in particular to the single-phase Sine Wave Pulse Width Modulation output of a kind of two frequencys multiplication IP kernel.
[background technology]
Sine Wave Pulse Width Modulation (SPWM) technology has a wide range of applications in the power electronic equipment that with the inverter circuit is core, and how producing SPWM pulse train and realization means thereof is keys of PWM technology.The one, the simulation comparison method of utilizing discrete component to build compares with triangular carrier and sinusoidal modulation wave, can produce the SPWM pulse.Next is digital algorithm and the timing logic that utilizes microprocessor to realize, also can produce the SPWM pulse.At present existing multiple microprocessor chip (as 80C196MC, TMS320F240 etc.) itself is integrated with Digital PWM generation circuit.Be conventional P WM control circuit once more, as SA866, SG3524 etc. by the digital integrated circuit formation of special integrated chip or middle and small scale.Analogy method circuit complexity is produced, debugging inconvenience, and with the inconvenience of digitial controller interface, it is serious that temperature is floated phenomenon, is difficult to satisfy complexity, high-precision requirement; Digital method, especially PWM generator that microprocessor is built-in, usually microprocessor is by regularly interrupt service routine generation SPWM pulse, structure is flexible, easy to use, but microprocessor must carry out Interrupt Process at each carrier cycle, processing speed is had relatively high expectations, thereby also having limited carrier frequency further improves, the Processing tasks of microprocessor is also heavier simultaneously, and uncertain interrupt response can cause the phase jitter of pwm pulse in the microprocessor, so that produce unthinkable result.Often there is complex circuit designs in the conventional P WM control circuit that digital integrated circuit by special integrated chip or middle and small scale constitutes, volume is big, poor anti jamming capability and difficult design, application-specific integrated circuit (ASIC) exists the supply of goods few simultaneously, source of goods instability, cause cost an arm and a leg, shortcoming such as the design cycle is long.
[utility model content]
The purpose of this utility model is to provide a kind of single-phase Sine Wave Pulse Width Modulation output of two frequencys multiplication IP kernel that can produce SPWM pulse train.
For achieving the above object, the utility model adopts following technical scheme: the single-phase Sine Wave Pulse Width Modulation output of a kind of two frequencys multiplication IP kernel comprises bus control unit, pre-frequency division parameter setting unit, the modulating wave power frequency controller, the modulating wave phase control unit, sinusoidal wave generating unit, positive triangular wave generating unit, anti-triangular wave generating unit, PWM ripple generating unit, the pulse delete cells, pulse daley unit and pulse blocking unit, described bus control unit and modulating wave power frequency controller, the modulating wave phase control unit is connected with pre-frequency division parameter setting unit, described PWM ripple generating unit with just, anti-triangular-wave generator, sinusoidal wave generating unit is connected with the pulse delete cells, described pulse daley unit is connected with the pulse blocking unit with the pulse delete cells, described modulating wave power frequency controller is worked bus control unit under 16 bit resolutions, pre-frequency division parameter setting unit, the modulating wave phase control unit, sinusoidal wave generating unit, positive triangular wave generating unit, anti-triangular wave generating unit, PWM ripple generating unit, the pulse delete cells, all work under 8 bit resolutions in pulse daley unit and pulse blocking unit.
Described sine waveform sampled data ROM preferably stores 256 or 512 0～90 ° of sine waves.
Described sine wave can replace with triangular wave and square wave.
The single-phase Sine Wave Pulse Width Modulation output of described two frequencys multiplication IP kernel is with the VHDL language design, compiles to draw under the Quartus of ALTERA II.
Described positive triangular wave generating unit is identical by pre-frequency division parameter setting unit given synchronised clock cooperation reversible counting unit realization output amplitude, frequency with anti-triangular wave generating unit, the triangular carrier that the phase phasic difference is 180 °.
Compared with prior art, the single-phase Sine Wave Pulse Width Modulation output of the utility model two frequencys multiplication IP kernel is inner to produce the SPWM sequence by sinusoidal wave generating unit, positive triangular wave generating unit, anti-triangular wave generating unit and PWM ripple generating unit, has therefore simplified control flow greatly.The single-phase Sine Wave Pulse Width Modulation output of this two frequency multiplication IP kernel can be embedded among the different FPGA or CPLD in addition, is applied to easily realize each different application demand among the different systems.
[description of drawings]
Fig. 1 is the single-phase Sine Wave Pulse Width Modulation output of the utility model two a frequencys multiplication IP kernel structural representation;
Fig. 2 is the process that sine wave and positive and negative triangular wave are realized two frequency multiplication waveforms.
[embodiment]
See also shown in Figure 1, the single-phase Sine Wave Pulse Width Modulation output of a kind of two frequencys multiplication IP kernel comprises bus control unit, pre-frequency division parameter setting unit, the modulating wave power frequency controller, the modulating wave phase control unit, sinusoidal wave generating unit, positive triangular wave generating unit, anti-triangular wave generating unit, PWM ripple generating unit, the pulse delete cells, pulse daley unit and pulse blocking unit, described bus control unit and modulating wave power frequency controller, the modulating wave phase control unit is connected with pre-frequency division parameter setting unit, described PWM ripple generating unit with just, anti-triangular-wave generator, sinusoidal wave generating unit is connected with the pulse delete cells, and described pulse daley unit is connected with the pulse blocking unit with the pulse delete cells.
The single-phase Sine Wave Pulse Width Modulation output of two frequencys multiplication IP kernel is to compile under the Quartus of ALTERA II with the VHDL language design to draw.The modulating wave power frequency controller is worked under 16 bit resolutions; All work under 8 bit resolutions in bus control unit, pre-frequency division parameter setting unit, modulating wave phase control unit, sinusoidal wave generating unit, positive triangular wave generating unit, anti-triangular wave generating unit, PWM ripple generating unit, pulse delete cells, pulse daley unit and pulse blocking unit.
Bus control unit comprises that RAM takes place for the multiplexing logic of bus and the address of finishing multiplexing logic of bus and address generation.Bus control unit read chip selection signal CS, address date control signal ALE, RD or WR effectively after, and choose modulating wave power frequency controller or modulating wave phase control unit, pre-frequency division parameter setting unit thus, then by data wire AD0～AD7 to modulating wave power frequency controller or modulating wave phase control unit, pre-frequency division parameter setting unit write parameters.
Pre-frequency division parameter setting unit is used to finish the setting of each cell parameters of the single-phase Sine Wave Pulse Width Modulation output of two frequencys multiplication IP kernel, provides the corresponding work frequency to each unit then.The modulating wave power frequency controller is used for the modulation wave frequency is set.
Sinusoidal wave generating unit comprises sine waveform sampled data ROM and reversible numeration unit.
Sine waveform sampled data ROM has stored 2
n0～90 ° the waveform sampling data of (n＜=10) individual sine wave.The ROM of sine waveform sampled data preferably stores 256 or 512 0～90 ° of sine waves.Sinusoidal wave original waveform sampled data also can be the waveform sampling data of corresponding triangular wave and square wave.
Reversible numeration unit is used to realize 0～255 at the carrier wave generating unit, and then counts from 255～0 circulation; Then realize 0～(2 at sinusoidal wave generating unit
n-1), and then from (2
n-1) cycle count～0.
The modulating wave phase control unit is used for the setting of offset of sinusoidal ripple initial phase, to satisfy the power supply output combination of 0～360 ° of phase difference.
Positive triangular wave generating unit is identical by pre-frequency division parameter setting unit given synchronised clock cooperation reversible counting unit realization output amplitude, frequency with anti-triangular wave generating unit, the triangular carrier that the phase phasic difference is 180 °.
PWM ripple generating unit by from the sine wave of sine waveform generating unit with regulate the multiply each other sinusoidal modulation wave that draws and just of parameter from the sine waveform amplitude of MCU, anti-two road triangular carriers compare and two road SPWM trains of impulses that draw, again with every road waveform negate and other two road SPWM pulse trains that draw respectively, four road SPWM trains of impulses of conversion generation just can directly be used for driving the MOSFET (field of electric force effect transistor) or the IGBT (igbt) of full-bridge inverting unit again through follow-up pulse deletion circuit and pulse delay circuit after isolating amplification thus.PWM ripple generating unit comprises the waveforms amplitude regulon.
See also shown in Figure 2, the realization of waveform series in inverter bridge of VG1～4 that relatively draw by modulating wave (sine wave) and positive and negative triangular wave.VG1 and VG4 the waveform shown in the VP occurred after VG2 and the VG3 stack, and the waveform output frequency shown in the VP is two times of frequency shown in VG1～VG4.
The pulse delete cells is used to realize narrow (less than 15 microseconds) pulse deletion, the deletion time of pulse can adjust according to the length of switching time of back power device, prevent under the situation that power device is not also opened fully, to close again, finally cause the power consumption of power tube to increase, temperature rises.The pulse deletion time is passed through the given parameter setting of MCU in frequency generation unit.
The pulse daley unit prevents same brachium pontis in the full-bridge inverting unit because the shoot through phenomenon that the electric current turn-off delay of power tube causes takes place.Can be according to power device by frequency generation unit by the given parameter change of MCU pulse delay time.
The pulse blocking control circuit is realized three functions: one: power-on pulse output is blocked; The 2nd, fault is turn-offed fast, the design of this function can be crossed the direct paired pulses blockade of MCU unit and be controlled, provide index signal simultaneously and carry out sound and light alarm, this signal in case effectively could be removed pulse blocking when having only start again or Global reset circuit effective; The 3rd; the MCU locking signal is made normal protection action: for example; have one to exceed normal range (NR) mutually if detect electric current, voltage, temperature during the closed-loop control of circuit; MCU will send the output of signal locking pulse; if the too high then open circuit again when temperature drops to permissible value of temperature, otherwise send the indication of reporting to the police.
The utility model is by being example with sinusoidal wave generating unit, positive triangular wave generating unit, anti-triangular wave generating unit and PWM ripple generating unit, introduced the single-phase Sine Wave Pulse Width Modulation output of a kind of two frequencys multiplication IP kernel, this can not be considered to the restriction to the utility model claim.If those skilled in the art has made change unsubstantiality, conspicuous or improvement according to the utility model, all should belong to the scope of the utility model claim protection.
Claims (4)
1, the single-phase Sine Wave Pulse Width Modulation output of a kind of two frequencys multiplication IP kernel, it is characterized in that: above-mentioned IP kernel comprises bus control unit, pre-frequency division parameter setting unit, the modulating wave power frequency controller, the modulating wave phase control unit, sinusoidal wave generating unit, positive triangular wave generating unit, anti-triangular wave generating unit, PWM ripple generating unit, the pulse delete cells, pulse daley unit and pulse blocking unit, described bus control unit and modulating wave power frequency controller, the modulating wave phase control unit is connected with pre-frequency division parameter setting unit, described PWM ripple generating unit with just, anti-triangular-wave generator, sinusoidal wave generating unit is connected with the pulse delete cells, described pulse daley unit is connected with the pulse blocking unit with the pulse delete cells, described modulating wave power frequency controller is worked bus control unit under 16 bit resolutions, pre-frequency division parameter setting unit, the modulating wave phase control unit, sinusoidal wave generating unit, positive triangular wave generating unit, anti-triangular wave generating unit, PWM ripple generating unit, the pulse delete cells, all work under 8 bit resolutions in pulse daley unit and pulse blocking unit.
2, the single-phase Sine Wave Pulse Width Modulation output of two frequencys multiplication according to claim 1 IP kernel, it is characterized in that: the ROM of described sine waveform sampled data has stored 2
nIndividual 0～90 ° of sine waveform sampled data, wherein n＜=10.
3, the single-phase Sine Wave Pulse Width Modulation output of two frequencys multiplication according to claim 2 IP kernel is characterized in that: described sine wave can replace with triangular wave or square wave.
4, the single-phase Sine Wave Pulse Width Modulation output of two frequencys multiplication according to claim 1 IP kernel, it is characterized in that: described positive triangular wave generating unit is identical by pre-frequency division parameter setting unit given synchronised clock cooperation reversible counting unit realization output amplitude, frequency with anti-triangular wave generating unit, the triangular carrier that the phase phasic difference is 180 °.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200520066734 CN2888737Y (en) | 2005-11-03 | 2005-11-03 | Duplicated-frequency single-phase sine wave pulse width modulated output IP core |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200520066734 CN2888737Y (en) | 2005-11-03 | 2005-11-03 | Duplicated-frequency single-phase sine wave pulse width modulated output IP core |
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| CN2888737Y true CN2888737Y (en) | 2007-04-11 |
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| CN 200520066734 Expired - Fee Related CN2888737Y (en) | 2005-11-03 | 2005-11-03 | Duplicated-frequency single-phase sine wave pulse width modulated output IP core |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102312737A (en) * | 2011-03-15 | 2012-01-11 | 隆鑫通用动力股份有限公司 | Frequency doubling inversing method and device for internal combustion engine driven generator |
-
2005
- 2005-11-03 CN CN 200520066734 patent/CN2888737Y/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102312737A (en) * | 2011-03-15 | 2012-01-11 | 隆鑫通用动力股份有限公司 | Frequency doubling inversing method and device for internal combustion engine driven generator |
| WO2012122895A3 (en) * | 2011-03-15 | 2012-11-08 | 隆鑫通用动力股份有限公司 | Multiple-frequency inversion method and control apparatus for internal-combustion driven generator |
| CN102312737B (en) * | 2011-03-15 | 2013-06-19 | 隆鑫通用动力股份有限公司 | Frequency doubling inversing method and device for internal combustion engine driven generator |
| US8712666B2 (en) | 2011-03-15 | 2014-04-29 | Loncin Motor Co., Ltd. | Multiple-frequency inversion method and control apparatus for internal combustion engine driven generator |
| RU2587170C2 (en) * | 2011-03-15 | 2016-06-20 | Лонсин Мотор Ко., Лтд. | Method for inversion with multiplication of frequency and generator control device driven by internal combustion engine |
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| CF01 | Termination of patent right due to non-payment of annual fee |