CN2876800Y - RF signal receiver device for global positioning system and compass second generation double system - Google Patents
RF signal receiver device for global positioning system and compass second generation double system Download PDFInfo
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- CN2876800Y CN2876800Y CNU2005200796332U CN200520079633U CN2876800Y CN 2876800 Y CN2876800 Y CN 2876800Y CN U2005200796332 U CNU2005200796332 U CN U2005200796332U CN 200520079633 U CN200520079633 U CN 200520079633U CN 2876800 Y CN2876800 Y CN 2876800Y
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Abstract
The utility model discloses an RF signal receiver device for global positioning system (GPS) and compass second generation double system which can receive the signals of band L1 of the GPS, band B1 and band B2 of the compass second generation double system. The application of down-conversion structure integrates a low noise amplifier, a mixer, an IF filter, a frequency synthesizer, an analog-to-digital converter, an automatic gain control signal amplifier into a unitary RF signal receiver. The major role of the RF signal receiver is to convert the satellite signal from the GPS and the signal from compass second generation satellite navigation system (SNS) within the range of RF frequency into the intermediate frequency, which enters the analog-to-digital converter after being amplified for the purpose of sampling the intermediate frequency analog signal as digital signal for output. The structure is simplified and the size and power consumption of the receiver are reduced. The receiver is widely used in the fields of traffic vehicles, ships, etc, featuring small size and low power consumption, with better social and economical benefits.
Description
Technical field
The utility model relates to a kind of video receiver device, particularly suitable is that the compatible GPS (GPS) and the signal of the Big Dipper two generations NAVSTAR receive, simultaneously the video receiver device of receiving world locational system L1 band signal, the Big Dipper two generations B1 wave band and B2 band signal.
Background technology
At present, the GPS video receiver is widely used, and the Big Dipper two generations NAVSTAR signal receiver also is implemented, but does not occur the signal receiver device of compatible dual system signal receiving function as yet.The signal receiver that possesses compatible dual system signal receiving function is accurate localization more not only, and can break away from the compatible global location of the dependence of single navigational system and the video receiver device of the Big Dipper two generations satellite positioning navigation.
Summary of the invention
The purpose of this utility model is in order to overcome the deficiencies in the prior art, not only accurate localization more of a kind of signal receiver that possesses compatible dual system signal receiving function is provided, and can breaks away from the compatible global location of the dependence of single navigational system and the video receiver device of the Big Dipper two generations satellite positioning navigation.The signal receiver device that possesses compatible dual system signal receiving function, accurate localization more not only, and can break away from dependence to single navigational system, improved reliability.Compatible GPS (GPS) and the Big Dipper two generations NAVSTAR, energy is the video receiver of receiving world locational system L1 band signal, the Big Dipper two generations B1 wave band and B2 band signal simultaneously, and structure is simplified, reduced the area and the power consumption of receiver.
The technical solution of the utility model is to solve like this: its improvements of the present utility model are this reception function receiving world locational system band signal simultaneously, the Big Dipper two generations band signal, by adopting the down coversion structure one time, with low noise amplifier, frequency mixer, intermediate-frequency filter, frequency synthesizer, the modulus signal converter, the integrated whole video receiver of automatic gaining controling signal amplifier, the input signal of the radiofrequency signal of described band signal circuit enters low noise amplifier, the output signal of low noise amplifier enters frequency mixer, the output signal of frequency mixer enters intermediate-frequency filter, the output signal of intermediate-frequency filter enters the automatic gaining controling signal amplifier, the output signal of automatic gaining controling signal amplifier enters the modulus signal converter, modulus signal converter output digital signal, the output signal of frequency synthesizer is a local oscillated signal, and local oscillated signal enters frequency mixer.
Comprise three signal paths in the video receiver system architecture:
The L1 path, receiving frequency is the L1 band signal circuit of the GPS of 1575.42MHz;
The B1 path, receiving frequency is the Big Dipper two generations B1 band signal circuit of 1561.098MHz;
The B2 path, receiving frequency is the Big Dipper two generations B2 band signal circuit of 1207.14MHz.
Signal receives principle: adopt one time the down coversion structure, radiofrequency signal is at first amplified signal by low noise amplifier, and guarantees extremely low noise figure; Signal is delivered to frequency mixer after amplifying, the local oscillated signal that provides with frequency synthesizer in the frequency mixer carries out down coversion to radiofrequency signal, and signal frequency is dropped to intermediate frequency range; Enter the automatic gaining controling signal amplifier after the intermediate-freuqncy signal process intermediate-frequency filter filtering that obtains and amplify, its gain coefficient size is determined by the strong and weak degree of satellite-signal, and can regulate in a big way; Intermediate-freuqncy signal is through being amplified into the modulus signal converter, and its effect is that analog intermediate frequency signal is sampled as digital signal output.
L1 path and same low noise amplifier of B1 path sharing and same frequency synthesizer, the bandwidth of this low noise amplifier is more than 17MHz, the local oscillated signal frequency of frequency synthesizer output is 1.571GHz, in the L1 path frequency mixer output the intermediate-freuqncy signal frequency at 4.092MHz, in the B1 path frequency mixer output the intermediate-freuqncy signal frequency at 10.23MHz.The B2 path adopts independently low noise amplifier and frequency synthesizer, and the local oscillated signal frequency of frequency synthesizer output is 1.215GHz, frequency mixer output the intermediate-freuqncy signal frequency at 8.184MHz.
The beneficial effects of the utility model are the signal receiver devices that possess compatible dual system signal receiving function, accurate localization more not only, and can break away from dependence to single navigational system, improved reliability.Compatible GPS (GPS) and the Big Dipper two generations NAVSTAR, energy is the video receiver of receiving world locational system L1 band signal, the Big Dipper two generations B1 wave band and B2 band signal simultaneously, and structure is simplified, the area and the power consumption of receiver have been reduced, be widely used among the GPS receiver radio frequency chip HXM001RF, field such as transportation and communication, ship, adopt 0.35 micron germanium silicon technology design to produce, and test successfully, good society and economic benefit are arranged.
Description of drawings
Fig. 1 is the utility model radio-frequency transmitter device one-piece construction schematic block diagram;
Fig. 2 is the circuit theory diagrams of the low noise amplifier of Fig. 1;
Fig. 3 is the schematic diagram of the mixer of Fig. 1;
Fig. 4 is the schematic diagram of the intermediate-frequency filter circuit of Fig. 1;
Fig. 5 is the circuit theory diagrams of the automatic gaining controling signal amplifier of Fig. 1;
Fig. 6 is the circuit theory diagrams of the modulus signal converter of Fig. 1;
Fig. 7 is the structured flowchart of the frequency synthesizer of Fig. 1;
Fig. 8 is the circuit theory diagrams of the voltage controlled oscillator of Fig. 7;
Fig. 9 is the circuit theory diagrams of the phase-locked loop module of Fig. 7;
Figure 10 is the circuit theory diagrams that the orthogonal signal of Fig. 7 produce circuit.
Embodiment
Accompanying drawing is embodiment of the present utility model
Below in conjunction with accompanying drawing summary of the invention of the present utility model is described further:
With reference to shown in Figure 1, comprise three signal paths in the video receiver system architecture:
The L1 path, receiving frequency is the L1 band signal of the GPS of 1575.42MHz;
The B1 path, receiving frequency is the Big Dipper two generations B1 band signal of 1561.098MHz;
The B2 path, receiving frequency is the Big Dipper two generations B2 band signal of 1207.14MHz.
The signal of each signal path receives principle: by adopting the down coversion structure one time, by low noise amplifier 2, frequency mixer 3, intermediate-frequency filter 6, frequency synthesizer 4, modulus signal converter 8, automatic gaining controling signal amplifier 7 is formed a video receiver, the input signal of described radiofrequency signal 1 enters low noise amplifier 2, the output signal of low noise amplifier 2 enters frequency mixer 3, the output signal of frequency mixer 3 enters intermediate-frequency filter 6, the output signal of intermediate-frequency filter 6 enters automatic gaining controling signal amplifier 7, the output signal of automatic gaining controling signal amplifier 7 enters modulus signal converter 8, modulus signal converter 8 output digital signals 9, the output signal of frequency synthesizer 4 is a local oscillated signal 5, and local oscillated signal 5 enters frequency mixer 3.Radiofrequency signal is at first amplified signal by low noise amplifier after introducing integrated radio frequency chip, and guarantees extremely low noise figure; Signal is delivered to frequency mixer after amplifying, the local oscillated signal that provides with frequency synthesizer in the frequency mixer carries out down coversion to radiofrequency signal, and signal frequency is dropped to intermediate frequency range; Enter the automatic gaining controling signal amplifier after the intermediate-freuqncy signal process intermediate-frequency filter filtering that obtains and amplify, its gain coefficient size is determined by the strong and weak degree of satellite-signal, and can regulate in a big way; Intermediate-freuqncy signal is through being amplified into the modulus signal converter, and its effect is that analog intermediate frequency signal is sampled as digital signal output.L1 path and same low noise amplifier of B1 path sharing and same frequency synthesizer, the bandwidth of this low noise amplifier is more than 17MHz, the local oscillated signal frequency of frequency synthesizer output is 1.571GHz, in the L1 path frequency mixer output the intermediate-freuqncy signal frequency at 4.092MHz, in the B1 path frequency mixer output the intermediate-freuqncy signal frequency at 10.23MHz.The B2 path adopts independently low noise amplifier and frequency synthesizer, and the local oscillated signal frequency of frequency synthesizer output is 1.215GHz, frequency mixer output the intermediate-freuqncy signal frequency at 8.184MHz.
Fig. 2 is the circuit theory diagrams of the low noise amplifier of Fig. 1, and input is a radio-frequency (RF) signal input end among the figure, and output is the radiofrequency signal output terminal; Voltage source vcc divides two-way to be connected with current source i1 one end, another road respectively with capacitor C 1, inductance L 1, capacitor C 2 is connected in parallel, capacitor C 1 one end ground connection, inductance L 1, the other end of capacitor C 2 is connected with the collector of triode Q2, the current source i1 other end is connected with the collector of triode Q3, two triode Q2, the base stage of Q3 links to each other, capacitor C 3 also in parallel in the middle of them, the collector of triode Q2 and base stage short circuit, triode Q2, the emitter of Q3 respectively with triode Q1, the collector of Q4 connects, its two triode Q1, the base stage of Q4 is connected in series with resistance R 1 respectively, R2, resistance R 2 is connected with the node i nput radio-frequency (RF) signal input end of the base stage of triode Q1, triode Q1, the emitter of Q4 is in parallel to be connected with ground, also is connected with output radiofrequency signal output terminal after the serial connection capacitor C 4 on the collector of triode Q2.
Fig. 3 is the schematic diagram of the mixer of Fig. 1, RF_in is the radio-frequency (RF) signal input end that comes from low noise amplifier, LO_in is the local oscillated signal input end that comes from frequency synthesizer, and IF_out is the intermediate-freuqncy signal output terminal after radiofrequency signal and the local oscillated signal mixing; The local oscillated signal input anode is connected with the base stage of triode Q5, be connected in series with resistance R 6, R7 on the collector of triode Q5, Q6, the other end of resistance R 6, R7 is connected with resistance R 3 and capacitor C 8 respectively, the two emitters series connection of triode Q5, Q6, the base stage of triode Q6 links to each other with the local oscillated signal input cathode, two emitters of triode Q5, Q6 link to each other with the collector of triode Q11 again, the emitter of triode Q11 connects a resistance R 12 and is connected with ground, and the base stage of triode Q11 is parallel with triode Q12 base stage, voltage source V 2 respectively; The emitter of triode Q12 connects a resistance R 13 and is connected with ground; The resistance R 3 and capacitor C 8 other ends are parallel resistance R4, R5 respectively, resistance R 4, R5 other end capacitor C 5, C6 link to each other with the collector of triode Q7, Q10, triode Q7 connects with the emitter of triode Q8, triode Q8, the series connection of Q9 base stage, triode Q9 collector is connected on the collector of triode Q7, and triode Q8 collector is connected on the collector of triode Q10; Triode Q10 base stage is in parallel with the base stage of triode Q7 and insert on the collector of triode Q6, triode Q7, Q8 and triode Q9, the emitter of Q10 respectively with triode Q7-1, the collector of Q9-1 links to each other, triode Q7-1, the emitter of Q9-1 is connected in series with resistance R 10, R11, triode Q7-1, the base stage two-way of Q9-1 and resistance R 8, R9 links to each other with the radio-frequency (RF) signal input end of low noise amplifier 2, resistance R 8, the other end of R9 is connected with voltage source V 1 and ground connection, the base stage of triode Q9-1 is connected with capacitor C 7 and ground connection, resistance R 4, R5 also is linked into the negative pole and the positive pole of intermediate-freuqncy signal output terminal respectively.
Fig. 4 is the schematic diagram of the intermediate-frequency filter circuit of Fig. 1, and INPUT is the signal input end of intermediate frequency that comes from frequency mixer, and OUTPUT is the filtered intermediate-freuqncy signal output terminal of process; The signal input end of intermediate frequency that comes from frequency mixer 3 is connected in series with resistance R 16 successively, R18, its bypass is connected with resistance R 14, resistance R 18 other ends respectively with capacitor C 7, the base stage of triode Q15 is connected, the collector of triode Q15 respectively with the base stage of triode Q13, capacitor C 40, field effect transistor M1 connects, field effect transistor M1, M2 links to each other, the two node is connected with field effect transistor M4, field effect transistor M3 and field effect transistor M5, field effect transistor M4 and field effect transistor M6 join, the base stage of triode Q14 links to each other with the source electrode of M2, the collector of Q14 connects power supply, triode Q13, the emitter connection in series-parallel resistance R 20 of Q14, behind the R21 again respectively with triode Q17, the collector of Q19 connects, field effect transistor M1 also is connected with the collector of triode Q15, field effect transistor M2 also is connected with the collector of triode Q16, triode Q15, the emitter of Q16 connects the back and inserts on the collector of triode Q18, triode Q17, Q18, Q19, the Q20 base stage, ground connection after voltage source V 3 is connected in series, resistance in series R22 successively on its each emitter, R23, R24, ground connection behind the R25, field effect transistor M6 serial connection voltage source V 4 back ground connection, the collector of triode Q18 is connected triode Q15, on the emitter of Q16, the base stage series resistor R19 of triode Q16, R17, the other end of resistance R 17 inserts the negative pole of the signal input end of intermediate frequency that comes from frequency mixer 3, resistance R 19 two ends also be connected in parallel resistance R 15 and capacitor C 8, resistance R 16, the end of R17 is shunt capacitance C5 also, C6, the emitter of triode Q13 inserts the positive pole of intermediate-freuqncy signal output terminal, the emitter of triode Q14 inserts the negative pole of intermediate-freuqncy signal output terminal, and an end of resistance R 14 and capacitor C 7 is linked into the positive pole of intermediate-freuqncy signal output terminal.
Fig. 5 is the circuit theory diagrams of the automatic gaining controling signal amplifier of Fig. 1, IF_in is the signal input end of intermediate frequency that comes from intermediate-frequency filter, IF_out is process amplified IF signal output terminal, and Vcon is the control voltage signal input end of control amplifier gain coefficient; The capacitor C 15 of positive pole serial connection that comes from the signal input end of intermediate frequency of intermediate-frequency filter 6, the other end of capacitor C 15 divide two-way respectively with the base stage of triode Q21, resistance R 27 1 ends connect, the other end inserts on the power supply VCC, connect a resistance R 28 on the collector of triode Q21, emitter links to each other with the emitter of triode Q22, connect a resistance R 29 on the collector of triode Q22, triode Q21, the base stage of Q24 links to each other, connection in series-parallel has resistance R 34 on the emitter of triode Q23 and Q24, R35, triode Q23, connect a capacitor C 18 on the collector of Q24 respectively, C17, emitter series resistor R34, R35, resistance R 26, R27, R28, R29, R30, R31, R32, the end of R33 is connected in parallel on the power supply VCC successively respectively, the other end of its resistance R 30 is connected on the base stage of the other end of capacitor C 18 and triode Q26, the other end of resistance R 31 is connected on the base stage of the other end of capacitor C 17 and triode Q25, the other end of resistance R 32 is connected on the negative pole of the collector of triode Q25 and intermediate-freuqncy signal output terminal, the other end of resistance R 33 is connected on the positive pole of the collector of triode Q26 and intermediate-freuqncy signal output terminal, triode Q25, the base stage of Q27 links to each other, the collector of triode Q27 links to each other with the negative pole of intermediate-freuqncy signal output terminal, emitter series resistor R36, R37 inserts on the emitter of triode Q28, its collector links to each other with the positive pole of intermediate-freuqncy signal output terminal, resistance R 36, node connects on the collector of triode Q32 between the R37, the base stage of the triode Q32 triode Q31 that is linked in sequence, Q30, the base stage of Q29, emitter series resistor R41 and field effect transistor M10, the other end of field effect transistor M10 respectively with field effect transistor M9, M8, M7 is connected in parallel, field effect transistor M9, M8, the other end of M7 respectively with resistance R 40, R39, R38 one end connects, the other end again respectively with triode Q31, Q30, the emitter of Q29 connects, its collector is connected to triode Q26, on the emitter of Q22 and resistance R 34 other ends, reverser inv1 of other end serial connection of field effect transistor M7, also join and ground connection the control voltage signal input end of the other end Access Control amplifier gain coefficient of reverser inv1 on the base stage of triode Q29 with voltage source V 5.
Fig. 6 is the circuit theory diagrams of the modulus signal converter of Fig. 1, and IF_in is the signal input end of intermediate frequency that comes from the automatic gaining controling signal amplifier, and this signal is a simulating signal, and C_out is the digital signal output end after conversion; The positive pole serial connection capacitor C 19 that comes from the signal input end of intermediate frequency of automatic gaining controling signal amplifier, capacitor C 19 other ends divide two-way to be connected with the base stage of resistance R 43 with triode Q34 respectively, the emitter of triode Q34 is connected with the base stage of triode Q35, its emitter is connected with the emitter of triode Q36 again, the collector of triode Q35 divides two-way to be connected with the base stage of resistance R 44 with triode Q38 respectively, one end of resistance R 45 divide two-way respectively with the collector of triode Q36, the base stage of Q37 is connected, one end of resistance R 46 divide two-way respectively with the collector of triode Q37, the base stage of Q39 is connected, triode Q39, the emitter of Q40 connects, one end of resistance R 47 divide two-way respectively with the collector of triode Q38, the base stage of Q39 is connected, resistance R 42, R43, R44, R45, R46, the R47 other end inserts on the power supply VCC, field effect transistor M11 is connected with M12, field effect transistor M13 is connected with M14, simultaneously field effect transistor M11 also with M19, M20 connects, M12, M13 and triode Q39, the collector of Q40 connects, M14, M20 connects, M15, M16 connects, M17, M18 connects, triode Q35 and Q36, Q37 and Q38, the emitter node of Q39 and Q40 inserts triode Q44 respectively, Q45, on the collector of Q46, triode Q33, the emitter series resistor R48 of Q34, R49 inserts triode Q42 respectively, on the collector of Q43, triode Q41, Q42, Q43, Q44, Q45, series resistor R50 successively on the emitter of Q46, R51, R52, R53, R54, R55, its each resistance and field effect transistor M19, M20, M16, the other end of M18 also inserts power supply VCC and goes up ground connection, the negative pole serial connection capacitor C 20 that comes from the signal input end of intermediate frequency of automatic gaining controling signal amplifier, capacitor C 20 other ends divide two-way to be connected with the base stage of resistance R 42 with triode Q33 respectively, triode Q41, Q42, the base stage of Q43 connects, connect current source i2, field effect transistor M17 on the triode Q41 collector, the termination of M18 is gone on the digital signal output end C_out after the conversion.
Fig. 7 is the structured flowchart of the frequency synthesizer of Fig. 1, and wherein VCO is a voltage controlled oscillator, produces oscillator signal clk_vco; PLL is a phase-locked loop module, and clk_vco is carried out bit comparison mutually with outside input reference clock signal clk_ref, and produce one control voltage the frequency of clk_vco is regulated; IQ is that orthogonal signal produce circuit, converts clk_vco to four quadrature phases signal by differential signal, and orthogonal signal are exported as local oscillated signal L0.
Fig. 8 is the circuit theory diagrams of the voltage controlled oscillator of Fig. 7, and OUTPUT is the output terminal by the oscillator signal clk_vco of voltage controlled oscillator generation, and Vtune is the input end of oscillation signal frequency control voltage; Power supply VCC is serially connected in the end of current source i3, its other end is connected in series with resistance R 56 successively, R57, R58 and ground connection, resistance R 56 1 ends are parallel resistance R59 and R60 also, the other end of resistance R 60 inserts the variable capacitance Ct1 by capacitor C 23 serial connections, Ct2, on the node of capacitor C 24, one termination of resistance R 61 is gone into the variable capacitance Ct3 by capacitor C 25 serial connections, Ct4, on the node of capacitor C 26, capacitor C 23, the other end of C25 and inductance L 2, resistance R 62, the collector of triode Q47 connects, the emitter of triode Q47 respectively with triode Q49, the collector of Q50 connects, its emitter is series resistor R63 respectively, R64, resistance R 63, the other end ground connection of R64, resistance R 60, the other end of R62 is connected to capacitor C 21 respectively, C22 and ground connection, triode Q47, the base stage intersection of Q48 is connected on triode Q47, on the collector of Q48, the emitter of triode Q48 and triode Q50, the base stage of Q52, the emitter of Q51 connects, its collector is connected capacitor C 26, C24, C27, on one end of inductance L 3 and the base stage of triode Q60, on the power supply VCC successively respectively with inductance L 2, inductance L 3, the collector of triode Q51, current source i4, triode Q59, Q60, the collector of Q57, current source i5 one end connects, triode Q51, Q52, Q53, Q54, Q55, Q56, Q57, the emitter of Q58 is series resistor R65 successively, R66, R67, R68, R69, R70, R71, R72 and triode Q52, the Q58 bypass is connected with capacitor C 28, C29 and ground connection, triode Q53, Q54, Q55, Q56, the base stage of Q58 is connected in series, triode Q53, the collector of Q55 links to each other, the collector of triode Q54 links to each other with the emitter of triode Q59, the collector of triode Q55 links to each other with the emitter of Q60, the collector of triode Q56 links to each other with the emitter of triode Q60, triode Q59, the output of the emitter of Q60 and oscillator signal clk_vco is rectified, negative pole links to each other.
Fig. 9 is the circuit theory diagrams of the phase-locked loop module of Fig. 7, CLK_REF is outside input reference clock signal input end, CLK_VCO is the input end of the oscillator signal of voltage controlled oscillator generation, the control voltage output end of Vtune for the voltage controlled oscillator oscillation signal frequency is regulated, the Dff module is a d type flip flop, DIV is an allocator module, and its concrete parameter is determined by range of application; Outside input reference clock signal input end CLK_REF connects a module Dff, module Dff respectively with reverser inv2, rejection gate nor1, Sheffer stroke gate nand1, power supply VCC connects, the other end of reverser inv2 is connected with the end of field effect transistor M21, the other end of field effect transistor M21 is serially connected with successively and connects field effect transistor M22, control voltage output end Vtune, M23, M24, field effect transistor M22, the end of M23 and voltage source V 6, V7 connects ground connection, field effect transistor M24 divides two-way to be connected to the both sides, bottom right of the second module Dff, rejection gate nor1 one end is connected the right side of the second module Dff, Sheffer stroke gate nand1 one end is connected with the end of field effect transistor M21, the left side of the second module Dff connects an allocator module DIV, the input end CLK_VCO of the oscillator signal that allocator module DIV and voltage controlled oscillator produce is connected, control voltage output end Vtune respectively connection in series-parallel resistance R 73 is arranged, capacitor C 30, C31 and ground connection.
Figure 10 is the circuit theory diagrams that the orthogonal signal of Fig. 7 produce circuit, LO_in is the input end that comes from the oscillator signal clk_vco of voltage controlled oscillator, output1 and output2 are the output terminal of the local oscillated signal with four orthogonal signal phase places of generation, wherein output1 and output2 respectively have two output terminals, their phase place differs 180 degree respectively, and the respective signal phase place of output1 and output2 differs 90 degree respectively; Come from resistance in series R74 on the positive pole of an end of oscillator signal input end clk_vco of voltage controlled oscillator, R75 inserts the positive pole of the output terminal output1 of local oscillated signal, resistance R 74, bypass one end of R75 is connected with capacitor C 32 respectively, C33 inserts resistance R 76, on the node of R77, resistance R 76, bypass one end of R77 is connected with capacitor C 34 respectively, C35 inserts resistance R 78, on the node of R79, resistance R 78, bypass one end of R79 is connected with capacitor C 36 respectively, C37 inserts resistance R 80, on the node of R81, resistance R 80, be connected with capacitor C 38 respectively on the other end node of R81, C39, capacitor C 38, the other end of C39 inserts resistance R 74, on the node of R75, capacitor C 35, the other end of capacitor C 39 is linked on the positive pole of output terminal output1 of local oscillated signal, capacitor C 35, the node of R79 is linked on the negative pole of output terminal output1 of local oscillated signal, capacitor C 37, on the negative pole of the output terminal output2 of the node access local oscillated signal of resistance R 81, capacitor C 33, on the positive pole of the output terminal output2 of the node access local oscillated signal of resistance R 77, capacitor C 36, resistance R 78, capacitor C 38, the node of resistance R 80 is linked into the negative pole of the output terminal output1 of local oscillated signal.
In sum, the utility model is widely used among the GPS receiver radio frequency chip HXM002RF, adopts 0.35 micron germanium silicon technology design to produce, and tests successfully.
Claims (4)
1, a kind of GPS and the Big Dipper two generations dual system video receiver device, it is characterized in that this receiver apparatus receiving world locational system band signal (L1) simultaneously, the Big Dipper two generations band signal (B1) and band signal (B2), by adopting the down coversion structure one time, with low noise amplifier (2), frequency mixer (3), intermediate-frequency filter (6), frequency synthesizer (4), modulus signal converter (8), the integrated whole video receiver of automatic gaining controling signal amplifier (7), the input signal of the radiofrequency signal (1) of described band signal (B2) circuit enters low noise amplifier (2), the output signal of low noise amplifier (2) enters frequency mixer (3), the output signal of frequency mixer (3) enters intermediate-frequency filter (6), the output signal of intermediate-frequency filter (6) enters automatic gaining controling signal amplifier (7), the output signal of automatic gaining controling signal amplifier (7) enters modulus signal converter (8), modulus signal converter (8) output digital signal (9), the output signal of frequency synthesizer (4) is local oscillated signal (5), local oscillated signal (5) enters frequency mixer (3), the described Big Dipper two generations band signal (B1) circuit and shared low noise amplifier of band signal (L1) circuit (2) and frequency synthesizer (4), other circuit structures are identical with band signal (B2) circuit.
2, GPS according to claim 1 and the Big Dipper two generations dual system video receiver device is characterized in that described video receiver comprises three signal paths:
Wherein the reception frequency of band signal (L1) path is the L1 band signal of the GPS of 1575.42MHz;
Wherein the reception frequency of band signal (B1) path is the Big Dipper two generations B1 band signal of 1561.098MHz;
Wherein the reception frequency of band signal (B2) path is the Big Dipper two generations B2 band signal of 1207.14MHz.
3, GPS according to claim 1 and the Big Dipper two generations dual system video receiver device, it is characterized in that described band signal (L1) path and the same low noise amplifier of band signal (B1) path sharing (2) and same frequency synthesizer (4), the bandwidth of this low noise amplifier (2) is more than 17MHz, the local oscillated signal frequency of frequency synthesizer (4) output is 1.571GHz, in band signal (L1) path frequency mixer (3) output the intermediate-freuqncy signal frequency at 4.092MHz, in band signal (B1) path frequency mixer (3) output the intermediate-freuqncy signal frequency at 10.23MHz.
4, GPS according to claim 1 and the Big Dipper two generations dual system video receiver device, it is characterized in that described band signal (B2) path adopts independently low noise amplifier (2) and frequency synthesizer (4), local oscillated signal (5) frequency of frequency synthesizer (4) output is 1.215GHz, frequency mixer (3) output the intermediate-freuqncy signal frequency at 8.184MHz.
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| CNU2005200796332U CN2876800Y (en) | 2005-11-03 | 2005-11-03 | RF signal receiver device for global positioning system and compass second generation double system |
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| CNU2005200796332U CN2876800Y (en) | 2005-11-03 | 2005-11-03 | RF signal receiver device for global positioning system and compass second generation double system |
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| WO2008144990A1 (en) * | 2007-05-25 | 2008-12-04 | Olinkstar Corporation, Ltd. | A general configurable rf processing method and system for navigation satellite signal |
| CN101915932A (en) * | 2010-06-12 | 2010-12-15 | 北京航空航天大学 | Radio frequency front-end device for dual-system and dual-frequency navigation receiver |
| CN102305934A (en) * | 2011-05-13 | 2012-01-04 | 陕西长岭电子科技有限责任公司 | Dual-channel radio-frequency signal processing module for navigation receiver |
| CN101872010B (en) * | 2009-04-24 | 2012-05-23 | 郑州威科姆科技股份有限公司 | Big Dipper/GPS (Global Position System) signal power divider and manufacture method thereof and dual-system radio frequency receiving module |
| CN102937715A (en) * | 2012-10-09 | 2013-02-20 | 桂林电子科技大学 | BD1 (Beidou 1) and BD2 radio frequency compatible receiving method and device |
| CN103095318A (en) * | 2013-01-17 | 2013-05-08 | 陕西北斗恒通信息科技有限公司 | Anti-interference radio-frequency receiving system |
| CN103513260A (en) * | 2012-06-14 | 2014-01-15 | 索尼公司 | Receiver |
| CN104237913A (en) * | 2014-09-03 | 2014-12-24 | 北京一朴科技有限公司 | GNSS software receiver architecture system |
| CN108072884A (en) * | 2017-09-18 | 2018-05-25 | 西安交通大学 | Global positioning system and Beidou satellite navigation system single channel dual-mode radio frequency receiver |
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2005
- 2005-11-03 CN CNU2005200796332U patent/CN2876800Y/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2008144990A1 (en) * | 2007-05-25 | 2008-12-04 | Olinkstar Corporation, Ltd. | A general configurable rf processing method and system for navigation satellite signal |
| CN101872010B (en) * | 2009-04-24 | 2012-05-23 | 郑州威科姆科技股份有限公司 | Big Dipper/GPS (Global Position System) signal power divider and manufacture method thereof and dual-system radio frequency receiving module |
| CN101915932A (en) * | 2010-06-12 | 2010-12-15 | 北京航空航天大学 | Radio frequency front-end device for dual-system and dual-frequency navigation receiver |
| CN101915932B (en) * | 2010-06-12 | 2012-07-25 | 北京航空航天大学 | Radio frequency front-end device for dual-system and dual-frequency navigation receiver |
| CN102305934A (en) * | 2011-05-13 | 2012-01-04 | 陕西长岭电子科技有限责任公司 | Dual-channel radio-frequency signal processing module for navigation receiver |
| CN103513260A (en) * | 2012-06-14 | 2014-01-15 | 索尼公司 | Receiver |
| CN103513260B (en) * | 2012-06-14 | 2017-09-08 | 索尼半导体解决方案公司 | Receiver |
| CN102937715A (en) * | 2012-10-09 | 2013-02-20 | 桂林电子科技大学 | BD1 (Beidou 1) and BD2 radio frequency compatible receiving method and device |
| CN103095318A (en) * | 2013-01-17 | 2013-05-08 | 陕西北斗恒通信息科技有限公司 | Anti-interference radio-frequency receiving system |
| CN104237913A (en) * | 2014-09-03 | 2014-12-24 | 北京一朴科技有限公司 | GNSS software receiver architecture system |
| CN108072884A (en) * | 2017-09-18 | 2018-05-25 | 西安交通大学 | Global positioning system and Beidou satellite navigation system single channel dual-mode radio frequency receiver |
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