CN2849835Y

CN2849835Y - Apparatus for implementing synchronous communication data receiving and transmitting by universal microprocessor

Info

Publication number: CN2849835Y
Application number: CN 200520036472
Authority: CN
Inventors: 刘正熙; 黄戈; 李新胜
Original assignee: Sichuan University; Sichuan Chuanda Zhisheng Software Co Ltd
Current assignee: Sichuan University; Sichuan Chuanda Zhisheng Software Co Ltd
Priority date: 2005-12-13
Filing date: 2005-12-13
Publication date: 2006-12-20
Anticipated expiration: 2015-12-13

Abstract

The utility model relates to a device for implementing synchronous communication data receiving and transmitting by a universal microprocessor and belongs to a device of a simultaneous serial communication interface. Communication and control signals of synchronous communication are input to the microprocessor. Synchronous data input RxD is input via one bit of I/O of the microprocessor and synchronous data output TxD is output to a D end of a D trigger in a clock period of this time through one bit of I/O of the microprocessor and is synchronously output by a Q end and an internal clock of the microprocessor in the next clock period. An output clock of the microprocessor is sent to a CP end of the D trigger to serve as a CP clock source. All the input and output signals respectively implement conversion from an RS-232 level to a TTL level and from the TTL level to the RS-232 level through a level conversion circuit. The utility model uses a universal microprocessor to replace a synchronous serial communication chip, implementing the synchronous serial communication function and realizing receiving and transmitting non-standard synchronous serial communication data.

Description

Utilize general purpose microprocessor to realize the device of synchronous communication data transmit-receive

One, technical field

The utility model relates to the interface arrangement of compunication, particularly the synchronous serial communication interface arrangement that makes with microprocessor.

Two, background technology

On the one hand, along with the fast development of computer network communication technology, synchronous serial communication is used fewer and feweri, mainly concentrates on some professional domains, and this directly causes synchronous serial communication special purpose interface chip more and more to be hard to buy; And, even if also have synchronous serial communication special purpose interface card rack product, can not handle the data transmit-receive of non-standard (non-HDLC and IBM are synchronously two) synchronous serial communication rules.On the other hand, general purpose microprocessor (single-chip microcomputer, DSP etc.) function is more and more stronger, and price is more and more lower; Compare with synchronous serial communication special purpose interface chip, easier purchase, expense is more cheap.

Therefore, available general purpose microprocessor alternative synchronization serial communication special purpose interface chip is finished the function of synchronous serial communication, and can be realized the transmitting-receiving of non-standard synchronous serial communication rules data.

Three, utility model content

The purpose of this utility model provides a kind of device that utilizes general purpose microprocessor to realize the synchronous communication data transmit-receive, with alternative synchronization serial communication special purpose interface chip, thus the utility unit of realization synchronous communication data transmit-receive.

The technical scheme that realizes the purpose of this utility model is: a kind of device that utilizes general purpose microprocessor to realize the synchronous communication data transmit-receive, it is characterized in that, and mainly form by a microprocessor and a d type flip flop; Parallel I/O mouth that all contacts of synchronous communication, control signal input to microprocessor, synchrodata input RxD is through 1 I/O input of microprocessor, synchrodata output TxD exports the D end of d type flip flop to by 1 I/O of microprocessor in this clock period, and is exported synchronously with the timer clock of microprocessor internal by the Q end of d type flip flop in the next clock period; The output clock of microprocessor delivers to the CP end of d type flip flop, as CP clock source; Also have level shifting circuit: above-mentioned all input and output signals are finished from the RS-232 level to Transistor-Transistor Logic level and conversion from Transistor-Transistor Logic level to the RS-233 level through level shifting circuit respectively.

Also have external sync clock source and one 2 and select 1 circuit; The output clock in the output clock of microprocessor or external sync clock source by 2 select 1 circuit select a ground deliver to the CP end of d type flip flop, as CP clock source.

The principle of this technical scheme is: all contacts of synchronous communication, control signal are finished with the parallel I/O port of general purpose microprocessor; Interrupt mode is taked in the input of synchronous communication data, promptly according to the synchronous communication clock, takes the external interrupt mode, carries out reception, the processing of data according to the respective communication rules by software; The output of synchronous communication data both can have been taked regularly to interrupt the way of output, also can take the outside that synchronous clock source side formula is provided.

Need to prove, take regularly to interrupt the way of output or take the outside that synchronous clock source side formula is provided, all will guarantee to export synchronously the synchronous of clock TxC and synchronous output data TxD regardless of the output of synchronous communication data.For this reason, this device utilizes d type flip flop to preset the way of outputs data bits, has realized clock and data synchronization, sees the back for details and describes.

This novel beneficial effect is: available general purpose microprocessor alternative synchronization serial communication special purpose interface chip, and finish the function of synchronous serial communication, and can realize the transmitting-receiving of non-standard synchronous serial communication rules data.

Four, description of drawings

Fig. 1 utilizes general purpose microprocessor to realize the schematic diagram of the device of synchronous communication data transmit-receive;

Fig. 2 shown in Figure 12 selects the circuit diagram of an embodiment of 1 circuit;

Fig. 3 is a manipulated or operated apparatus shown in Figure 1.

Five, embodiment

Fig. 1 illustrates, and the utility model is mainly by a microprocessor, and mouth trigger and one 2 select 1 circuit to form; Parallel I/O mouth that logical synchronously firmly all are got in touch with, control signal inputs to microprocessor, synchrodata input RxD is through 1 I/O input of microprocessor, synchrodata output TxD exports the D end of d type flip flop to by 1 I/O of microprocessor in this clock period, and in the next clock period Q end and clock synchronization output by d type flip flop; Above-mentioned clock is the timer clock and the external sync clock source of microprocessor internal; The output clock in the output clock of microprocessor or external sync clock source selects 1 circuit to select the CP end that d type flip flop is delivered on a ground by 2, as CP clock source; Also have level shifting circuit: above-mentioned all input and output signals are all finished from the RS-232 level to Transistor-Transistor Logic level and conversion from Transistor-Transistor Logic level to the RS-233 level through level shifting circuit.

Can on the such scheme basis, cancel external sync clock source and 2 to select 1 circuit (being the CP end that the output clock of microprocessor is directly delivered to d type flip flop) and form another reduction procedure.

Relevant foregoing circuit is described as follows:

1. synchrodata input

With the external interrupt request signal of synchronous clock input RxC as microprocessor, synchrodata input RxD is as 1 I/O input of microprocessor.In interrupt service routine, read in this I/O input, promptly synchrodata is imported RxD, and carries out data processing by HDLC or the two synchronization criterion communication control procedures of IBM, and whether the CRC effect is determined when initialization.

2. synchrodata output

After synchrodata output TxD is ready to by microprocessor, 1 I/O by microprocessor exports to d type flip flop, clock that is produced by the microprocessor internal timer or the outside clock source that provides are as synchronous clock TxC together, clock and microprocessor last time are exported to the data of d type flip flop by 1 I/O, and promptly the Q end data of d type flip flop is exported synchronously.

Need to prove that 1 I/O of each microprocessor exports to the data of d type flip flop, all in this clock period, deliver to the D end of d type flip flop, deliver to the Q end and clock synchronization output of d type flip flop in the next clock period.

Describe with regard to timer clock and external clock reference below.

(1) timer clock

Timer clock by microprocessor according to the synchronous communication baud rate time corresponding cycle, produce regularly interruption by timer internal, and in the timer interrupt service routine, by 1 I/O output clock TxC of microprocessor, simultaneously this clock is given 2 and selected 1 circuit as one of CP clock source of d type flip flop.

Because timer clock is to produce the mode of regularly interrupting by timer internal to obtain, and 1 I/O output by microprocessor, so there is certain error in clock, but usually baud rate 19.2Kbps with interior less relatively.For the application scenario that needs degree of precision, can adopt the external clock reference mode.

(2) external clock reference

External clock reference refers to the clock source by active crystal oscillator and so on, according to the synchronous communication baud rate time corresponding cycle, provide synchronous output clock TxC by the control frequency dividing circuit, also this clock is given simultaneously 2 and selected 1 circuit as one of CP clock source of d type flip flop.

(3) 2 select 1 circuit

2 select 1 circuit implementation more, the simplyst can realize with 1 74LS00 exactly, as shown in Figure 2.

1 I/O output of microprocessor is as 2 control signals of selecting 1 circuit.When control signal is ' 1 ', select timer clock to export as synchronous communication clock TxC; When control signal is ' 0 ', select external clock reference to export as synchronous communication clock TxC.

3. control cue

The control cue is fairly simple, and all the position I/O with microprocessor realizes.

Embodiment:

AT90S8515 single-chip microcomputer with atmel corp is an example below, the embodiment of utilizing general purpose microprocessor to realize the synchronous communication data transmit-receive is described, as shown in Figure 3 (if adopt other single-chip microcomputer, DSP microprocessor, embodiment is identical), 2 select 1 circuit to be made up of four Sheffer stroke gate 74LS00-1,74LS00-2,74LS00-3,74LS00-4; The output signal of 74LS00-3 and 74LS00-2 is connected to the input end of 74LS00-4 respectively, the output signal of 74LS00-4 is delivered to the CP end of d type flip flop, the input end of 74LS00-2 inserts the signal of external clock reference, another input end connects the output terminal of 74LS00-1, the input end of input end of 74LS00-1 and 74LS00-3 inserts the output control signal of microprocessor, and another input end of 74LS00-3 inserts the microprocessor clock signal.

Described microprocessor adopts single chip computer AT 90S8515; Described level shifting circuit adopts the level conversion integrated circuit; This circuit structure is as follows: the MAX202-1 input end inserts synchrodata input RxD, output terminal connects the PBO pin of single-chip microcomputer, synchronous clock input RxC is as the input clock of single-chip microcomputer, input to the PD2 pin of single-chip microcomputer through MAX202-2, the PB3 pin of single-chip microcomputer connects the D end of d type flip flop, the PB2 pin connects another input end of 74LS00-3, the PB1 pin is connected to the input end of 74LS00-3 and 74LS00-1, the PB2 pin is externally exported synchronous clock output TxC signal, the signal of external clock reference inputs to the input end of 74LS00-2 through MAX202-3, and the output signal of d type flip flop Q end is externally exported through MAX202-5.

1, synchrodata input

RxC is through level conversion integrated circuit MAX202-2 in the synchronous clock input, it is Transistor-Transistor Logic level from the RS-232C level conversion that synchronous clock is imported RxC, interrupt request singal as AT90S8515 single-chip microcomputer external interrupt 0 is input to PD2 (INT0) pin, and interrupts in the rising edge request of synchronous clock input RxC.

Equally, RxD is through level conversion integrated circuit MAX202-1 in the synchrodata input, and it is Transistor-Transistor Logic level from the RS-232C level conversion that synchronous clock is imported RxD, as the position input of AT90S8515 single-chip microcomputer PB0 pin, and reads in this bit data in interrupt service routine.

2, synchrodata output

After synchrodata output TxD is ready to by the AT90S8515 single-chip microcomputer, PB3 pin by single-chip microcomputer, export to d type flip flop, clock that is produced by the microprocessor internal timer or the outside clock source that provides are as synchronous clock TxC together, clock and microprocessor last time are exported to the data of d type flip flop by the PB3 pin, the Q end data that is d type flip flop is exported to level conversion integrated circuit MAX202-5 synchronously, synchrodata is exported TxD be converted to the output of RS-232C level from Transistor-Transistor Logic level.

If adopt the timer clock mode, 16 bit timing device T1 of then available AT90S8515 single-chip microcomputer produce the timing in synchronous communication baud rate time corresponding cycle and interrupt, and in the timing interrupt service routine, PB2 pin output clock TxC by single-chip microcomputer, through level conversion integrated circuit MAX202-4, synchronous clock is exported TxC be the output of RS-232C level from the TIL level conversion.Simultaneously the output clock TxC of PB2 pin is given one of the 2 Sheffer stroke gate 74LS00-3 that select 1 circuit CP clock source as d type flip flop.

2 select the control signal of 1 circuit to control with the PB1 pin of AT90S8515 single-chip microcomputer.When PB1 is ' 1 ', through Sheffer stroke gate 74LS00-1 is anti-phase be ' 0 ' after as 1 input of Sheffer stroke gate 74LS00-2, mask external sync clock source, make the output of Sheffer stroke gate 74LS00-2 be always ' 1 '; Open Sheffer stroke gate 74LS00-3 simultaneously and select timer clock, and after Sheffer stroke gate 74LS00-4 is anti-phase once more, send d type flip flop, as CP clock source as synchronous communication clock TxC output.

When PB1 was ' 0 ', 1 input as Sheffer stroke gate 74LS00-3 masked the timer clock source, makes the output of Sheffer stroke gate 74LS00-3 be always ' 1 '; Simultaneously through Sheffer stroke gate 74LS00-1 is anti-phase be ' 1 ' after as 1 input of Sheffer stroke gate 74LS00-2, open Sheffer stroke gate 74LS00-2, make external sync clock source normally export to Sheffer stroke gate 74LS00-4 by Sheffer stroke gate 74LS00-2, and after Sheffer stroke gate 74LS00-4 is anti-phase once more, send d type flip flop, as CP clock source.

Claims

1, a kind of device that utilizes general purpose microprocessor to realize the synchronous communication data transmit-receive is characterized in that, mainly is made up of a microprocessor and a d type flip flop; Parallel I/O mouth that all contacts of synchronous communication, control signal input to microprocessor, synchrodata input RxD is through 1 I/O input of microprocessor, synchrodata output TxD exports the D end of d type flip flop to by 1 I/O of microprocessor in this clock period, and is exported synchronously with the timer clock of microprocessor internal by the Q end of d type flip flop in the next clock period; The output clock of microprocessor delivers to the CP end of d type flip flop, as CP clock source; Also have level shifting circuit: above-mentioned all input and output signals are finished from the RS-232 level to Transistor-Transistor Logic level and conversion from Transistor-Transistor Logic level to the RS-233 level through level shifting circuit respectively.

2, device according to claim 1 is characterized in that, also has external sync clock source and one 2 and selects 1 circuit; The output clock in the output clock of microprocessor or external sync clock source by 2 select 1 circuit select a ground deliver to the CP end of d type flip flop, as CP clock source.

3, device according to claim 2 is characterized in that, described 2 select 1 circuit to be made up of four Sheffer stroke gate 74LS00-1,74LS00-2,74LS00-3,74LS00-4; The output signal of 74LS00-3 and 74LS00-2 is connected to the input end of 74LS00-4 respectively, the output signal of 74LS00-4 is delivered to the CP end of d type flip flop, the input end of 74LS00-2 inserts the signal of external clock reference, another input end connects the output terminal of 74LS00-1, the input end of input end of 74LS00-1 and 74LS00-3 inserts the output control signal of microprocessor, and another input end of 74LS00-3 inserts the clock signal of microprocessor.

4, device according to claim 3 is characterized in that, described microprocessor adopts single chip computer AT 90S8515; Described level shifting circuit adopts level conversion integrated package MAX202; This circuit structure is as follows: the MAX202-1 input end inserts synchrodata input RxD, and output terminal connects the PBO pin of single-chip microcomputer, and synchronous clock input RxC inputs to the PD of single-chip microcomputer as the input clock of single-chip microcomputer through MAX202-2 ₂Pin, the PB of single-chip microcomputer ₃Pin meets D end, the PB of d type flip flop ₂Another input end, the PB1 pin that pin meets 74LS00-3 is connected to an input end, the PB of 74LS00-3 and 74LS00-1 ₂Pin is externally exported synchronous clock output TxC signal, and the signal of external clock reference inputs to the input end of 74LS00-2 through MAX202-3, and the output signal of d type flip flop Q end is externally exported through MAX202-5.