CN218482868U - Autonomous controllable POWERLINK communication device - Google Patents

Autonomous controllable POWERLINK communication device Download PDF

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CN218482868U
CN218482868U CN202222986371.4U CN202222986371U CN218482868U CN 218482868 U CN218482868 U CN 218482868U CN 202222986371 U CN202222986371 U CN 202222986371U CN 218482868 U CN218482868 U CN 218482868U
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powerlink
interface
processor
communication apparatus
memory
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张润时
王峥瀛
康晓非
王乾
王乐陶
肖棋元
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China Three Gorges Corp
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China Three Gorges Corp
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Abstract

The utility model provides an independently controllable POWERLINK communication device, include: the system comprises a 2K1000 processor, an integrated memory, a gigabit PHY and an external interface, wherein the integrated memory, the gigabit PHY and the external interface are in bidirectional interactive connection with the 2K1000 processor, two links are formed by the gigabit PHY and a network transformer, the gigabit PHY is in bidirectional interactive connection with the network transformer, and the network transformer is connected with the external interface. The utility model provides a pair of independently controllable POWERLINK communication device realizes POWERLINK's communication through the 2K1000 treater, utilizes 2K1000 treater dominant frequency high, the interface is abundant, and the characteristics that can dispose in a flexible way realize POWERLINK communication independently controllable to with integrated memory, giga PHY, external interface and network transformer modularization setting safe and reliable, the integrated level is high, applicable in various adverse circumstances.

Description

Autonomous controllable POWERLINK communication device
Technical Field
The utility model relates to a computer communication technology field, concretely relates to independently controllable POWERLINK communication device.
Background
The POWERLINK is a real-time communication protocol based on a common ethernet, does not need a special Application Specific Integrated Circuit (ASIC) chip, and supports multiple platforms such as Windows (which is an operating system developed by microsoft corporation based on a graphical user interface and mainly applied to devices such as computers and smart phones), linux (which is a Unix-like operating system free to use and propagate and is an operating system based on POSIX, multi-user, multi-task, multi-thread and multi-CPU), vxWorks (which is a real-time operating system proposed by american corporation), and the like, and is an open technical standard.
The current POWERLINK products are ARM frameworks (electronic product processor frameworks), and can not meet the requirement of autonomous controllability.
SUMMERY OF THE UTILITY MODEL
Therefore, the to-be-solved technical problem of the utility model lies in solving the problem that the ARM framework that POWERLINK product adopted can not satisfy independently controllable requirement among the prior art to an independently controllable POWERLINK communication device is provided.
The embodiment of the utility model provides an independently controllable POWERLINK communication device, include:
the system comprises a 2K1000 processor, an integrated memory, a gigabit PHY and an external interface, wherein the integrated memory, the gigabit PHY and the external interface are in bidirectional interactive connection with the 2K1000 processor, two links are formed by the gigabit PHY and a network transformer, the gigabit PHY is in bidirectional interactive connection with the network transformer, and the network transformer is connected with the external interface.
Optionally, the 2K1000 processor includes:
a GMAC controller connected to the gigabit PHY through an RGMII interface;
a central processor connected to the GMAC controller;
the DMA controller is respectively connected with the GMAC controller and the central processing unit;
and the buffer is connected with the central processing unit.
Optionally, the central processor, the GMAC controller, the gigabit PHY, the network transformer, and the external interface form a POWERLINK bus signal link.
Optionally, the integrated memory comprises: DDR3 memory, NAND FLASH memory, BOOT FLASH memory.
Optionally, the gigabit PHY employs YT8521S.
Optionally, the external interface includes: six serial ports, one USB interface, one SDIO interface, one GPIO interface, two CAN interfaces and two Ethernet interfaces; the two Ethernet interfaces are respectively connected with the network transformers in the two links.
Optionally, the two ethernet interfaces respectively adopt RJ45 interfaces.
Optionally, the method further comprises:
and the programmable read-only memory is connected with the 2K1000 processor through an integrated circuit bus interface.
Optionally, the method further comprises:
and the clock is connected with the 2K1000 processor through the integrated circuit bus interface. Optionally, the method further comprises:
a power supply connected with the 2K1000 processor.
The utility model discloses technical scheme has following advantage:
the embodiment of the utility model provides an independently controllable POWERLINK communication device realizes POWERLINK's communication through 2K1000 treater, utilizes 2K1000 treater dominant frequency high, the interface is abundant, and the characteristics that can dispose in a flexible way realize the independently controllable of POWERLINK communication to with integrated memory, giga PHY, external interface and network transformer modularization setting safe and reliable, the integrated level is high, applicable in various adverse circumstances.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a specific example of an autonomously controllable POWERLINK communication apparatus in an embodiment of the present invention;
fig. 2 is a block diagram of the internal bus of YT8521S in an embodiment of the present invention;
fig. 3 is a power link bus block diagram based on a 2K1000 processor according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a POWERLINK bus signal link according to an embodiment of the present invention.
In the figure, 1-2K1000 processors; 2-an integrated memory; 3-giga PHY; 4-external interface; 5-a network transformer; a 6-GMAC controller; 7-a central processing unit; 8-DMA controller; 9-a buffer; 10-programmable read only memory; 11-a clock; 12-power supply.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it is to be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper end", "inside", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that unless otherwise explicitly stated or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as a fixed connection, a detachable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in a specific case to those of ordinary skill in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The utility model provides an independently controllable POWERLINK communication device, as shown in FIG. 1, include:
the system comprises a 2K1000 processor 1, an integrated memory 2, a gigabit PHY3 and an external interface 4, wherein the integrated memory 2, the gigabit PHY3 and the external interface 4 are in bidirectional interactive connection with the 2K1000 processor 1, two links are formed by the gigabit PHY3 and a network transformer 5, the gigabit PHY3 is in bidirectional interactive connection with the network transformer 5, and the network transformer 5 is connected with the external interface 4.
Specifically, the 2K1000 processor 1 is mainly applied to a network, and adopts a 40nm (nanometer) technology, a master frequency of 1GHz (gigahertz), a 64-bit DDR3 (which is a computer memory specification) controller, and adopts a loongson autonomous instruction system architecture LoongArch (dragon architecture for short), a cpu (central processing unit) master frequency is 800mhz (megahertz) to 1GHz (gigahertz), chip peripheral interfaces include two paths of PCIE2.0 (bus interfaces), 1 path of SATA2.0 (ports for connecting a motherboard and a large number of storage devices), 4 paths of USB2.0 (universal serial bus), two paths of DVO (interfaces for outputting digital signals to external devices), 64-bit DDR2/3 (storage interfaces) and other various interfaces, and the chip is a home-made network chip, and has the characteristics of strong autonomous controllability, high reliability, convenient networking and the like, and adopts an autonomous instruction system architecture LoongArch, and has a master frequency as high as 1G and rich interfaces, and low power consumption, and is suitable for high-performance embedded system applications.
Specifically, the external interface 4 includes: six serial Ports (universal asynchronous receiver transmitter interface, short for UART), one USB interface, one SDIO (Secure Digital Input and Output) interface, one GPIO interface (General Purpose Input/Output port), two CAN (industrial field bus) interfaces and two Ethernet interfaces; the two Ethernet interfaces are respectively connected with the network transformer 5 in the two links; and the two paths of Ethernet interfaces respectively adopt RJ45 interfaces.
Specifically, as shown in fig. 2, the gigabit PHY3 (gigabit ethernet transceiver) uses YT8521S to output 1 line 10/100/1000Mbps (megabits per second) network interface through YT8521S, YT8521S is a domestic PHY chip, is a highly integrated ethernet transceiver, and conforms to 10BASE Te (referring to 10Mbit/S baseband ethernet specification using two pairs of twisted-pair cables for connection), 100BASE-TX (referring to 5 types of unshielded twisted-pair cables with 100 ohms for impedance, and 100 meters for maximum transmission distance), and 1000BASE-T IEEE802.3 standard (1000 BASE-T uses all 4 pairs of the 5 th type of twisted-pair cables and implements bidirectional transmission of signals in each pair of wires, and the IEEE802.3 protocol family specifies that four media can carry transmission of gigabit ethernet), provides physical layer functions required for transmission and reception, and packets on the ethernet are transmitted via CAT5E unshielded p cables (category five unshielded cables).
The YT8521S realizes high-speed data transmission by adopting an advanced DSP (digital signal processing) technology and an Analog Front End (AFE), transmission and reception are carried out through a UTP (unshielded twisted pair) cable, cross detection and automatic correction, polarity function correction, adaptive equalization, crosstalk cancellation, echo cancellation, timing recovery and error correction are realized in YT8521S, data transmission between MAC and PHY (Physical port layer) is carried out for communication of 1000BASE-T, 100BASE-TX and 10BASE-Te through a simplified gigabit media independent interface (RGMII) interface at 10Mbps, 100Mbps or 1000Mbps, wherein the RGMII interface consists of Physical coding sublayer transmission and Physical coding sublayer reception.
Further, the operating principle of YT8521S is: YT8521S needs to provide external crystal oscillator to generate system time, the external crystal oscillator generates a system clock through a phase-locked loop, and a timing recovery function module controls a phase selector to provide the clock for an ADC (Analog-to-digital converter); YT8521S provides a 3.3V (volt) power supply externally, a switch power supply circuit is integrated internally, the voltage is converted into 1.2V for internal use, and YT8521S needs an external 2.49K (kiloohm) bias resistor; YT8521S provides a SerDes interface for connecting an optical module, and simultaneously provides a management interface for accessing an internal register of YT8521S, LED lighting control is used for indicating network communication speed, LED0 is lighted, communication speed is 10Mbps, LED1 is lighted, communication speed is 100Mbps, LED2 is lighted, and communication speed is 1000Mbps.
Specifically, the integrated storage 2 is expanded by adopting a mode of on-board memory granules, and is integrally connected to each granule through a processor, each controller is connected with 4 pieces of 500M (mega) DDR3 memory granules, and the memory granules adopt purple SCB13H8G162BF memory granules; the integrated memory 2 includes: a DDR3 memory, a NAND FLASH (which is one of FLASH memories, a nonlinear macro-unit mode is adopted in the NAND FLASH, and a cheap and effective solution is provided for the realization of a solid-state high-capacity memory) memory and a BOOT FLASH (FLASH memory, which is used for storing the configuration of a router) memory; the NAND FLASH memory adopts FM29G04C, the BOOT FLASH memory adopts 8Mbit SPI FLASH, and the model is GD25Q80CSIG.
In an alternative embodiment, as shown in fig. 3, the 2K1000 processor 1 includes:
a GMAC controller 6 (gigabit ethernet controller), the GMAC controller 6 being connected to the gigabit PHY3 via an RGMII interface.
Specifically, the loongson 2K1000 is provided with two-way GMAC controllers 6, supports 10/100/1000Mbps adaptation, is compatible with IEE802.3, adopts RGMII interfaces in connection with the external gigabit PHY3, supports half-duplex/full-duplex adaptation, has a Timestamp function, supports automatic generation and Check of Cyclic Redundancy Check (CRC) Check codes, and supports preamble generation and deletion.
Furthermore, the GMAC controller 6 is usually composed of a MAC controller and a PHY, the CPU, the MAC, and the PHY are not integrated in the same chip, because the PHY includes a large number of analog devices, but the MAC is a typical digital circuit, considering the chip area and the analog/digital mixed architecture, the MAC is integrated into the CPU and the PHY is left outside the chip, the MAC controller mainly completes the packing of IP datagrams of a data link layer into network frames and sends data to the PHY, the PHY mainly completes speed negotiation, the conversion of digital signals into analog signals, and finally outputs the signals to the network cable.
A central processing unit 7, said central processing unit 7 (CPU) being connected to said GMAC controller 6.
Specifically, the central processing unit 7 outputs data of an integer type (INT) through a Processor interface.
A DMA (Direct Memory Access) controller 8, where the DMA controller 8 is connected to the GMAC controller 6 and the central processing unit 7, respectively.
Specifically, the DMA controller 8 controls the central processor 7 with interaction between the GMAC controllers 6.
A buffer 9 (Rrgister), said buffer 9 being connected to said central processor 7.
In an alternative embodiment, as shown in fig. 4, the central processor 7, the GMAC controller 6, the gigabit PHY3, the network transformer 5, and the external interface 4 form a POWERLINK bus signal link.
Specifically, the POWERLINK bus follows three layers of an Open System Interconnection Reference Model (OSI Model) seven-layer protocol: the power link layer adopts standard Ethernet and follows IEE802.3 fast Ethernet standard, and the power link layer on hardware only needs MCU and PHY chip with MAC, and then sends and receives signals through network transformer 5 and RJ45 interface without adopting special ASIC (Application Specific Integrated Circuit) chip.
Furthermore, the application layer software of the POWERLINK is open source, and only one MCU (Microcontroller Unit) with a Media Access Control (MAC) and a network chip are needed on hardware to realize the software, so that the development and implementation cost of the POWERLINK bus is very low; the POWERLINK cycle is controlled by the MN (undervoltage trip unit), where the synchronous data exchange between nodes occurs periodically and repeatedly at fixed time intervals, referred to as POWERLINK cycles; the data link layer of POWERLINK specifies two communication mechanisms: the user can flexibly configure according to the communication requirements of different devices, the application layer of the POWERLINK follows a CANopen standard, the CANopen standard is an open-source application layer protocol, and a uniform interface is provided for an application program, so that different devices and the application program have uniform access modes.
In an optional embodiment, the method further comprises:
the programmable read-only memory 10 is connected with the 2K1000 processor 1 through an integrated circuit bus interface.
Specifically, the programmable read only memory 10 is an EEPROM (electrically erasable programmable read only memory) of the type BL24C256A-NTRC, and is connected to the 2K1000 processor 1 through an integrated circuit bus interface (IIC interface) to store a network IP address.
In an optional embodiment, further comprising:
and the clock 11 is connected with the 2K1000 processor 1 through the integrated circuit bus interface.
Specifically, the clock 11 is connected to the 2K1000 processor 1 through the CBM1307 via the IIC interface, and the 2K1000 processor 1 is used to obtain accurate time.
In an optional embodiment, the method further comprises:
a power supply 12, the power supply 12 being connected to the 2K1000 processor 1.
Above-mentioned independently controllable POWERLINK communication device realizes POWERLINK's communication through the 2K1000 treater, utilizes 2K1000 treater dominant frequency height, interface abundant, and the characteristics that can dispose in a flexible way realize POWERLINK communication independently controllable to with integrated memory, giga PHY, external interface and network transformer modularization setting safe and reliable, the integrated level is high, applicable in various adverse circumstances.
It is to be understood that the above examples are illustrative only for the purpose of clarity of description and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. This need not be, nor should it be exhaustive of all embodiments. And obvious variations or modifications can be made without departing from the scope of the invention.

Claims (10)

1. An autonomously controllable POWERLINK communications device, comprising:
the system comprises a 2K1000 processor, an integrated memory, a gigabit PHY (physical layer) and an external interface, wherein the integrated memory, the gigabit PHY and the external interface are in bidirectional interactive connection with the 2K1000 processor, two paths of links are formed by the gigabit PHY and a network transformer, the gigabit PHY is in bidirectional interactive connection with the network transformer, and the network transformer is connected with the external interface.
2. The autonomously controllable POWERLINK communication apparatus of claim 1, wherein said 2K1000 processor comprises:
a GMAC controller connected to the gigabit PHY through an RGMII interface;
a central processor connected to the GMAC controller;
the DMA controller is respectively connected with the GMAC controller and the central processing unit;
and the buffer is connected with the central processing unit.
3. The autonomously controllable POWERLINK communication apparatus of claim 2, wherein said central processor, said GMAC controller, said gigabit PHY, said network transformer and said external interface comprise a POWERLINK bus signal link.
4. The autonomously controllable POWERLINK communication apparatus of claim 1, wherein said integrated memory comprises: DDR3 memory, NAND FLASH memory, BOOT FLASH memory.
5. The autonomously controllable POWERLINK communication apparatus of claim 1, wherein said gigabit PHY employs YT8521S.
6. The autonomously controllable POWERLINK communication apparatus of claim 1, wherein said external interface comprises: six serial ports, one USB interface, one SDIO interface, one GPIO interface, two CAN interfaces and two Ethernet interfaces; the two Ethernet interfaces are respectively connected with the network transformers in the two links.
7. The autonomously controllable POWERLINK communication apparatus according to claim 6, wherein each of the two ethernet interfaces is an RJ45 interface.
8. The autonomously controllable POWERLINK communication apparatus of claim 1, further comprising:
and the programmable read-only memory is connected with the 2K1000 processor through an integrated circuit bus interface.
9. The autonomously controllable POWERLINK communication apparatus of claim 8, further comprising:
and the clock is connected with the 2K1000 processor through the integrated circuit bus interface.
10. The autonomously controllable POWERLINK communication apparatus of claim 7, further comprising:
a power supply connected with the 2K1000 processor.
CN202222986371.4U 2022-11-07 2022-11-07 Autonomous controllable POWERLINK communication device Active CN218482868U (en)

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