CN2791739Y - High-speed digital-signal collection playback card - Google Patents
High-speed digital-signal collection playback card Download PDFInfo
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- CN2791739Y CN2791739Y CN 200520070518 CN200520070518U CN2791739Y CN 2791739 Y CN2791739 Y CN 2791739Y CN 200520070518 CN200520070518 CN 200520070518 CN 200520070518 U CN200520070518 U CN 200520070518U CN 2791739 Y CN2791739 Y CN 2791739Y
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Abstract
The utility model relates to a high-speed digital signal collection and playback card which is characterized in that a circuit is composed of a digital signal collecting module, a digital signal playback module, a digital signal level conversion module, a buffer management module and a system bus interface module, wherein the digital signal collecting module comprises a signal interface switch and serial / parallel conversion logic; the digital signal playback module comprises serial / parallel conversion logic, a signal interface switch and a clock control circuit; the digital signal level conversion module comprises collecting signal level conversion logic and playback signal level conversion logic; the buffer management module comprises a data buffer FIFO and a data cross switch; the system bus interface module comprises a PCI /PCI bus controller and PCI/PCI bus control logic. The utility model can realize the high-speed collection and the playback of various digital signal types, can support four kinds of signal levels, such as a TTL signal level, an LvTTL signal level, a CMOS signal level and an ECL signal level, and can support 0-300Mbps digital signal collection and 32-180Mbps signal playback. The bus transfer rate is bigger than 100MB/s.
Description
Technical field
The utility model belongs to data collecting field, especially towards national defence, the contour terminal number word of Aero-Space signal communication field, relates to high-frequency digital signal is gathered and treatment technology in real time.
Background technology
The digital signal acquiring technology is the technology of gathering digital signal level with certain clock frequency, is widely used in numerous areas such as national defence, Aero-Space, remote sensing, scientific experimentation, communication and Industry Control.Existing digital signal acquiring system exists that acquisition rate is low, the supporting signal kind is single, real-time is poor, can not support simultaneously to gather and shortcomings such as playback function, is used for industrial control field more.Along with the develop rapidly of national defence, aeronautical and space technology, digital signal acquiring is had higher requirement promptly higher acquisition rate, the support of more signal types and stronger real-time performance.Above-mentioned requirements is that existing digital signal acquiring system is unappeasable.
Summary of the invention
The purpose of this utility model is in order to overcome the weak point of prior art, propose a kind of high-speed digital signal and gather solution, design and be adapted to the hardware collection playback card that various high-end digital signal acquirings are used, realize the real-time collection and the playback of multiple high-speed digital signal, support is up to the digital signal acquiring speed of 300Mbps, and making high-end digital signal acquiring use becomes possibility.
For achieving the above object, the technical solution adopted in the utility model is: a kind of high-speed digital signal is gathered playback card, and its circuit is made up of digital signal acquiring module, digital playback signal module, digital signal level modular converter, cache management module and system bus interface module five parts;
Described digital signal acquiring module comprises signaling interface switch and serial/parallel conversion logic, the signaling interface switch receives one road synchronizing clock signals and a circuit-switched data signal, by switch is set discerns and select, and utilize the rising edge of synchronizing clock signals or negative edge to carry out signals collecting to TTL, LvTTL, CMOS and four kinds of varying level type signals of ECL; To the serial digital signal of gathering, serial/parallel conversion logic adopts two MC100E445 chips to realize the conversion of serial data to parallel data;
Described digital playback signal module comprises parallel/serial conversion logic, signaling interface switch and clock control circuit, parallel/serial conversion logic adopts two MC100E446 chips, to convert serial data to from the parallel data that the computer system playback is read, by signaling interface switch playback one road synchronizing clock signals and a circuit-switched data signal, clock control circuit produces the data readback synchronous clock, the signaling interface switch is provided with switch with the signal type of user's appointment, and playback of data is carried out playback with the level type of user's appointment;
Described digital signal level modular converter comprises acquired signal level conversion logic and playback signal level conversion logic, and acquired signal level conversion logic converts the signal level of gathering to the ECL level signal and blocks interior transmission; The signal level signal that the ECL level signal of playback converted appointment in playback signal level conversion logic will be blocked is exported;
Described cache management module comprises metadata cache FIFO and data crossbar, data crossbar adopt EPM7064 realize to the control of data buffering and with the interface of external circuit, realize data buffering FIFO and outside high-speed data path;
Described system bus interface module comprises PCI/cPCI bus controller and PCI/cPCI bus control logic, the PCI/cPCI bus controller is realized the interface with the PCI/cPCI bus, the PCI/cPCI bus control logic realizes the control interface to the PCI/cPCI bus controller, the data of described digital signal acquiring module collection are sent to computer system or obtain data from computer system, send by described digital playback signal module.
Related content in the technique scheme is explained as follows:
1, in the such scheme, in the described digital playback signal module clock control circuit with the constant-temperature crystal oscillator of 16MHz as reference clock, and adopt the SY89429V frequency synthesizer as programmable clock, to be implemented in the signal playback of optional frequency in 32～180MHz scope.
The utility model principle of work is: described digital signal acquiring module receives one tunnel high-speed figure level signal and one tunnel clock signal, implement collection according to the hopping edge of clock signal to digital signal, after the serial/parallel conversion of serial digital signal process of gathering, send to the back-end computer system by said bus interface module; Described digital playback signal module is obtained playback of data by said bus interface module, through parallel/serial conversion, with specific clock frequency data serial is sent; Described digital signal level modular converter is realized the conversion of multiple signal level, and at different signal levels, the unification of digital signal level modular converter converts the speed height to, the little ECL level signal of distortion is blocked interior transmission; Described cache management module realizes the buffer memory of high speed acquisition data, keeps continuity to guarantee high-speed data-flow in processing and transmission course; Described system bus interface module realizes the data exchanging function with computer system, realize exchanges data by PCI/cPCI bus and computer system, the data of said digital signal acquiring module collection are sent to computer system or obtain data from computer system, send by described digital playback signal module.
The utility model can be realized the high speed acquisition and the playback of multiple digital signal type, supports TTL, LvTTL, four kinds of signal levels of CMOS, ECL, supports the digital signal acquiring of 0～300Mbps and the signal playback of 32～180Mbps.Its key technical indexes is as follows:
1, supporting signal type: TTL, LvTTL, CMOS, ECL
2, acquisition rate: 0～300Mbps
3, playback rate: 32～180Mbps
4, bus transfer rate:＞100MB/s
The utility model can be applicable to following field:
1, radar and sonar digital signal receive
2, satellite digital communication
3, remotely-sensed data receives
4, radio communication
5, scientific experimentation
6, Industry Control
Description of drawings
Fig. 1 the utility model high-speed digital signal is gathered the hardware structure diagram of playback card.
Embodiment
Below in conjunction with drawings and Examples the utility model is further described:
Embodiment: a kind of high-speed digital signal is gathered playback card, its hardware is made up of digital signal acquiring module I, digital playback signal module ii, digital signal level modular converter III, cache management module I V, system bus interface module V five parts, as shown in Figure 1.
The composition and the function declaration of each module are as follows:
I, digital signal acquiring module comprise signaling interface switch and serial/parallel conversion logic, wherein:
1) signaling interface switch
The signaling interface switch is realized identification and the selection to the varying level type signal, according to different incoming signal level types switch is set, and carries out different processing respectively at different signal levels.The collection of hardware supported TTL, LvTTL, CMOS and four kinds of level signals of ECL of the utility model design, and traditional data collecting card is generally only supported one to two kind of signal level.In order to realize the support to multiple level signal, system introduces the signaling interface switch concept, supports multiple signal level by the signaling interface switch, comprises positive level signal (as TTL, LvTTL, CMOS) and negative level signal (ECL).
The signaling interface switch receives one road synchronizing clock signals and a circuit-switched data signal, according to the collection of synchronizing clock signals realization to data, hardware is gathered data-signal according to the hopping edge of synchronous clock, because the utility model is primarily aimed at the collection of high-frequency digital signal, high-frequency signal is easy to produce distortion and skew in transmission course, for example the length of signal transmission cable all might exert an influence to signal, therefore, rising edge or negative edge that hardware design becomes can be arranged on flexibly synchronizing clock signals carry out signals collecting, have solved skew and distortion that signal causes in transmission course to a great extent.
2) serial/parallel conversion logic
Serial/parallel conversion logic is realized the conversion of serial data to parallel data, the signal of system acquisition is a serial data signal, must convert the serial data stream of gathering to parallel data by serial/parallel conversion logic, make things convenient for data storage to handle to computer system or other signal analysis softwares.Simultaneously, by serial/parallel conversion logic, also can reduce the frequency of signal, for example, after the serial digital signal of 300MHz is converted to 8 bit parallel digital signals, frequency is reduced to 37.5MHz, makes that distortion was littler when signal transmitted in card, and this also is the reason of at the very start carrying out serial/parallel conversion of the utility model in data acquisition.
Serial/parallel conversion realizes by two MC100E445 chips, MC100E445 is 4 serial/parallel conversion chips of a kind of high speed, we use two MC100E445 chips to realize 8 serial/parallel conversion, serial/parallel conversion logic input serial digital signal and synchronizing clock signals are exported 8 channel parallel data signals and 8 frequency-dividing clock synchronizing signals.
II, digital playback signal module comprise parallel/serial conversion logic, signaling interface switch and clock control circuit, wherein:
1) parallel/serial conversion logic
Parallel/serial conversion logic is realized the conversion of parallel data to serial data, and the signal that system carries out playback is the parallel data from computer system reads, must go out with the form playback of serial data with parallel data through parallel/serial conversion.
Parallel/serial transfer process is actually the inverse process of above-mentioned serial/parallel transfer process, realize by two MC100E446 chips, MC100E446 is 4 parallel/serial conversion chips of a kind of high speed, for realizing 8 parallel/serial conversions, we adopt two MC100E446 chips to realize, parallel/serial conversion logic is imported 8 road parallel digital signals and synchronizing clock signals, exports 1 road serial data signal and 8 frequency doubling clock synchronizing signals.
2) signaling interface switch
The signaling interface switch realizes that the different according to this signal level type of logarithm carries out playback, according to the signal type of user's appointment switch is set, and playback of data is carried out playback with the level type (TTL, LvTTL, ECL, CMOS) of user's appointment.
Signaling interface switch playback one road synchronizing clock signals and a circuit-switched data signal carry out the playback of data-signal in the hopping edge of clock, and hardware can carry out signal playback along (rising edge clock or negative edge) according to the clock of user's appointment.
3) clock control circuit
Clock control circuit produces the data readback synchronous clock, the data readback module realizes the playback operation of data according to the playback synchronous clock, general only support of traditional digital playback signal card carried out playback with one or several fixing frequencies to signal, in order to improve the defective of conventional digital signal playback card, we have introduced the hardware design of programmable clock, to be implemented in the signal playback of optional frequency in 32～180MHz scope.The user can set the clock frequency of signalization playback by software flexible ground to playback hardware.
In order to produce the high precision synchronous clock, the constant-temperature crystal oscillator of selecting 16MHz in the circuit for use is as reference clock, the SY89429V frequency synthesizer of selecting SYNERGY simultaneously for use is as programmable clock, SY89429V has 25～400MHz clock fan-out capability, the shake peak value of output clock only is 25ps, SY89429 provides data and control input port in addition, and is very convenient to its control.The output frequency fout of this circuit and the relation of incoming frequency fin are as follows:
fout＝(fin/8)(M/N)
M and N are two numerical value that write SY89429 by interface in the formula, according to different M and N value are set, can obtain the clock output of 25～400MHz.
III, digital signal level modular converter comprise that TTL changes the ECL logic and ECL changes the TTL logic, wherein:
1) TTL changes the ECL logic:
The high-frequency signal of the multiple level of present technique novel process, for unified design, the unified signal quality that uses of signal transmission is good in card, the ECL signal level that distortion is little.The ECL signal is the negative level signal, and TTL, LvTTL, cmos signal are the positive level signal, at the collection of this several types signal, at first it is converted thereof into the ECL signal by the level conversion logic and handle, not only reduced the complexity of hardware design but also improved the quality of signal transmission.
TTL changes the ECL logic, and we select for use the SY100ELT24 of Micrel company to realize.SY100ELT24 is that a kind of signal of Transistor-Transistor Logic level efficiently divides the converter of ECL level signal to fork, the input Transistor-Transistor Logic level, and through transforming, output fork divides ECL signal.It is good that SY100ELT24 has signal level, the characteristics of conversion efficiency height (500ps time-delay).
2) ECL changes the TTL logic:
When carrying out signal playback,, in the time will carrying out playback, the ECL conversion of signals must be become the signal level signal of appointment to export with other signal level forms because unified ECL level signal is adopted in the signal transmission in the plate.
We select for use the SY100ELT25 of Micrel company to realize the conversion of ECL signal to the TTL signal, SY100ELT25 is that a kind of fork efficiently divides the converter of ECL level signal to the Transistor-Transistor Logic level signal, the input fork divides the ECL signal, output Transistor-Transistor Logic level signal, and SY100ELT25 has the transmission delay of 2.6ns.
IV, cache management module comprise metadata cache FIFO and data crossbar, wherein:
1) metadata cache FIFO
The processing of the novel realization high-speed digital signal of present technique, requirement can require to have large-capacity data buffering FIFO that data are carried out buffered, to avoid owing to the temporary performance bottleneck of system causes overflowing of image data to the real-time processing of high-speed data.
We select for use the IDT72V3694 of IDT company to go up data buffering as card, IDT72V3694 is the fifo chip of a two-way 32K * 36 * 2, fast data buffer up to 256KB can be provided, access time 6.5ns, be the FIFO device of a high speed, low-power consumption (3.3V), inner two independently clock the bidirectional operation of FIFO is provided.The buffer memory of data buffering FIFO and pci bus controller FIFO and application software constitutes a multistage data Caching Mechanism, has realized the real-time processing of high-speed data, has avoided data to overflow.
2) data crossbar
Data crossbar realize to the control of data buffering and with the interface of external circuit, we select for use the FPGA device EPM7064 of Altera to realize.To the read-write sequence of FIFO, marking signal carries out control and management, realizes data buffering FIFO and outside high-speed data path.
V, system bus interface module comprise pci bus controller and pci bus steering logic, wherein:
1) pci bus controller
Pci bus controller is realized the interface with pci bus, and 32 and 64 s' PCI protocol controller is arranged at present.In the high-speed data acquisition playback card of the utility model design, the data throughput of 300Mbps is provided, from satisfying the prerequisite of system requirements and taking into account system cost, we have selected the PCI protocol controller of 32 33MHz for use, and the peak transmission speed of 1Gbps is provided.
2) pci bus steering logic
The pci bus steering logic realizes the control interface to pci bus controller, we adopt the programmable logic device (PLD) EPM7256 of altera corp that the Add-On interface of pci bus controller is controlled, realized upward register access of card, high speed DMA data path, control function such as interrupt management.
The foregoing description only is explanation technical conceive of the present utility model and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present utility model and enforcement according to this, can not limit protection domain of the present utility model with this.All equivalences of being done according to the utility model spirit change or modify, and all should be encompassed within the protection domain of the present utility model.
Claims (2)
1, a kind of high-speed digital signal is gathered playback card, and it is characterized in that: circuit is made up of digital signal acquiring module, digital playback signal module, digital signal level modular converter, cache management module and system bus interface module five parts;
Described digital signal acquiring module comprises signaling interface switch and serial/parallel conversion logic, the signaling interface switch receives one road synchronizing clock signals and a circuit-switched data signal, by switch is set discerns and select, and utilize the rising edge of synchronizing clock signals or negative edge to carry out signals collecting to TTL, LvTTL, CMOS and four kinds of varying level type signals of ECL; To the serial digital signal of gathering, serial/parallel conversion logic adopts two MC100E445 chips to realize the conversion of serial data to parallel data;
Described digital playback signal module comprises parallel/serial conversion logic, signaling interface switch and clock control circuit, parallel/serial conversion logic adopts two MC100E446 chips, to convert serial data to from the parallel data that the computer system playback is read, by signaling interface switch playback one road synchronizing clock signals and a circuit-switched data signal, clock control circuit produces the data readback synchronous clock, the signaling interface switch is provided with switch with the signal type of user's appointment, and playback of data is carried out playback with the level type of user's appointment;
Described digital signal level modular converter comprises acquired signal level conversion logic and playback signal level conversion logic, and acquired signal level conversion logic converts the signal level of gathering to the ECL level signal and blocks interior transmission; The signal level signal that the ECL level signal of playback converted appointment in playback signal level conversion logic will be blocked is exported;
Described cache management module comprises metadata cache FIFO and data crossbar, data crossbar adopt EPM7064 realize to the control of data buffering and with the interface of external circuit, realize data buffering FIFO and outside high-speed data path;
Described system bus interface module comprises PCI/cPCI bus controller and PCI/cPCI bus control logic, the PCI/cPCI bus controller is realized the interface with the PCI/cPCI bus, the PCI/cPCI bus control logic realizes the control interface to the PCI/cPCI bus controller, the data of described digital signal acquiring module collection are sent to computer system or obtain data from computer system, send by described digital playback signal module.
2, high-speed digital signal according to claim 1 is gathered playback card, it is characterized in that: in the described digital playback signal module clock control circuit with the constant-temperature crystal oscillator of 16MHz as reference clock, and adopt the SY89429V frequency synthesizer as programmable clock, to be implemented in the signal playback of optional frequency in 32～180MHz scope.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520070518 CN2791739Y (en) | 2005-04-04 | 2005-04-04 | High-speed digital-signal collection playback card |
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| CN 200520070518 CN2791739Y (en) | 2005-04-04 | 2005-04-04 | High-speed digital-signal collection playback card |
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| CN2791739Y true CN2791739Y (en) | 2006-06-28 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944002A (en) * | 2010-08-26 | 2011-01-12 | 北京航空航天大学 | Gain adjustable multifunctional data acquisition card |
| CN104519280A (en) * | 2014-11-26 | 2015-04-15 | 成都盛军电子设备有限公司 | Image capture board card with playback function |
| CN104754303A (en) * | 2015-03-24 | 2015-07-01 | 中国科学院长春光学精密机械与物理研究所 | Multi-channel data transmission system with high bandwidth and high interference resistance and transmission method |
| CN112989748A (en) * | 2021-02-24 | 2021-06-18 | 中科芯集成电路有限公司 | Integrated circuit capable of reducing wiring quantity |
-
2005
- 2005-04-04 CN CN 200520070518 patent/CN2791739Y/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944002A (en) * | 2010-08-26 | 2011-01-12 | 北京航空航天大学 | Gain adjustable multifunctional data acquisition card |
| CN101944002B (en) * | 2010-08-26 | 2012-05-30 | 北京航空航天大学 | Gain adjustable multifunctional data acquisition card |
| CN104519280A (en) * | 2014-11-26 | 2015-04-15 | 成都盛军电子设备有限公司 | Image capture board card with playback function |
| CN104754303A (en) * | 2015-03-24 | 2015-07-01 | 中国科学院长春光学精密机械与物理研究所 | Multi-channel data transmission system with high bandwidth and high interference resistance and transmission method |
| CN104754303B (en) * | 2015-03-24 | 2017-10-03 | 中国科学院长春光学精密机械与物理研究所 | Multi-channel Transmission System and transmission method with high bandwidth, strong anti-interference |
| CN112989748A (en) * | 2021-02-24 | 2021-06-18 | 中科芯集成电路有限公司 | Integrated circuit capable of reducing wiring quantity |
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Granted publication date: 20060628 Termination date: 20110404 |