CN2785038Y - Real time debugger of digital signal processor - Google Patents
Real time debugger of digital signal processor Download PDFInfo
- Publication number
- CN2785038Y CN2785038Y CN 200520028139 CN200520028139U CN2785038Y CN 2785038 Y CN2785038 Y CN 2785038Y CN 200520028139 CN200520028139 CN 200520028139 CN 200520028139 U CN200520028139 U CN 200520028139U CN 2785038 Y CN2785038 Y CN 2785038Y
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- bus interface
- conversion circuit
- debugger
- lvds
- interface conversion
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Abstract
The utility model belongs to the technical field of the digital signal processing which is a real time debugger of the digital signal processor, and the real time debugger is composed of a target panel, a debugger panel and a computer. The target panel comprises an LVTTL bus interface, a data bus interface transform circuit, an address, a control bus interface transform circuit and an LVDS bus interface. The real time debugger panel comprises the LVDS bus interface, the data bus interface transform circuit, the address, the control bus interface transform circuit, the programmable logic device 4, an SCM and a serial converter. The target panel and the debugger panel are connected together in two-way through the LVDS bus interface, and the debugger panel and the computer are connected together in two-way through the standard serial converting circuit. The utility model solves the problems of the prior art that it can not monitor the real-time variation of variable, and it is not convenient to combined adjust on site of application, so the debugger is favorable for the real-time debugging of the complex algorithmic, and the development time is reduced, and the transmission distance can exceed 20 m. The debugger is suitable for the on-line debugging of putting the target panel in complex environment.
Description
Technical field
The utility model belongs to digital signal processing technique field, relates to the digital signal processor analogue system, specifically a kind of real time debugger of digital signal processor.
Background technology
In existing digital signal processing, the structured flowchart of real time debugging device as shown in Figure 1: comprise the Target Board 1, JTEG mouth emulator 2, the computing machine 3 that contain digital signal processor.
Since the beginning of the eighties, the single-chip digital signal processor chip was born, real time digital signal processor technology had obtained using widely in national economy and aspect of social life, and becomes the determinative that electronic product updates gradually.But in the exploitation debug process of DSP chip, whether the function of developing instrument is complete, and whether use convenient, will influence the construction cycle and the time to market (TTM) of digital signal processor system to a great extent.The developing instrument of DSP chip promptly adopts the method for main frame-emulator-Target Board to constitute development environment usually by means of computing machine.Main frame is selected computing machine for use, Target Board is the hardware system that DSP chip is housed, emulator one end is connected with Target Board by jtag interface, the emulator other end link to each other with computer by serial, parallel port or USB mouth (deciding) on concrete emulator, by jtag interface, emulator can be observed all storeies and the register in the digital signal processor.But will fall-back when finding to want monitored variable or breaking in actual use based on the emulator of jtag interface, therefore for the video image of stream data is handled, situation of change that can not the real time monitoring variable, emulator and Target Board distance is short about 10 centimetres in addition, and about 1 meter of the distance of emulator and computing machine, this makes in site of deployment very inconvenient sometimes.
Summary of the invention
For solve in the prior art based on the emulator of jtag interface for the video image of stream data handle can not the real time monitoring variable situation of change, it is short in the very inconvenient sometimes problem of site of deployment to reach emulator and Target Board distance, but the utility model provides a kind of real time debugging device that is used for digital signal processor of real time monitoring variable change situation.The distance of this device and Target Board can reach more than 20 meters.
The utility model is by Target Board 1, debugger plate 4, and computing machine 3 three parts constitute, and debugger plate 4 wherein replaces emulator 2 of the prior art.
Structure of the present utility model as shown in Figure 2.
The utility model Target Board 1 comprises the LVTTL bus interface 1-1 of digital signal processor, data bus is interface conversion circuit 1-2 during as output bus, data bus is interface conversion circuit 1-3 during as input bus, address and control bus interface conversion circuit 1-4, LVDS bus interface 1-5.LVTTL bus interface 1-1 passes through interface conversion circuit 1-2,1-3, and 1-4 is connected with LVDS bus interface 1-5.In the utility model Target Board 1, the transmission of data bus interface change-over circuit 1-2 signal is unidirectional, from LVTTL bus interface 1-1 to LVDS bus interface 1-5, the transmission of data bus interface change-over circuit 1-3 signal is unidirectional, to LVTTL bus interface 1-1, constituted BDB Bi-directional Data Bus from LVDS bus interface 1-5 by data bus interface change-over circuit 1-2 and data bus interface change-over circuit 1-3.The transmission of the signal of address, control bus interface conversion circuit 1-4 is unidirectional, from LVTTL bus interface 1-1 to LVDS bus interface 1-5.
Interface conversion circuit 4-2 when real time debugger plate 4 comprises LVDS bus interface 4-1, data bus as output bus, data bus is interface conversion circuit 4-3 during as input bus, address and control bus interface conversion circuit 4-4, programmable logic device (PLD) 4-5, single-chip microcomputer 4-6, serial converter spare 4-7.In the utility model debugger plate 4, the transmission of data bus interface change-over circuit 4-2 signal is unidirectional, from LVDS bus interface 4-1 to programmable logic device (PLD) 4-5, the transmission of data bus interface change-over circuit 4-3 signal is unidirectional, to LVDS bus interface 4-1, constituted BDB Bi-directional Data Bus from programmable logic device (PLD) 4-5 by data bus interface change-over circuit 4-2 and data bus interface change-over circuit 4-3.The transmission of the signal of address, control bus interface conversion circuit 4-4 is unidirectional, from LVDS bus interface 4-1 to programmable logic device (PLD) 4-5.Is two-way by programmable logic device (PLD) 4-5 to the transmission of single-chip microcomputer 4-6 signal, also is two-way by single-chip microcomputer 4-6 to the transmission of serial converter spare 4-7 signal.
Target Board 1 and debugger plate 4 usefulness 40 core cables are LVDS bus interface 1-5 and two-way connection of LVDS bus interface 4-1, and debugger plate 4 and computing machine 3 are by two-way connection of standard serial port change-over circuit 4-7.
Because the widespread use of extensive field programmable gate array, therefore using digital signal processor usually all is that its data bus, address bus and control signal are linked in the field programmable gate array.But utilize field programmable gate array I/O pin flexible configuration to become the characteristic of input, output or transmitted in both directions, data bus is configured to transmitted in both directions, address and control bus are configured to the way of output.Link on the LVTTL bus interface of digital signal processor.
The LVTTL bus interface 1-1 of digital signal processor of the present utility model converts data, address and the control signal of LVTTL level to the LVDS level standard through interface conversion circuit, deliver to the long line transmission of LVDS bus interface, increase the distance of Target Board and debugger plate; In the real time debugger plate, to change into the LVTTL level again through interface conversion circuit from data, address and the control signal of LVDS on the Target Board, offering programmable logic device (PLD) latchs, data after single-chip microcomputer reads programmable logic device (PLD) and latchs change into serial signal with it and deliver to serial ports level conversion device from microcontroller serial port and change into standard 232 forms and send to the computing machine.Simultaneously single-chip microcomputer reads serial ports of computers and sends here to be sent in the programmable logic device (PLD) behind the routine data of digital signal processor and latch, data after latching are delivered in the digital signal processor through twice level shifting circuit again, the Auto Loader that digital signal processor powers on runs through the back and carries out this code for from computing machine reader code.In the utility model, address, control signal are unidirectional, and to the debugger plate, and data-signal is two-way, and the variable that monitor is delivered to the debugger plate from Target Board, and routine data is read the Target Board from the debugger plate from Target Board.
Each parts annexation: on Target Board, the LVTTL bus interface 1-1 of digital signal processor, this bus interface comprises data bus, address bus and control signal, and data bus links to each other with interface conversion circuit 1-2 during as output bus, the data bus of bus interface 1-1 links to each other with interface conversion circuit 1-3 during as input bus, the address bus of bus interface 1-1 output links to each other with interface conversion circuit 1-4 with control signal.With interface conversion circuit 1-2,1-3, the 1-4LVDS end links to each other with LVDS bus interface 1-5.
On the real time debugger plate, the data bus of LVDS bus interface 4-1 links to each other with interface conversion circuit 4-2 during as output bus, the data bus of LVDS bus interface 4-1 links to each other with interface conversion circuit 4-3 during as input bus, the address bus of LVDS bus interface 4-1 and control signal link to each other with interface conversion circuit 4-4, with interface conversion circuit 4-2,4-3, the LVTTL end of 4-4 links to each other with programmable logic device (PLD) 4-5, data after programmable logic device (PLD) 4-5 latchs link to each other with single-chip microcomputer 4-6, link to each other with computing machine 3 behind the serial data process serial ports level transferring chip 4-7 of single-chip microcomputer 4-6.
Owing to the data that will observe in the digital signal processor are directly delivered in the computing machine in the utility model, realized the real-time communication of digital signal processor and computing machine, can the Real Time Observation local variable and the situation of change of any institute data of interest.Solve in the prior art can not monitored variable real-time change and in the problem of site of deployment uniting and adjustment inconvenience, the utility model helps the real-time debug of complicated algorithm, shorten the development time, simultaneously owing to adopt differential signal transmission between debugger plate and the Target Board, transmission range can surpass 20 meters, is suitable for Target Board and is placed on and carries out on-line debugging in the complex operating environment.
Description of drawings
Fig. 1 is the real time debugger structured flowchart that prior art is used for digital signal processor.1 is that the Target Board, 2 that contains digital signal processor is that JTEG mouth emulator, 3 is computing machine among the figure.
Fig. 2 is the utility model structural drawing, also is the specification digest accompanying drawing.1-1 is the LVTTL bus interface among the figure, and 1-2 is an interface conversion circuit, and 1-3 is an interface conversion circuit, 1-4 is an interface conversion circuit, 1-5 is the LVDS bus interface, and 4-1 is the LVDS bus interface on the real time debugger plate, and 4-2 is an interface conversion circuit, 4-3 is an interface conversion circuit, 4-4 is an interface conversion circuit, and 4-5 is a programmable logic device (PLD), and 4-6 is a single-chip microcomputer, 4-7 is a serial converter spare, and 3 is computing machine.
Fig. 3 is the circuit structure diagram of an embodiment of the utility model on Target Board.
Fig. 4 is the circuit structure diagram of an embodiment of the utility model on the debugger plate.
Embodiment
Below in conjunction with drawings and Examples the utility model is further specified.
LVTTL is low-voltag transistor-transistor logic, and LVDS is a low-voltage differential signal.
Embodiment of the present utility model realizes by structured flowchart as shown in Figure 2, comprises the LVTTL bus interface 1-1 of digital signal processor on the Target Board, data bus is interface conversion circuit 1-2 during as output bus, data bus is interface conversion circuit 1-3 during as input bus, address and control bus interface conversion circuit 1-4, LVDS bus interface 1-5, LVDS bus interface 4-1 on the real time debugger plate, data bus is interface conversion circuit 4-2 during as output bus, data bus is interface conversion circuit 4-3 during as input bus, address and control bus interface conversion circuit 4-4, programmable logic device (PLD) 4-5, single-chip microcomputer 4-6, serial converter spare 4-7, computing machine 3.Wherein, 1-1,1-2,1-3,1-4,1-5 are on Target Board, and 4-1,4-2,4-3,4-4,4-5,4-6,4-7 are on the real time debugger plate.
Fig. 3, Fig. 4 are specific embodiments of the present utility model, and the LVTTL bus interface 1-1 of digital signal processor is that the signal of digital signal processor is through outputing to data, address and the control signal on the 20 core sockets behind the field programmable gate array; Data bus during as output bus interface conversion circuit 1-2 adopt 2 DS90LV047, data bus during as input bus interface conversion circuit 1-3 adopt two DS90LV048; Address and control bus interface conversion circuit 1-4 adopt 2 DS90LV047; LVDS bus interface 1-5 adopts 40 core sockets on the Target Board, LVDS bus interface 4-1 adopts 40 core sockets on the real time debugger plate, data bus when interface conversion circuit 4-2 adopts 2 DS90LV048, data bus as input bus during as output bus interface conversion circuit 4-3 to adopt 2 DS90LV047, address and control bus interface conversion circuit 4-4 to adopt 2 DS90LV048, programmable logic device (PLD) 4-5 to adopt EPM7128E, single-chip microcomputer 4-6 to adopt P8051, serial converter coroner 4-7 to adopt MAX232, computing machines 3 are arbitrary computing machines that have serial ports.Target Board is connected by 40 core cables with the real time debugger plate, owing to adopt the LVDS transmission, transmission range can be above 20 meters.
The annexation of embodiment is as follows: the LVTTL form shfft of data bus is shown D[7:0], the LVDS form shfft of data bus is shown D
+[7:0], D
-[7:0], the LVTTL form shfft of address bus is shown A[4:0], the LVDS form shfft of address bus is shown A
+[4:0], A
-[4:0], the LVTTL form shfft of control signal is shown RD, WR, CS, the LVDS form shfft of control signal is shown RD
+, RD
-, WR
+, WR
-, CS
+, CS
-The DS90LV047 device converts LVTTL to the LVDS level standard, as D[7:0] convert D to
+[7:0], D
-[7:0]; The DS90LV048 device converts LVDS to the LVTTL level standard, as: D
+[7:0], D
-[7:0] converts D[7:0 to];
On Target Board 1, the data bus D[7:0 of the LVTTL bus interface 1-1 of digital signal processor] convert LVDS form D to through two DS90LV047 during as output bus
+[7:0], D
-[7:0], data bus D[7:0] receive the LVDS data bus signal that two DS90LV048 come, the address bus A[4:0 of bus interface output during as input bus] and read signal RD, write signal WR, chip selection signal CS convert LVDS form A to through two DS90LV047
+[4:0], A
-[4:0], RD
+, RD
-, WR
+, WR
-, CS
+, CS
-With D
+[7:0], D
-[7:0], A
+[4:0], A
-[4:0], RD
+, RD
-, WR
+, WR
-, CS
+, CS
-Link on the 40 core LVDS bus interface sockets, Target Board 40 core LVDS bus interface sockets are connected through 40 core cables with 40 core LVDS bus interface sockets on the real time debugger plate.
On real time debugger plate 4, the data bus D of LVDS bus interface
+[7:0], D
-[7:0] converts LVTTL level D[7:0 to through two DS90LV048 during as output bus] with the IO[7:0 of EPM7128] link to each other, the data bus D of LVDS bus interface 4-1
+[7:0], D
-[7:0] receives the LVTTL level D[7:0 of two DS90LV047 inputs during as input bus], the address bus A of bus interface 4-1
+[4:0], A
-[4:0] and control signal RD
+, RD
-, WR
+, WR, CS
+, CS
-Convert the A[4:0 of LVTTL level to through two DS90LV048], RD, WR, the IO[12:8 of CS and EPM7128], IO13, IO14, IO15 links to each other, the data address multiplexing line AD[7:0 of P8051] with the IO[23:16 of EPM7128] link to each other, the high eight-bit address wire A[15:8 of P8051] with the IO[31:24 of EPM7128] link to each other, two look-at-me INT1 of P8051, the IO32 of INT0 and EPM7128, IO33 links to each other, the control signal MRD of P8051, MWR, ALE respectively with the IO34 of EPM7128, IO35, IO36 links to each other, the rs 232 serial interface signal TXD of P8051, the TIN of RXD and MAX232, ROUT links to each other, the TOUT of MAX232, RIN links to each other with serial ports of computers.
Claims (2)
1, a kind of real time debugger of digital signal processor is made of Target Board (1), JTEG mouth emulator (2), computing machine (3) three parts, it is characterized in that replacing JTEG mouth emulator (2) with debugger plate (4); Described Target Board (1) comprises the LVTTL bus interface (1-1) of digital signal processor, data bus interface conversion circuit (1-2) during as output bus, data bus interface conversion circuit (1-3) during as input bus, address and control bus interface conversion circuit (1-4), LVDS bus interface (1-5); Described real time debugger plate (4) comprises LVDS bus interface (4-1), data bus interface conversion circuit (4-2) during as output bus, data bus interface conversion circuit (4-3) during as input bus, address and control bus interface conversion circuit (4-4), programmable logic device (PLD) (4-5), single-chip microcomputer (4-6), serial converter spare (4-7).
2, the real time debugger of a kind of digital signal processor according to claim 1, it is characterized in that LVTTL bus interface (1-1) in the Target Board (1) is by interface conversion circuit (1-2), (1-3), (1-4) be connected with LVDS bus interface (1-5), the signal transmission of interface conversion circuit (1-2) from LVTTL bus interface (1-1) to LVDS bus interface (1-5) is unidirectional, the signal transmission of interface conversion circuit (1-3) from LVDS bus interface (1-5) to LVTTL bus interface (1-1) is unidirectional, BDB Bi-directional Data Bus, address have been constituted by interface conversion circuit (1-2) and interface conversion circuit (1-3), the signal transmission of control bus interface conversion circuit (1-4) from LVTTL bus interface (1-1) to LVDS bus interface (1-5) is unidirectional; The signal transmission of interface conversion circuit (4-2) in the debugger plate (4) from LVDS bus interface (4-1) to programmable logic device (PLD) (4-5) is unidirectional, the signal transmission of interface conversion circuit (4-3) from programmable logic device (PLD) (4-5) to LVDS bus interface (4-1) is unidirectional, constituted BDB Bi-directional Data Bus by interface conversion circuit (4-2) and interface conversion circuit (4-3), the address, the signal transmission of control bus interface conversion circuit (4-4) from LVDS bus interface (4-1) to programmable logic device (PLD) (4-5) is unidirectional, is two-way by programmable logic device (PLD) (4-5) to the transmission of single-chip microcomputer (4-6) signal, also is two-way by single-chip microcomputer (4-6) to the transmission of serial converter spare (4-7) signal; With LVDS bus interface (1-5) and two-way connection of LVDS bus interface (4-1), debugger plate (4) and computing machine (3) are by two-way connection of standard serial port change-over circuit (4-7) with 40 core cables for Target Board (1) and debugger plate (4).
3, the real time debugger of a kind of digital signal processor according to claim 2, the LVTTL bus interface (1-1) that it is characterized in that digital signal processor are that the signal of digital signal processor is through outputing to data, address and the control signal on the 20 core sockets behind the field programmable gate array; Target Board (1) is gone up interface conversion circuit (1-2) and is adopted two DS90LV047, interface conversion circuit (1-3) adopts two DS90LV048, address and control bus interface conversion circuit (1-4) adopt two DS90LV047, and LVDS bus interface (1-5) adopts 40 core sockets; Real time debugger plate (4) is gone up LVDS bus interface (4-1) and is adopted 40 core sockets, interface conversion circuit (4-2) adopts two DS90LV048, interface conversion circuit (4-3) adopts two DS90LV047, address and control bus interface conversion circuit (4-4) adopt two DS90LV048, programmable logic device (PLD) (4-5) adopts EPM7128E, single-chip microcomputer (4-6) adopts P8051, and serial converter spare (4-7) adopts MAX232; Computing machine (3) is arbitrary computing machine that has serial ports.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520028139 CN2785038Y (en) | 2005-01-13 | 2005-01-13 | Real time debugger of digital signal processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200520028139 CN2785038Y (en) | 2005-01-13 | 2005-01-13 | Real time debugger of digital signal processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2785038Y true CN2785038Y (en) | 2006-05-31 |
Family
ID=36772005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200520028139 Expired - Fee Related CN2785038Y (en) | 2005-01-13 | 2005-01-13 | Real time debugger of digital signal processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2785038Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105067926A (en) * | 2015-08-11 | 2015-11-18 | 成都思邦力克科技有限公司 | Radar signal processing board test terminal machine |
-
2005
- 2005-01-13 CN CN 200520028139 patent/CN2785038Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105067926A (en) * | 2015-08-11 | 2015-11-18 | 成都思邦力克科技有限公司 | Radar signal processing board test terminal machine |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |