CN2779616Y - Projection-free wafer package - Google Patents

Projection-free wafer package Download PDF

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Publication number
CN2779616Y
CN2779616Y CNU2005200015323U CN200520001532U CN2779616Y CN 2779616 Y CN2779616 Y CN 2779616Y CN U2005200015323 U CNU2005200015323 U CN U2005200015323U CN 200520001532 U CN200520001532 U CN 200520001532U CN 2779616 Y CN2779616 Y CN 2779616Y
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China
Prior art keywords
wafer
bumpless
fuel plate
formula
encapsulation body
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Expired - Lifetime
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CNU2005200015323U
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Chinese (zh)
Inventor
许志行
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Via Technologies Inc
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Via Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The utility model relates to a wafer packaging body without a convex block, which comprises a plate-shaped element, a wafer and an inner connecting line structure, wherein the plate-shaped element has a plurality of electrodes on a first surface, the back side of the wafer is arranged on the first surface of the plate-shaped element, and a plurality of first connecting cushions are arranged on the active surface of the wafer far away from the plate-shaped element. The inner connecting line structure is matched with the first surface of the plate-shaped element and the active surface of the wafer, and the first connecting cushions of the wafer are electrically connected with the electrodes of the inner connecting line structure and the plate-shaped element. In addition, a plurality of second connecting cushions of the wafer are arranged on the active surface of the wafer far away from the plate-shaped element. The wafer is matched with the plate-shaped element having the function of heat dissipation, heat generated by the wafer can be rapidly transferred to the plate-shaped element, and thus favorable efficiency of heat dissipation can be obtained. Favorable electrical effect can be obtained when the plate-shaped element is used as a capacitance element or other kinds of passive elements. The utility model has the advantages of favorable electrical quality and favorable efficiency of heat dissipation.

Description

Bumpless formula wafer encapsulation body
Technical field
The utility model relates to a kind of wafer encapsulation body, particularly relates to a kind of use bumpless formula and increases layer (Bump-less Build-UpLayer, BBUL) the bumpless formula wafer encapsulation body (BUMP-LESSCHIP PACKAGE) of type.
Background technology
Along with electronic technology development with rapid changepl. never-ending changes and improvements, many-sided requirements such as high speed processingization, multifunction, high productive setization (integration), miniaturization and and low priceization for the strengthening electronic element, so wafer (be chip, below all be called wafer) encapsulation technology is also and then towards microminiaturization and densification development.Existing known ball pin trellis array (Ball Grid Array, BGA) encapsulation technology often adopts the carrier (carrier) of base plate for packaging (package substrate) as integrated circuit (IC) wafer (IC chip), and utilize chip bonding (flip chip bonding) or routing joining technique electrical connection technologies such as (wire bonding), wafer is electrically connected to the end face of base plate for packaging, and many soldered balls (solder ball) are disposed at the bottom surface of base plate for packaging in face array (area array) mode.Therefore, wafer is able to a plurality of soldered balls via the internal wiring of base plate for packaging and bottom thereof, and is electrically connected to the electronic installation of next level, for example printed circuit board (PCB) etc.
Yet, because existing known BGA encapsulation technology must be utilized the base plate for packaging of high wiring density (high layoutdensity), and electric connection technology such as collocation chip bonding or routing joint, thereby cause the signal transmission path long.Therefore, developed at present and the wafer package technology that a kind of bumpless formula increases layer (BBUL), it has omitted the processing procedure of chip bonding or routing joint, and directly on wafer, make a multi-layer internal connection line (multi-layered interconnection structure), and with the face array way, on multi-layer internal connection line, make electrical contacts such as soldered ball or stitch, in order to be electrically connected to the electronic installation of next level.
Seeing also shown in Figure 1ly, is the generalized section that existing known bumpless formula increases the layer wafer packaging body.Should existing known bumpless formula increase layer wafer packaging body 100, it comprises a supporting bracket (stiffener) 110, a wafer 120, an internal connection-wire structure 130, a sealing (encapsulant) 140 and a plurality of soldered ball 150, wherein, supporting bracket 110 has an opening (opening) 110a, and wafer 120 is disposed in the opening 110a.In addition, sealing 140 is between the inwall of wafer 120 and opening 110a.Wafer 120 has a plurality of connection pads 122 on its active surface (active surface), and internal connection-wire structure 130 is to be disposed on the active surface of wafer 120, and electrically connects with connection pad 122.
This internal connection-wire structure 130, comprise a plurality of dielectric layers (dielectric layer) 132, a plurality of line layer 134 and a plurality of conductions duct (conductive via) 134a, wherein, these line layers 134 are to be overlapped in regular turn on wafer 120 and the supporting bracket 110, and these line layers 134 is to electrically connect with the connection pad 122 of wafer 120 via conduction duct 134a near wafer.In addition, 132 of these dielectric layers are disposed at respectively between the two adjacent line layers 134, and these conductions duct 134a runs through one of these dielectric layers 132 respectively, and electrically connect two line layers 134 at least.In addition, existing known bumpless formula increases layer wafer packaging body 100 and more comprises a plurality of connection pads 160 and a welding cover layer (solder mask layer) 170, wherein, these connection pads 160 are to be disposed on the internal connection-wire structure 130, and welding cover layer 170 is to be disposed on the internal connection-wire structure 130, and exposes these connection pads 170.Moreover these soldered balls 150 are to be disposed at respectively on these connection pads 170.
From the above, though existing known bumpless formula increases layer wafer packaging body 100 and has better reliability degree and electrical property efficiency, yet along with the increase of wiring density and dwindling of line-spacing (line pitch), the cross-talk of the high-frequency signals that it transmitted (cross talk) phenomenon is also just more and more serious.In other words, the existing known bumpless formula electrical quality that increases layer wafer packaging body 100 also will be affected along with the increase of wiring density and dwindling of line-spacing.
This shows that above-mentioned existing bumpless formula increases the layer wafer packaging body in structure and use, obviously still has inconvenience and defective, and demands urgently further being improved.Increase the problem that the layer wafer packaging body exists in order to solve the bumpless formula, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because above-mentioned existing bumpless formula increases the defective that the layer wafer packaging body exists, the design people is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge thereof, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of bumpless formula wafer encapsulation body of new structure, can improve general existing bumpless formula and increase the layer wafer packaging body, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the utility model that has practical value finally.
Summary of the invention
The purpose of this utility model is, overcome existing bumpless formula and increase the defective that the layer wafer packaging body exists, and provide a kind of bumpless formula wafer encapsulation body of new structure, technical problem to be solved is to make it have preferable electrical quality and preferable radiating efficiency, thereby is suitable for practicality more.
The purpose of this utility model and to solve its technical problem be to adopt following technical scheme to realize.In order to reach aforementioned goal of the invention or other purposes, the utility model proposes a kind of bumpless formula wafer encapsulation body, it comprises a fuel plate, a wafer and an internal connection-wire structure, wherein fuel plate has a plurality of electrodes on the one first surface.Wafer is to be disposed on the first surface of fuel plate with its back side, and wafer has a plurality of first connection pads on its active surface away from fuel plate.Internal connection-wire structure is disposed on the active surface of the first surface of fuel plate and wafer, and these first connection pads of wafer can electrically connect by these electrodes of internal connection-wire structure and fuel plate.In addition, internal connection-wire structure has a plurality of second connection pads on its surface away from wafer.
The utility model compared with prior art has tangible advantage and beneficial effect.By technique scheme, the utility model bumpless formula wafer encapsulation body has following advantage at least: the utility model can be with wafer configuration on the fuel plate with thermolysis, so the heat that wafer is produced can promptly conduct to fuel plate, therefore bumpless formula wafer encapsulation body of the present utility model has preferable radiating efficiency.In addition, when the passive device of fuel plate such as capacity cell or other types, bumpless formula wafer encapsulation body of the present utility model has more preferable electrical property efficiency.In addition, fuel plate more can be another wafer, to form a stacked polycrystalline sheet bumpless formula packaging body.
In sum, the bumpless formula wafer encapsulation body of the utility model special construction, have preferable electrical quality and preferable radiating efficiency, and in like product, do not see have similar structural design to publish or use and really genus innovation, no matter it structurally or bigger improvement all arranged on the function, have large improvement technically, and produced handy and practical effect, and more existing bumpless formula increases the multinomial effect that the layer wafer packaging body has enhancement, thereby be suitable for practicality more, and have the extensive value of industry, really be a novelty, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solutions of the utility model, for can clearer understanding technological means of the present utility model, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present utility model can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is that existing known bumpless formula increases layer generalized section of bumpless formula wafer encapsulation body.
Fig. 2 is the generalized section according to the bumpless formula wafer encapsulation body of the utility model first embodiment.
Fig. 3 is the generalized section according to the bumpless formula wafer encapsulation body of the utility model second embodiment.
100: bumpless formula wafer encapsulation body 110: supporting bracket
110a: opening 120: wafer
122,160: connection pad 130: internal connection-wire structure
132: dielectric layer 134: line layer
134a: conduction duct 140: sealing
150: soldered ball 170: welding cover layer
200: bumpless formula wafer encapsulation body 210: supporting bracket
210a: opening 220: wafer
222,238: connection pad 230: internal connection-wire structure
232a, 232b, 232c: dielectric layer 234a, 234b: line layer
236: conduction duct 240: fuel plate
242: electrode 250: fin
260: electrical contact 270: welding cover layer
280: sealing 300: bumpless formula wafer encapsulation body
310: fuel plate 312: electrode
Embodiment
For further setting forth the utility model is to reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, to according to its embodiment of bumpless formula wafer encapsulation body, structure, feature and the effect thereof that the utility model proposes, describe in detail as after.
[first embodiment]
Seeing also shown in Figure 2ly, is the generalized section according to the bumpless formula wafer encapsulation body of the utility model first embodiment.The bumpless formula wafer encapsulation body 200 of present embodiment, it comprises a supporting bracket 210, a wafer 220, an internal connection-wire structure 230 and a fuel plate 240, wherein:
This supporting bracket 210 has at least one opening 210a, and fuel plate 240 is to be embedded in the opening 210a.In addition, fuel plate 240 has a plurality of electrodes 242 on the one first surface.What deserves to be mentioned is,, between fuel plate 240 and supporting bracket 210, more can insert a sealing 280 in order to make fuel plate 240 can be fixed in the opening 210a.In addition, the material of supporting bracket 210 for example is glass or metal, yet the material of supporting bracket 210 more can be other dielectric materials or electric conducting material.
This wafer 220, its back side are to be disposed on the first surface of fuel plate 240, and wafer 220 has a plurality of connection pads 222 on its surface away from fuel plate 240, for example are on the active surface of wafer 220.In addition, wafer 220 for example is by adhesion coating or the solder layer (not shown) is fixed on the fuel plate 240.In addition, internal connection-wire structure 230 is to be disposed on supporting bracket 210, fuel plate 240 and the wafer 220, and wafer 220 is to electrically connect mutually with the internal wiring of internal connection-wire structure 230, wherein, this internal connection-wire structure 230 for example is that the bumpless formula increases layer (Bumpless Build-UpLayer, BBUL), meaning is that the electric connection between supporting bracket 210 and the wafer 220 is not by existing known chip package projection, but directly passes through the internal wiring of internal connection-wire structure 230.
This internal connection-wire structure 230, it comprises multilayer dielectric layer 232a, 232b and 232c, multilayer line layer 234a and 234b and a plurality of conductions duct 236, and wherein these dielectric layers 232a, 232b and 232c and these line layers 234a and 234b are interconnected on supporting bracket 210 and wafer 220.These conduction ducts 236 are to run through one of these dielectric layers 232a, 232b and 232c respectively in addition, and line layer 234a and 234b are electrically connected to each other via these conduction ducts 236, and these conduction ducts 236 and these line layers 234a and 234b are the internal wirings that constitutes internal connection-wire structure 230.In addition, line layer 234a and 234b are the connection pads 222 that is electrically connected to wafer 220 via these conduction ducts 236.
Please continue to consult shown in Figure 2, this fuel plate 240, for example be tabular active member (panel-shape active component) or tabular passive device (panel-shape passivecomponent), wherein, tabular active member for example is tabular transistor element, and tabular passive device for example is tabular capacity cell, tabular resistive element or tabular inductance element etc.What deserves to be mentioned is that fuel plate 240 more can have active member part and passive device part simultaneously, and becomes integrated fuel plate.In addition and since fuel plate 240 can manufacture of semiconductor or the ceramic post sintering processing procedure made, so the material of fuel plate 240 can be silicon or pottery.
This fuel plate 240 have a plurality of electrodes 242 on its surface near wafer 220, and these electrodes 242 is the connection pads 222 that are electrically connected to wafer 220 by the internal wiring of internal connection-wire structure 230.In addition, internal connection-wire structure 230 has more a plurality of connection pads 222, and it is to be positioned on the surface away from wafer 220 of internal connection-wire structure 230, and these connection pads 238 are to be electrically connected to wafer 220 and fuel plate 240 via the internal wiring of internal connection-wire structure 230.Moreover these connection pads 238 can belong to the conductive layer of same patterning, and its processing procedure is to be same as these line layers 234a and 234b.
What deserves to be mentioned is that do not disposing electrical contact 260 to the situation of connection pad 238, these connection pads 238 can be applied to fill up the signal output-input interface of lattice array (LGA) type.In addition, on these connection pads 238, also can dispose an electrical contact 260 respectively, and the electrical contact 260 of present embodiment is conducting sphere (conductive ball), so that the signal output-input interface of sphere grid array (BGA) type to be provided.In addition, in another embodiment of the present utility model, electrical contact 260 also conducts electricity stitch (conductive pin), and so that the signal output-input interface of pin lattice array (PGA) type to be provided, but such embodiment does not represent with drawing.When these connection pads 238 weld an electrical contact 260 respectively, an also configurable welding cover layer 270 on internal connection-wire structure 230, it exposes these connection pads 238, and the surface lines of protection internal connection-wire structure 230.
Because wafer 220 is to be disposed on the first surface of fuel plate 240, and a second surface of fuel plate 240 is outside being exposed to, so the heat energy that wafer 220 is produced can conduct to fuel plate 240.In other words, compared to prior art, the bumpless formula wafer encapsulation body 200 of present embodiment not only has preferable radiating efficiency, has more preferable electrical property efficiency.Yet, in order further to improve the radiating efficiency of bumpless formula wafer encapsulation body 200, this bumpless formula wafer encapsulation body 200 more comprises a fin (heat spreader) 250, it is configured on the surface away from internal connection-wire structure 230 of supporting bracket 210 and wafer 220, promptly conducts to the surface of fin 250 in order to the high heat that wafer 220 is produced.
What deserves to be mentioned is, when fuel plate 240 is tabular capacity cell, because wafer 220 is to be disposed on the fuel plate 240, therefore bumpless formula wafer encapsulation body 200 has less voltage fluctuation (voltage fluctuation), and can improve the electrical property efficiency of bumpless formula wafer encapsulation body 200.In addition, the bumpless formula wafer encapsulation body 200 of present embodiment is not defined for the single-chip module, and (multi-chip module, MCM), the quantity of fuel plate 240 also is not limited to single simultaneously, also can be a plurality of more to can be used for polycrystalline sheet module.
[second embodiment]
Seeing also shown in Figure 3ly, is the generalized section according to the bumpless formula wafer encapsulation body of the utility model second embodiment.This second embodiment is similar to first embodiment, its difference is: in the bumpless formula wafer encapsulation body 300 of second embodiment, the size of fuel plate 210 is the sizes that are approximately identical to internal connection-wire structure 230, make fuel plate 210 can be considered one and carry the carrier (carrier) of wafer 220 usefulness, and internal connection-wire structure 230 is to be disposed on wafer 220 and the fuel plate 310 at this.In other words, present embodiment there is no the supporting bracket 210 of similar Fig. 2 and the structure of sealing 280.In addition, the electrode 312 of fuel plate 310 also can have the arrangement of different pattern, for example is face array way, concentric annular mode or other modes.
As first embodiment, this fuel plate 310 for example is tabular active member or tabular passive device, wherein, tabular active member for example is tabular transistor element, and tabular passive device for example is tabular capacity cell, tabular resistive element or tabular inductance element etc.In addition, fuel plate 310 more can have active member part and passive device part simultaneously, and becomes integrated fuel plate.
In sum, the utility model with fuel plate as the bumpless formula increase the layer (BBUL) type bumpless formula wafer encapsulation body carrier (or local carrier) and be electrically connected to wafer, when fuel plate had high thermal conductivity coefficient, bumpless formula wafer encapsulation body of the present utility model had preferable radiating efficiency.In addition, when fuel plate is tabular capacity cell, bumpless formula wafer encapsulation body of the present utility model can have less voltage fluctuation and cross-talk phenomenon, thereby have preferable electrical property efficiency.In addition, what the fuel plate of bumpless formula wafer encapsulation body of the present utility model can not take bumpless formula wafer encapsulation body does the surface that electrically connects with the external world, be to be positioned at the another side of bumpless formula wafer encapsulation body and to be adjacent to wafer on the contrary, this helps to reduce the assembling quantity and the occupied area thereof of surface adhesion type (SMT) element, and can shortening and fuel plate and wafer between the signal transmission path, thereby can promote the electrical property efficiency of the integral body of bumpless formula wafer encapsulation body.
The above, it only is preferred embodiment of the present utility model, be not that the utility model is done any pro forma restriction, though the utility model discloses as above with preferred embodiment, yet be not in order to limit the utility model, any those skilled in the art, in the scope that does not break away from technical solutions of the utility model, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solutions of the utility model content, foundation technical spirit of the present utility model is to above any simple modification that embodiment did, equivalent variations and modification all still belong in the scope of technical solutions of the utility model.

Claims (10)

1, a kind of bumpless formula wafer encapsulation body is characterized in that it comprises:
At least one fuel plate has most electrodes on the one first surface;
At least one wafer is disposed on this first surface of this fuel plate, and this wafer has most first connection pads and is disposed on its surface away from this fuel plate; And
One internal connection-wire structure, be disposed on this fuel plate and this wafer, and those first connection pads of this wafer to be those electrodes by this internal connection-wire structure and this fuel plate electrically connect, and this internal connection-wire structure has most second connection pads and is disposed on its surface away from this wafer.
2, bumpless formula wafer encapsulation body according to claim 1 is characterized in that wherein said internal connection-wire structure comprises:
A most dielectric layer;
Those dielectric layers are run through in most conduction ducts respectively; And
Most line layers, wherein those line layers and those dielectric layers are interconnected, and one of those line layers are to conduct electricity one of ducts and be electrically connected to another of those line layers via those.
3, bumpless formula wafer encapsulation body according to claim 1, it is characterized in that it more comprises a supporting bracket, this supporting bracket has an opening, and this fuel plate is to be disposed in this opening, and this internal connection-wire structure is to be disposed on this supporting bracket, this fuel plate and this wafer.
4, bumpless formula wafer encapsulation body according to claim 1 is characterized in that it more comprises most electrical contacts, is disposed on those second connection pads.
5, bumpless formula wafer encapsulation body according to claim 1 is characterized in that it more comprises a fin, is disposed on the second surface away from this wafer of this fuel plate.
6, bumpless formula wafer encapsulation body according to claim 1 is characterized in that it more comprises a welding cover layer, is disposed on this internal connection-wire structure, and exposes those second connection pads.
7, bumpless formula wafer encapsulation body according to claim 1 is characterized in that wherein said fuel plate is to be tabular active member.
8, bumpless formula wafer encapsulation body according to claim 1 is characterized in that wherein said fuel plate is to be tabular passive device.
9, bumpless formula wafer encapsulation body according to claim 1 is characterized in that wherein said fuel plate has active member part and passive device part.
10, bumpless formula wafer encapsulation body according to claim 1 is characterized in that the material of wherein said fuel plate comprises silicon or pottery.
CNU2005200015323U 2005-01-25 2005-01-25 Projection-free wafer package Expired - Lifetime CN2779616Y (en)

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