CN2770095Y - 可降低电磁干扰的封装晶片 - Google Patents

可降低电磁干扰的封装晶片 Download PDF

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CN2770095Y
CN2770095Y CN 200520028278 CN200520028278U CN2770095Y CN 2770095 Y CN2770095 Y CN 2770095Y CN 200520028278 CN200520028278 CN 200520028278 CN 200520028278 U CN200520028278 U CN 200520028278U CN 2770095 Y CN2770095 Y CN 2770095Y
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conductor layer
electromagnetic interference
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资重兴
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Liang Xiwei
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资重兴
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Abstract

本实用新型公开了一种可降低电磁干扰的封装晶片，其包括有一晶片、复数排列状引脚所构成的导线架，于导线架各引脚一面分别设有外接电凸块，其特征在于，晶片的电讯接点面固设有一导线架，导线架的外接电凸块位于外侧，导线架各引脚以导线分别与晶片构成电性连接，导线架的外接电凸块该面设有一黏着层固设一导体层；该导体层为一板体，在板面对应各引脚外接电凸块部位分别设有通孔，各外接电凸块延伸出导体层的通孔外；晶片的至少一电讯接点与该导体层形成电性连接，即组成可降低电磁干扰的封装晶片，本实用新型由于设有导体层，该导体层可作为接地面或电源面，因此可进一步获得降低电磁波干扰、增进传输速率的效果。

Description

可降低电磁干扰的封装晶片
技术领域
本实用新型涉及一种可降低电磁干扰的封装晶片，特别涉及一种具有接地及屏蔽结构，可降低电气杂讯干扰，并增进传输速率的封装晶片。
背景技术
任何电子产品在运作使用时，均会产生电磁波干扰、杂讯(包括散弹杂讯、闪烁杂讯、突波杂讯、热杂讯、分配杂讯等)及高温等情形，其中大部分杂讯的产生是源于电磁波干扰的情况，因而影响电子系统的稳定性；但是，电磁波干扰并不能完全克服，是必须透过电子元件适当的电路规划或屏蔽、接地等结构设计，使电磁波干扰降低至标准数值之下，以达成电磁相容设计的目的。然而，上述习知的封装晶片，通常是于一晶垫上置设有一晶片，于该晶片两侧设有可对外导通电性的导线架，其中该导线架是为复数引脚排列构成，在晶片的接点及导线架的复数引脚间设有金线连接，并于晶片外部设有一绝缘性的封胶体，藉此保护晶片、金线等内部元件，同时达成固定作用。但是，上述习知的晶片封装，并无防止电磁波干扰的结构设计，因此在降低电磁波干扰的目的下，即难以符合现今电子产品的电磁相容的高标准要求。
实用新型内容
本实用新型的目的是要解决上述晶片封装结构存在的易受电磁波干扰的问题，而提供一种可克服上述缺点的可降低电磁干扰的封装晶片。
本实用新型包括有一晶片、复数排列状引脚所构成的导线架，于导线架各引脚一面分别设有外接电凸块，其特征在于，晶片的电讯接点面固设有一导线架，导线架的外接电凸块位于外侧，导线架各引脚以导线分别与晶片构成电性连接，导线架的外接电凸块该面设有一黏着层固设一导体层；该导体层为一板体，在板面对应各引脚外接电凸块部位分别设有通孔，各外接电凸块延伸出导体层的通孔外；晶片的至少一电讯接点与该导体层形成电性连接，即组成可降低电磁干扰的封装晶片。
所述的晶片的电讯接点与导体层形成电性连接的方式是以一导电物构成电性连接，导体层可作为接地面或电源面。
所述的导体层的通孔可为复数相互对齐排列状或相互交错位置排列状。
所述的导体层可在对应晶片的电讯接点部位设有一镂空部，该镂空部设有封胶体。
所述的外接电凸块可为球形导体或锥形导体或其它足以导电的结构形态。
本实用新型由于设有导体层，该导体层可作为接地面或电源面，因此可进一步获得降低电磁波干扰、增进传输速率的效果。
附图说明
图1为本实用新型封装状态的剖视示意图。
图2为本实用新型导体层设有镂空部的封装状态剖视示意图。
图3为本实用新型局部构件的立体分解示意图。
图4为本实用新型二排引脚封装状态示意图。
图5为本实用新型四排引脚封装状态示意图。
图6为本实用新型外接电凸块及导体层的通孔形成交错位置排列状的封装状态示意图
图7为本实用新型外接电凸块的另一实施例示意图一。
图8为本实用新型外接电凸块的另一实施例示意图二。
具体实施方式
请参阅图1、图2、图3所示，本实用新型之实施例包括有一晶片1、一导线架2、复数导线3、一黏着层4及一导体层5，其中，如图1所示，晶片1是习知半导体材料制成的电子元件，在选定面设有复数电讯接点11；
导线架2为金属材料冲压呈二排平行如图4所示，或四排矩阵阵列如图5所示的复数引脚21所构成，在各引脚21底面选定处分别设有一外接电凸块22如图1所示，可令各外接电凸块22形成对齐排列状态；
导线3是使该晶片1的电讯接点11可与导线架2各引脚21形成电性连接的金属导体，例如金线等；
黏着层4可为一种液态干燥后形成黏固的物质如胶水等，或胶带等，并具有绝缘特性；
如图3所示，导体层5可为一片状金属板或金属膜，在板面对应导线架2各引脚21的外接电凸块22部位分别设有通孔51；
藉此，如图1所示，在晶片1的电讯接点11该面固设有一所述的导线架2，使该导线架2的外接电凸块22位于外侧，并令导线架2各引脚21内端以导线3分别与晶片1的电讯接点11连接，而具有外接电凸块22的导线架2该面设有一所述的黏着层4，用该黏着层4黏固一导体层5，恰使各引脚21的外接电凸块22延伸出通孔51外，并令该晶片1至少一电讯接点11与该导体层5形成电性连接，藉此组成导体层5可作为接地面(Groundplane)或电源面(Power piane)的封装晶片，进一步获得电气杂讯隔绝、降低电磁波干扰、增进传输速率等效果。其中，晶片1固设导线架2的方式，是可使用如上述液态干燥后形成黏固物质(如胶水)或胶带等的另一黏着层4’，藉此完成固定功能。
本实用新型是以导体层5所形成之为接地面(Ground plane)或电源面(Power piane)，来实现所述的电气杂讯隔绝、降低电磁波干扰、增进传输速率等效果。另因该导体层5可应用金属板实施完成，其藉以黏着层4黏固于导线架2外侧面状态，恰可密封晶片1电讯接点11部位及导线3，如图1所示，故能同步获得节省封胶材料的封装效果。
其次，如图2、图3、图4所示，导体层5也可选定对应晶片1电讯接点11部位设有一镂空部52，藉此依上述方式依序组装晶片1、导线架2、黏着层4及导体层5构成封装晶片后，再经由导体层5的镂空部52针对晶片1电讯接点11及各引脚21进行连结导线3，并令该晶片1至少一电讯接点11与该导体层5形成电性连接，即可于导体层5的镂空部52处实施一局部封胶体6，将该电讯接点11及导线3等密封，达成保护作用，且能以该导体层5进一步获得电气杂讯隔绝、降低电磁波干扰、增进传输速率等效果。
请参阅图1、图2所示，所述晶片至少一电讯接点11与导体层5形成电性连接的方式是以一导电物7构成电性连接，例如应用一金属导线连结于电讯接点11与导体层5间，即能令导体层5作为接地面(Ground plane)或电源面(Power piane)，以获得前述的效果。
请参阅图6所示，导体层5的复数通孔51是对应各引脚21的外接电凸块22位置而设，因此，各引脚21的外接电凸块22在形成相互交错位置排列状时，该导体层5的复数通孔51也可对应形成相互交错位置排列状，使外接电凸块22可经由各通孔51外露与电路板等其它电子设备作电性连接，以达成防止电性连接时的焊锡溢流导致短路，确保该封装晶片安装应用时的良品率。
另外，前述导线架2各引脚21底面的外接电凸块22，不以引脚21底面一体成型形态为限，请参阅图7、图8所示，也可在各引脚21底面结合有对应导体层5各通孔51的球形导体23如锡球，或锥形导体24，或其它足以导电的各种结构形态，使该球形导体23或锥形导体24延伸出通孔51外，并令晶片1至少一电讯接点11与导体层5形成电性连接，藉此也组成导体层5可作为接地面(Ground plane)或电源面(Power piane)，以获得前述相同的效果。

Claims (5)

1、一种可降低电磁干扰的封装晶片，其包括有一晶片、复数排列状引脚所构成的导线架，于导线架各引脚一面分别设有外接电凸块，其特征在于：晶片的电讯接点面固设有一导线架，导线架的外接电凸块位于外侧，导线架各引脚以导线分别与晶片构成电性连接，导线架的外接电凸块该面设有一黏着层固设一导体层；该导体层为一板体，在板面对应各引脚外接电凸块部位分别设有通孔，各外接电凸块延伸出导体层的通孔外；晶片的至少一电讯接点与该导体层形成电性连接。
2、按照权利要求1所述的一种可降低电磁干扰的封装晶片，其特征在于：所述的晶片的电讯接点与导体层形成电性连接的方式是以一导电物构成电性连接，导体层可作为接地面或电源面。
3、按照权利要求1所述的一种可降低电磁干扰的封装晶片，其特征在于：所述的导体层的通孔为复数相互对齐排列状或相互交错位置排列状。
4、按照权利要求1所述的一种可降低电磁干扰的封装晶片，其特征在于：所述的导体层在对应晶片的电讯接点部位设有一镂空部，该镂空部设有封胶体。
5、按照权利要求1所述的一种可降低电磁干扰的封装晶片，其特征在于：所述的外接电凸块为球形导体或锥形导体。
CN 200520028278 2005-02-18 2005-02-18 可降低电磁干扰的封装晶片 Expired - Fee Related CN2770095Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7782391B2 (en) 2007-08-01 2010-08-24 Hon Hai Precision Industry Co., Ltd. Camera module having a structure for preventing external electronic waves and noise from being introduced into the camera module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7782391B2 (en) 2007-08-01 2010-08-24 Hon Hai Precision Industry Co., Ltd. Camera module having a structure for preventing external electronic waves and noise from being introduced into the camera module
CN101359080B (zh) * 2007-08-01 2011-02-02 鸿富锦精密工业（深圳）有限公司 相机模组

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