CN2762225Y - Interrupt processing device in chip - Google Patents
Interrupt processing device in chip Download PDFInfo
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- CN2762225Y CN2762225Y CN 200420122256 CN200420122256U CN2762225Y CN 2762225 Y CN2762225 Y CN 2762225Y CN 200420122256 CN200420122256 CN 200420122256 CN 200420122256 U CN200420122256 U CN 200420122256U CN 2762225 Y CN2762225 Y CN 2762225Y
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- 238000012545 processing Methods 0.000 title abstract description 4
- 239000013598 vector Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 35
- 238000012216 screening Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000008676 import Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
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Abstract
The utility model discloses an interrupt processing device in chips, which solves the problem that in a plurality of identical priority interrupt simultaneously generated in the prior art, only one priority interrupt is processed. The interrupt processing device in chips comprises an interrupt generating unit, an interrupt screen control unit, an interrupt vector memory unit and a control output unit, wherein a plurality of functional modules are arranged in the interrupt generating unit. The functional modules which can generate interrupt are used for respectively inputting interrupt signals through the interrupt screen control unit into the interrupt vector memory unit and the control output unit. The control output unit sends out an interrupt request signal towards a supervisory computer of a chip. After the supervisory computer of the chip is used for screening the functional modules through the interrupt screen control unit, the interrupt vector memory unit is read. In the process of executing the interrupt, if the functional modules which are screened generate new interrupt, the interrupt is ignored; if the functional modules which are not screened generate the new interrupt, the execution of current interrupt is stopped for executing the new interrupt.
Description
Technical field
The utility model relates to the treating apparatus of interruption, relates in particular to a kind of Interrupt Process device of chip internal.
Background technology
In a chip, may have many interrupt sources, and chip to distribute to the pin of interruption be limited, chip piece has only an interrupt pin usually.
As shown in Figure 1, the Interrupt Process device that is used in the prior art in the chip comprises that one interrupts importation 1, is used to import a plurality of interruptions; An interruptable controller 2 is used for from interrupting importation 1 interruption of selecting a limit priority of output being arranged; And an interrupt handler 3, be used to handle the interruption of on interruptable controller 2, selecting.
In the Interrupt Process device of Fig. 1, when a new interruption is input in the interruption importation 1, the priority of interrupt handled on the priority of interrupt of input newly and the interrupt handler 3 is compared, if the priority of interrupt of new input is not higher than the priority of interrupt of handling on the interrupt handler 3, then continue the current interruption of handling; If the priority of interrupt of new input is higher than the priority of interrupt of handling on the interrupt handler 3, then stop current ongoing interruption, interruption priority is higher by interruptable controller 2 outputs to interrupt handler 3, is handled by interrupt handler 3.
When the priority of interrupt of handling on the priority of interrupt of new generation and the interrupt handler 3 is identical, interruptable controller 2 outputs to interrupt handler 3 according to the sequencing that interrupts producing with interruption, the interruption that produces earlier will at first obtain handling, when handling this interruption, the interruption of other equal priority will be left in the basket, if when the interruption of several equal priority produces simultaneously, can only have an interruption processed, other interruption also will be coughed up suddenly.
In above-mentioned interruption processing method, when the interruption of several equal priority produces simultaneously, can only there be an interruption processed, other interruption will be left in the basket.Some interrupts just can not get handling like this, must handle if the interruption that neglects is a chip, will the function of chip be impacted.
Summary of the invention
The purpose of this utility model is to provide the Interrupt Process device in a kind of chip, when solving underway disconnected processings of prior art, can only have in produced simultaneously a plurality of equal priority interruptions one processed, other the problem that will be left in the basket.
For addressing the above problem, the utility model provides following technical scheme:
Interrupt Process device in a kind of chip comprises:
Interrupt generating unit is used to produce look-at-me;
The interrupt mask control module is used for selectively shielding from the look-at-me of interrupt generating unit output;
The interrupt vector storage unit is used to store the interrupt vector of not conductively-closed;
The control output unit is used for sending interrupt request singal when the interrupt vector of not conductively-closed is deposited in the interrupt vector storage unit;
Have a plurality of functional modules in the interrupt generating unit, the look-at-me of all functions module is input to the interrupt mask control module, and the output terminal of interrupt mask control module is imported interrupt vector storage unit and control output unit respectively.
Described interrupt mask control module by interrupt mask register and some and the door constitute, the corresponding respectively interrupt mask register position of each functional module and one and door, the look-at-me of functional module and pairing interrupt mask register position are the input end with door.
Described interrupt vector storage unit is for reading zero clearing formula register, and each in this register is all corresponding with a functional module in the interrupt generating unit.
Described interrupt vector storage unit is connected with the host computer of chip.
Described control output unit is or door, or the output terminal of door is connected with the host computer of chip.
Because the utility model has adopted above technical scheme, so have following beneficial effect:
Interrupt Process device of the present utility model can be noted produced simultaneously a plurality of interrupt vectors, interrupt service routine by host computer decides which interrupt vector of execution, priority of interrupt judged by interrupt service routine, also can all interrupt vectors are handled by the host computer order.In the time of in commission disconnected,, can select output to more important interruption by setting to the interrupt mask control module.When adopting the utility model to carry out Interrupt Process, the problem that important interruption is left in the basket can not appear.
Description of drawings
Fig. 1 is for being used for the structural representation of the Interrupt Process device in the chip in the prior art;
Fig. 2 is for being divided into chip the synoptic diagram of different stage module;
Fig. 3 is the schematic diagram of Interrupt Process device of the present utility model;
Fig. 4 is the structural representation of Interrupt Process device of the present utility model;
Fig. 5 is the process flow diagram of Interrupt Process of the present utility model.
Embodiment
As shown in Figure 2, in the chip design process, chip can be divided into a lot of one-level modules, each one-level module is made up of some secondary modules again, comprises littler module in the secondary module again.Like this entire chip is divided into a lot of levels.In the utility model, chip can be counted as a module, has a total Interrupt Process device corresponding with it, all corresponding Interrupt Process device of each module in the chip, and each Interrupt Process device all has an interrupt signal output.The look-at-me of each one-level module output is that one-level is interrupted, and with all one-level look-at-me lines or constitute the interruption output pin of total Interrupt Process device together, interrupt request singal is sent to the host computer of chip by interrupting output pin.Each one-level module is made up of many secondary modules, each one-level module all has an one-level Interrupt Process device corresponding with it, interrupt the same with one-level, secondary look-at-me line in each one-level module also all or together constitutes the interruption output pin of one-level Interrupt Process device, this interrupts output pin and is connected with the host computer of chip, its working method is identical with total Interrupt Process device, by that analogy, produces multistage Interrupt Process mode.
The structure of the Interrupt Process device of different stage is identical in the chip, and as shown in Figure 3, Interrupt Process device of the present utility model comprises: an interrupt generating unit is used to produce the look-at-me of a plurality of functional modules of same rank; An interrupt mask control module is used for selectively shielding from the look-at-me of interrupt generating unit output; An interrupt vector storage unit is used to store the interrupt vector of not conductively-closed; A control output unit is used for sending interrupt request singal when the interrupt vector of not conductively-closed is deposited in the interrupt vector storage unit; Have a plurality of functional modules in the interrupt generating unit, the look-at-me of all functions module is input to the interrupt mask control module.
As shown in Figure 4, above-mentioned interrupt mask control module is made up of interrupt mask register and some and door institute, each functional module respectively in the corresponding interrupt mask register and one and.Above-mentioned interrupt vector storage unit is connected with the host computer of chip, and for reading the register of zero clearing formula, each in this interrupt vector register is all corresponding with a functional module in the interrupt generating unit.Above-mentioned control output unit be one or, be connected with the host computer of chip, from the look-at-me line of all functions module of interrupt mask control module output or constituted the interruption output pin of this Interrupt Process device together.Behind the look-at-me input interrupt mask control module of each functional module, carry out and computing with door by one with the interrupt mask register position of correspondence, with the output terminal of door import respectively in the corresponding position of interrupt vector register of this functional module and the control output unit or.
As shown in Figure 5, when the functional module in the interrupt generating unit produces interruption, come the interruption of process chip according to following processes.
In above-mentioned Interrupt Process device, when the functional module in the interrupt generating unit produces interruption, the look-at-me line of functional module is input to high level signal in the interrupt mask control module, with pairing interrupt mask register position by carrying out and computing with door, under non-shielding state, the value of interrupt mask register position is " 1 ", therefore the interrupt mask control module is output as high level, this high level signal imported respectively in the corresponding position of interrupt vector register and the control output unit or door, or the output terminal of door interrupts the host computer that high level signal of output pin output is given chip for interrupting output pin.
The host computer of chip enables interrupt mask register by interrupt service routine after receiving this high level signal, is about to the interrupt mask register zero clearing, masks all interrupt vectors afterwards.The host computer of chip reads interrupt vector register then, when some position of finding interrupt vector register changes, can conclude that is which module produces interruption, because interrupt vector register is the design of reading zero clearing, therefore after running through interrupt vector register, interrupt vector register is zero, has no progeny in reading when executing, interrupt mask register is opened, allowed new interrupt vector to enter in the interrupt vector register.Interrupt service routine can be carried out the interrupt vector that is read in proper order, also can carry out interruption according to the priority that pre-defines.
Interrupt mask register also can selectively shield interrupt vector afterwards under the control of the host computer of chip, when the interruption outbalance of certain module or priority are higher, the host computer of chip is after receiving the high level signal of control module, will interrupt mask register corresponding position set by interrupt service routine with it, other interrupt mask register position reset, the host computer of chip reads interrupt vector register and carries out corresponding the interruption then, in commission in the Duan process, if being the module of " 1 ", above-mentioned interrupt mask register position produces interruption, the then current interruption of carrying out is stopped, interrupt service routine begins to carry out the interruption that this module produces, in executing this, have no progeny, with in the interrupt mask register by reset the position set again, allow new interrupt vector to enter in the interrupt vector register.
The above; it only is the preferable embodiment of the utility model; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement all should be encompassed within the protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of claims.
Claims (5)
1, the Interrupt Process device in a kind of chip is characterized in that comprising:
Interrupt generating unit is used to produce look-at-me;
The interrupt mask control module is used for selectively shielding from the look-at-me of interrupt generating unit output;
The interrupt vector storage unit is used to store the interrupt vector of not conductively-closed;
The control output unit is used for sending interrupt request singal when the interrupt vector of not conductively-closed is deposited in the interrupt vector storage unit;
Have a plurality of functional modules in the interrupt generating unit, the look-at-me of all functions module is input to the interrupt mask control module, and the output terminal of interrupt mask control module is imported interrupt vector storage unit and control output unit respectively.
2, Interrupt Process device according to claim 1, it is characterized in that: described interrupt mask control module by interrupt mask register and some and the door constitute, the corresponding respectively interrupt mask register position of each functional module and one and door, the look-at-me of functional module and pairing interrupt mask register position are the input end with door.
3, Interrupt Process device according to claim 1 is characterized in that: described interrupt vector storage unit is for reading zero clearing formula register, and each in this register is all corresponding with a functional module in the interrupt generating unit.
4, Interrupt Process device according to claim 1 is characterized in that: described interrupt vector storage unit is connected with the host computer of chip.
5, Interrupt Process device according to claim 1 is characterized in that: described control output unit is or door, or the output terminal of door is connected with the host computer of chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420122256 CN2762225Y (en) | 2004-12-31 | 2004-12-31 | Interrupt processing device in chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420122256 CN2762225Y (en) | 2004-12-31 | 2004-12-31 | Interrupt processing device in chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2762225Y true CN2762225Y (en) | 2006-03-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420122256 Expired - Lifetime CN2762225Y (en) | 2004-12-31 | 2004-12-31 | Interrupt processing device in chip |
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| Country | Link |
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| CN (1) | CN2762225Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104809024A (en) * | 2014-01-28 | 2015-07-29 | Arm有限公司 | Speculative interrupt signalling |
-
2004
- 2004-12-31 CN CN 200420122256 patent/CN2762225Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104809024A (en) * | 2014-01-28 | 2015-07-29 | Arm有限公司 | Speculative interrupt signalling |
| CN104809024B (en) * | 2014-01-28 | 2019-12-03 | Arm 有限公司 | Speculate interrupt signal |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20041231 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |