CN1432929A - Arbitration structure and method for responding interruption service request in multiple microprocessor system - Google Patents
Arbitration structure and method for responding interruption service request in multiple microprocessor system Download PDFInfo
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- CN1432929A CN1432929A CN 03102642 CN03102642A CN1432929A CN 1432929 A CN1432929 A CN 1432929A CN 03102642 CN03102642 CN 03102642 CN 03102642 A CN03102642 A CN 03102642A CN 1432929 A CN1432929 A CN 1432929A
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Abstract
In the present invention, multiple microprocessor, system has m microprocessors and a chipset connected to the microprocessors via bus. The chipset includes a memory unit and a comparator connected electrically to the memory, and m pieces of work load information for the m microprocessors are stored in the memory with the idle microprocessor corresponding to the highest work load grade .The chipset responds and interruption service request to generate one comparison signal, so that the comparator compares the m pieces of work load information and the microprocessor being not in idle state but in lowest work load grade with process some interruption service request prior.
Description
Technical field
The present invention relates to a kind of arbitration structure and method of response break in service requirement in computer system, refer to especially a kind of in having the Pentium IV Computer Systems Organization of a plurality of microprocessors, arbitration structure and method that the response break in service requires.
Background technology
(Multi-Processors MP) forms the core of Computer Systems Organization, is one of at present main application development trend always with a plurality of microprocessors.
But, because the working load weight between each microprocessor differs, and for making its break in service that offers peripheral unit (interrupt service) can be more efficient, therefore, the various existing work loads that can monitor each microprocessor at any time, decision preferentially makes arbitration structure and the method for certain particular microprocessor (for example, by the lightest microprocessor of working load) processing from the break in service of peripheral unit, promptly one after the other is suggested.
As shown in Figure 1, be to have the arbitration structure exemplary plot that the response break in service requires in the Pentium III system of a plurality of microprocessors in early days.According to shown in Figure 1, it is the Pentium III system that is example to have 4 first to fourth microprocessor P1～P4, these 4 microprocessor P1～P4 are electrically connected on a north bridge (North Bridge) chipset NB1 with one first bus B 1 (it can be a FSB (Front Side Bus) bus), and (it can be one has advanced programmable interrupt control (AdvancedProgrammable Interrupt Control, APIC) bus of function) and is electrically connected mutually with a south bridge (South Bridge) chipset SB1 with one second bus B 2.
This has the bus B 2 of APIC function because these 4 microprocessor P1～P4 can arrange in pairs or groups; to carry out and to finish a break in service and arbitrate (arbitration); therefore; this South Bridge chip group SB1 can respond the look-at-me St from a peripheral unit E usually, has bus B 2 places of APIC function and export a break in service requirement Si to this.Afterwards, require the content of Si according to this break in service and judge by this bus B 2 with APIC function, and require Si to deliver to this 4 microprocessor P1～P4 this break in service for the arbitration of these 4 present working load information of microprocessor P1～P4.
Wherein, this break in service requires the content of Si can comprise following three information at least: (interrupt type (Type), microprocessor numbering (Number), interrupt vector (Vector)) or the like.For example, this interrupt type can be divided at least: fixedly interrupt type (Fixed Interrupt Type) and lowest priority interrupt type (Lowest Priority Interrupt Type).Should be fixedly interrupt type be meant the microprocessor that break in service can be provided, designated in advance and be maintained fixed constant; The lowest priority interrupt type is meant that then the priority order by present handled job task (task) is the microprocessor that belongs to minimum (that is, working load is the lightest at present), responds this break in service requirement Si.
As for this microprocessor vehicle indicator section, be to be used for arranging in pairs or groups this interrupt type usefulness.Promptly, when this interrupt type is set to fixedly interrupt type, this microprocessor vehicle indicator section promptly is set at a certain particular microprocessor numbering that break in service can be provided, and requires Si to deliver to this particular microprocessor place this break in service so that this bus B 2 with APIC function is fixed.
If this interrupt type is set to the lowest priority interrupt type, then this microprocessor vehicle indicator section just can be for setting a plurality of microprocessor numberings, so that this bus B 2 with APIC function can be in the processor that break in service should be a plurality of can be provided, the lightest microprocessor of the arbitration present working load of judgement responds this break in service and requires Si.In addition, relevant with action and belong to general prior art about this interrupt vector part because of its kind with this peripheral unit E, promptly no longer given unnecessary details at this.
About having the arbitration structure that the response break in service requires in the Pentium IV system architecture with a plurality of microprocessors at present now, can consult Fig. 2.Shown in Figure 2, be a kind of standard arbitration structure of handling interrupt service request.
Comparison diagram 1, Fig. 2 can find, have 4 microprocessor P1～P4 equally, just in existing Pentium IV system architecture shown in Figure 2, it only has one first bus B 1 (it is a FSB bus), and this shown in the use figure one do not have the bus B 2 of APIC function.Thus, South Bridge chip group SB2 among Fig. 2, produce from the look-at-me St of peripheral unit E after this break in service requires Si in response, directly output to existing north bridge chipset NB2, carry out being similar to shown in Figure 1 this and having the arbitration arbitration functions of the bus B 2 of APIC function for this existing north bridge chipset NB2.In addition, 4 first to fourth microprocessor P1～P4 of this shown in Fig. 2, this peripheral unit E, this look-at-me St, this break in service require Si and this South Bridge chip group SB2, and all associated component as shown in Figure 1 or signal are no longer given unnecessary details at this.
Furthermore, in this existing north bridge chipset NB2, include a storage device 21 at least, be electrically connected on a selecting arrangement 22 of this storage device 21, and a comparison means 23 that is electrically connected on this selecting arrangement 22.Wherein, existing Pentium IV system architecture shown in Figure 2 is when carrying out an initialization (initialize) action to this storage device 21, be an existing initialization directive I who is produced by an existing basic output/input system B, (please cooperated earlier and consult Fig. 3 A so that the microprocessor number information NO of this 4 microprocessor P1～P4 and working load information PL store an existing database 211 respectively, this database is arranged in this storage device 21) in, and between the stored position of the working load information PL of the number information NO of this microprocessor and this microprocessor, form the storage relation of a correspondence.Certainly, this existing database 211 can be one in this storage device 21 and stores block.
As shown in Figure 3A, the exemplary plot that changes for the data in this existing database 211.Wherein, cooperate shown in Figure 2 should existing basic output/input system B execution being somebody's turn to do before the existing initialization directive I, can store fields for depositing all relevant in this existing database 211 with these 4 microprocessor P1～P4, that its content for example can all be supposed to be in is one irrelevant (don ' t care) state (representing) with d.Should have initialization directive I now in case carry out, should the number information NO of these 4 microprocessor P1～P4 can be deposited in relevant field in this existing database 211 by existing basic output/input system B, so that should learn which microprocessor was electrically connected mutually with it by existing north bridge chipset NB2.With Fig. 3 A is example, and the number information NO of this microprocessor has numbering 0～3, to represent to be electrically connected on these 4 microprocessor P1～P4 of this existing north bridge chipset NB2 respectively.
In addition, no matter the present residing duty of these 4 microprocessor P1～P4 is idle (idle) state (break in service is not provided) actually, or be work (operating) state (break in service can be provided), should all these 4 microprocessor P1～corresponding initialization information on load PL of P4 be set at 0 by existing basic output/input system B, soon (0,0,0,0) deposits the relevant field in this existing database 211 respectively in.Wherein, the priority level of the job task (task) of working load information representative can be divided into 16 grades such as 0～F, and grade is low more, the working load of microprocessor that expression has this grade job task is light more, and it just can require Si in order to this break in service of priority processing.
In case this existing basic output/input system B finishes aforesaid initialization action to this storage device 21 after, the operating system OS that cooperates this 4 microprocessor P1～P4 work, promptly can be according to the present residing duty of these 4 microprocessor P1～P4 (for the idle state of break in service is not provided, or for the duty of break in service can be provided), and notify this existing north bridge chipset NB2 for this processor P 1 that break in service can be provided, the priority level of its handled job procedure (task) is set in this existing database 211.Promptly, if if the priority level of the present handled job task of this microprocessor P1, OS changes to 3 by this operating system, then this microprocessor P1 promptly can notify this existing north bridge chipset NB2 to write the relevant position that is set to this existing database 211 with 3, thus, the working load information PL of these 4 microprocessor P1～P4 promptly changes into: (3,0,0,0).
Certainly, should have the signal variation that north bridge chipset NB2 promptly can monitor this first bus B 1 at set intervals now, in case arbitrary microprocessor that break in service can be provided among these 4 microprocessor P1～P4 is when switching different work task (task), changed the priority order of job task simultaneously, should existing north bridge chipset NB2 promptly can cooperate this operating system OS and, be re-set in this existing database 211 priority order of new job task.
About Fig. 3 B, cooperate the work exemplary plot of this existing database 211 with this comparison means 23 for this selecting arrangement 22 among this existing north bridge chipset NB2.Wherein, should existing north bridge chipset NB2 receive this break in service when requiring Si when shown in Figure 2, its content that can require Si according to this break in service (for example, adopt the lowest priority interrupt type), and produce many group selections signal V1～Vm to these selecting arrangement 22 places, so that the number information NO of selected microprocessor and working load information PL export in this comparison means 23.For example, this existing database 211 among Fig. 3 B store four groups of microprocessors related data (NO, PL), comprise: (0,3), (1,0), (2,0), (3,0), so should promptly need export this selecting arrangement 22 of two group selection signals by existing north bridge chipset NB2.Certainly, should also can require Si to produce a comparison signal CMP by existing north bridge chipset NB2 according to this break in service to these comparison means 23 places, so that this comparison means 23 compares the size of the working load information PL between selected microprocessor, and produce the number information Sn that output has the particular microprocessor of lowest workload information.
Work as and to find from aforementioned explanation about Fig. 3 B, this selecting arrangement 22 is set in this existing north bridge chipset NB2, though the mechanism and processing elasticity of working load between this microprocessor of balance P2～P4 are provided, so because of being generally used for handling high speed signal by existing north bridge chipset NB2, therefore, the existence of this selecting arrangement 22, the burden in the time of will certainly increasing this existing north bridge chipset NB2 computing, and then cause the signal delay phenomenon.
On the other hand, no matter because of according to the present residing duty of aforementioned these 4 microprocessor P1～P4 be idle (idle) state (break in service is not provided) actually, or be work (operating) state (break in service can be provided), when original state, should all these 4 microprocessor P1～corresponding initialization information on load PL of P4 institute be set by existing basic output/input system B: (0,0,0,0), and after entering this operating system OS, this working load information PL is set at by this existing north bridge chipset NB2 again: (3,0,0,0), so in case carry out work according to the structure shown in this existing north bridge chipset NB2, following break in service mistake will inevitably appear: promptly, be in this microprocessor P1 of this duty, the priority level (0) that is higher than this microprocessor P2～P4 that is in this idle state because of its priority level (3), so, for this microprocessor P1 of break in service can be provided, the number information of its microprocessor is never by these comparison means 23 outputs; Again, because of this microprocessor P2～P4 all is in this idle state that break in service is not provided, therefore, this comparison means 23 also can not be exported the number information of this microprocessor P2～P4.In brief, will not have any microprocessor and can be used to respond this break in service requirement Si.
Summary of the invention
Fundamental purpose of the present invention provides a kind ofly in multi-micro processor system, and the component count of facilitating chip group internal circuit to be avoiding the influencing communications time, and still can respond the arbitration structure of break in service requirement.
Another object of the present invention, provide a kind of in multi-micro processor system, to set the referee method that correct initial value responds the break in service requirement.
To achieve these goals, the invention provides the arbitration structure of response break in service requirement in a kind of multi-micro processor system, have a m microprocessor and a chipset that is electrically connected on this m microprocessor with a bus at least; Wherein, this chipset comprises: a storage device, store m working load information, with expression respectively each working load grade of corresponding microprocessor; Wherein, this arbitrary working load information is minimum to the highest any that is total in n the working load grade, and in this m working load information, be in the corresponding working load information of microprocessor of an idle state, be to be initially set high work load grade, and not being in the corresponding working load information of microprocessor of this idle state, is other working load grade that is initially set beyond the high work load grade; An and comparison means, be electrically connected on this storage device, this comparison means can respond a comparison signal, to compare this m working load information, make the particular microprocessor that is not in this idle state in this m microprocessor and has the lowest workload grade, can priority processing one break in service requirement.
According to above-mentioned conception of the present invention, wherein this multi-micro processor system is one to have the Pentium IV system architecture of a plurality of microprocessors.
According to above-mentioned conception of the present invention, wherein this m microprocessor represents to comprise at least 2 microprocessors, and m working load information representation comprises 2 working load information at least.
According to above-mentioned conception of the present invention, wherein this n working load grade represents to comprise at least this minimum and this high work load grade.
According to above-mentioned conception of the present invention, wherein this bus can be a FSB (Front Side Bus) bus.
According to above-mentioned conception of the present invention, wherein this arbitrary working load grade represent an operating system (O.S.) in the same time by each job task (task) of this m microprocessor processes, the priority order of being set respectively.
According to above-mentioned conception of the present invention, wherein should minimumly represent minimum the highest common n the right of priority that arrive respectively to this highest n working load grade altogether.
According to above-mentioned conception of the present invention, wherein this chipset can comprise a north bridge (North Bridge) and south bridge (South Bridge) chipset.
According to above-mentioned conception of the present invention, wherein this storage device and this comparison means all are arranged in this north bridge chipset.
According to above-mentioned conception of the present invention, wherein this South Bridge chip group can respond the look-at-me of a peripheral unit and produces and export this break in service and require to this north bridge chipset.
According to above-mentioned conception of the present invention, wherein this north bridge chipset can respond the priority order that arbitrary microprocessor is changed when switching different work task (task), and cooperate the priority order of will this arbitrary microprocessor handled new job task of this operating system, be re-set in this storage device.
According to above-mentioned conception of the present invention, wherein this north bridge chipset can respond an initialization directive that is produced by a basic input/output (BIOS), will be in the corresponding working load information of microprocessor of this idle state, be initially set this high work load grade, and will not be in the corresponding working load information of microprocessor of this idle state, be initially set other working load grade beyond this high work load grade.
According to above-mentioned conception of the present invention, wherein this storage device also can comprise the number information of m microprocessor, so that this chipset is learnt the quantity with its microprocessor that is electrically connected mutually, and between the storage location of the storage location of the number information of arbitrary microprocessor and arbitrary working load information, form a corresponding relation that stores.
According to above-mentioned conception of the present invention, wherein this comparison means can be exported to this particular microprocessor with corresponding to the number information of this particular microprocessor in this storage device, responds this break in service requirement to impel this particular microprocessor.
The present invention also provides a kind of referee method of response break in service requirement in multi-micro processor system, comprises the following steps: to store in m working load information to one storage device working load grade of a corresponding m microprocessor to learn; Wherein, this arbitrary working load information is minimum to the highest any that is total in n the working load grade; Respond an initialization directive, with with in this m the working load information, be in the corresponding working load information of microprocessor of idle (idle) state, be initially set high work load grade, and will not be in the corresponding working load information of microprocessor of this idle state, be initially set other working load grade beyond the high work load grade; And respond a break in service requirement, and to compare this m working load information, make the particular microprocessor that is not in this idle state in this m microprocessor and has the lowest workload grade, can this break in service requirement of priority processing.
According to above-mentioned conception of the present invention, wherein this multi-micro processor system is one to have the Pentium IV system architecture of a plurality of microprocessors.
According to above-mentioned conception of the present invention, wherein this m microprocessor represents to comprise at least 2 microprocessors, and m working load information representation comprises 2 working load information at least.
According to above-mentioned conception of the present invention, wherein this n working load grade represents to comprise at least this minimum and this high work load grade.
According to above-mentioned conception of the present invention, wherein this arbitrary working load grade represent an operating system (O.S.) in the same time by each job task (task) of this m microprocessor processes, the priority order of being set respectively.
According to the above-mentioned conception of this case, wherein this minimumly represents minimum to the highest common n right of priority respectively to this highest altogether n working load grade.
According to the above-mentioned conception of this case, wherein this storage device can be located in the chipset, and this chipset is electrically connected with this m microprocessor with a bus.
According to the above-mentioned conception of this case, wherein this bus can be a FSB (Front Side Bus) bus.
According to the above-mentioned conception of this case, wherein this chipset can comprise a north bridge (North Bridge) and south bridge (South Bridge) chipset, and this South Bridge chip group can respond the look-at-me of a peripheral unit and produces and export this break in service and require to this north bridge chipset that includes this storage device.
According to above-mentioned conception of the present invention, wherein this north bridge chipset can respond the priority order that arbitrary microprocessor is changed when switching different work task (task), and cooperate the priority order of will this arbitrary microprocessor handled new job task of this operating system, be re-set in this storage device.
According to above-mentioned conception of the present invention, wherein this initialization directive can be produced by a basic input/output (BIOS), so that this north bridge chipset will be in the corresponding working load information of microprocessor of this idle state, be initially set this high work load grade, and will not be in the corresponding working load information of microprocessor of this idle state, be initially set other working load grade beyond this high work load grade.
According to above-mentioned conception of the present invention, wherein this north bridge chipset can comprise that also one is electrically connected on the comparison means of this storage device, in order to respond the comparison signal that this north bridge chipset is produced according to this break in service requirement, to compare this m working load information, make this particular microprocessor, can this break in service requirement of priority processing.
According to above-mentioned conception of the present invention, wherein also comprise the following steps: to store the number information of m microprocessor to this storage device, so that this north bridge chipset is learnt the quantity with its microprocessor that is electrically connected mutually, and between the storage location of the storage location of the number information of arbitrary microprocessor and arbitrary working load information, form a corresponding relation that stores.
According to above-mentioned conception of the present invention, wherein this comparison means can be exported to this particular microprocessor with corresponding to the number information of this particular microprocessor in this storage device, responds this break in service requirement to impel this particular microprocessor.
The invention has the beneficial effects as follows, the present invention is owing to the working load information setting that will be in the microprocessor of idle condition is a maximal value, and make a distinction with the minimum minimum value of working load, so can correctly notify and be in this duty and this minimum microprocessor of working load responds this break in service requirement, with the break in service mistake phenomenon of avoiding being taken place in the aforementioned prior art, and in this north bridge chipset because of not using selecting arrangement of the prior art, reduce the usage quantity of circuit unit and reduced manufacturing cost, and further prevented the generation of signal delay phenomenon.
The invention will be further described below in conjunction with the drawings and specific embodiments.
Description of drawings
Fig. 1 has the arbitration structure exemplary plot that the response break in service requires in the Pentium III system of a plurality of microprocessors in early days;
Fig. 2 has the arbitration structure exemplary plot that the response break in service requires in the Pentium IV system of a plurality of microprocessors at present;
Fig. 3 A is that the data in the existing database of being located in this storage device changes exemplary plot;
Fig. 3 B is the work exemplary plot that this selecting arrangement cooperates this existing database shown in Fig. 3 A among Fig. 2 with this comparison means;
Fig. 4 is of the present invention one preferable enforcement topology example figure;
Fig. 5 A is that the interior data of database that the present invention is located in this storage device changes exemplary plot; Fig. 5 B is the work exemplary plot that this comparison means cooperates this database shown in Fig. 5 A among the present invention; Fig. 6 is the flow example figure of a preferable implementation method of the present invention.Each label declaration that is comprised in the accompanying drawing of the present invention is as follows: Fig. 1:
First to fourth microprocessor P1～P4 peripheral unit E
Look-at-me St break in service requires Si
North bridge chipset NB1 South Bridge chip group SB1
First and second bus B 1, B2 Fig. 2 and Fig. 3 A, Fig. 3 B:
First to fourth microprocessor P1～P4 peripheral unit E
Look-at-me St break in service requires Si
Existing north bridge chipset NB2 South Bridge chip group SB2
Storage device 21 existing databases 211
Selecting arrangement 22 comparison means 23
The existing initialization directive I of existing basic output/input system B
The number information NO of microprocessor
The working load information PL of microprocessor
Many group selections signal V1～Vm operating system OS
Comparison signal CMP
Number information Sn Fig. 4 of particular microprocessor:
First to fourth microprocessor P1～P4 peripheral unit E
Look-at-me St break in service requires Si
First bus B, 1 chipset 30
North bridge chipset NB3 South Bridge chip group SB3
Basic output/input system Bn initialization directive In
The number information Sn of comparison signal CMP particular microprocessor
Fig. 5～Fig. 6:
First to fourth microprocessor P1～P4
Break in service requires Si
Initialization directive In operating system OS
The number information NO of microprocessor
The working load information PL of microprocessor
Embodiment
As shown in Figure 4, be of the present invention one preferable enforcement topology example figure; In Fig. 4, be included among the north bridge chipset NB3 in the chipset 30 comparison means 32 that includes a storage device 31 and be electrically connected on this storage device 31; In addition, 4 first to fourth microprocessor P1～P4, peripheral unit E, look-at-me St, break in service require Si and are included in South Bridge chip group SB3 in the chipset 30, and all associated component as shown in Figure 2 or signal are also no longer given unnecessary details at this.
Fig. 4 of the present invention is with the difference of existing structure shown in Figure 2: new north bridge chipset NB3 is provided, and a basic output/input system Bn that can carry out new initialization directive In.Furthermore, Pentium IV system architecture shown in the present, when this storage device 31 being carried out a new initialization action, be to export substantially/this initialization directive In that input system Bn produced by this, (please be cooperated and consult Fig. 5 A so that the microprocessor number information NO of this 4 microprocessor P1～P4 and working load information PL are stored in a database 311 respectively, it is set in this storage device 31) in, and between the stored position of the working load information PL of the number information NO of this microprocessor and this microprocessor, form the storage relation of a correspondence.Certainly, this database 311 can be one in this storage device 31 and stores block.
Shown in Fig. 5 A, be that the data in this database 311 changes exemplary plot.Wherein, cooperate shown in Figure 4 should carrying out before this beginning instruction In by basic output/input system Bn, can store fields for depositing all relevant in this database 311 with these 4 microprocessor P1～P4, its content for example can all suppose to be in one to have nothing to do (don ' t care) state (representing) with d.Should be in case carry out from the beginning of changing instruction In, should the number information NO of these 4 microprocessor P1～P4 can be deposited in relevant field in this database 311 by basic output/input system Bn, so that this north bridge chipset NB3 has learnt which microprocessor is electrically connected mutually with it.With Fig. 5 A is example, and the number information NO of this microprocessor has numbering 0～3, to represent to be electrically connected on these 4 microprocessor P1～P4 of this north bridge chipset NB3 respectively.
In addition, according to the present residing duty of these 4 microprocessor P1～P4 is idle (idle) state (break in service is not provided) actually, or be work (operating) state (break in service can be provided), should can give different initial values at the residing different operating state of these 4 microprocessor P1～P4 by basic output/input system Bn, if this microprocessor P1, P2 all is in this duty that break in service can be provided, and this microprocessor P3, when P4 then is in this idle state that break in service is not provided, respectively beginning working load information PL at the beginning of these 4 microprocessor P1～P4 institute is corresponding is set at (0,0, F, F).Wherein, the priority level of the job task (task) of working load information representative can be divided into 16 grades such as 0～F, and grade is low more, the working load of microprocessor that expression has this grade job task is light more, and it just can require Si in order to this break in service of priority processing.
In case this export substantially/input system Bn finishes to this storage device 31 after the aforesaid initialization action, an operating system OS who cooperates this 4 microprocessor P1～P4 work, can be according to the present residing duty of these 4 microprocessor P1～P4 (for this idle state of break in service be provided, or for this duty of break in service can be provided), and notify this north bridge chipset NB3 for this processor P 1, P2 that break in service can be provided, the priority level of its handled job procedure (task) is set in this database 311.Promptly, if if the priority level of the present handled job task of this microprocessor P1 is assumed to be 5, and the priority level of the present handled job task of this microprocessor P2 is assumed to be 2, promptly notify this north bridge chipset NB3 by this operating system OS, to write the relevant position that is set to this database 311 respectively with 5,2, thus, the working load information PL of these 4 microprocessor P1～P4 promptly changes into: (5,2, F, F).
Certainly, the signal that this north bridge chipset NB3 promptly can monitor this first bus B 1 at set intervals changes, in case arbitrary microprocessor that break in service can be provided among these 4 microprocessor P1～P4 is when switching different work task (task), changed the priority order of job task simultaneously, this north bridge chipset NB3 promptly can cooperate this operating system OS and with the priority order of new job task, be re-set in this database 311.
About Fig. 5 B, be the work exemplary plot of these comparison means 32 these databases 311 of cooperation among this north bridge chipset NB3.Wherein, because of this north bridge chipset NB3 shown in the present does not use this selecting arrangement 22 shown in Fig. 2, so when this north bridge chipset NB3 shown in Figure 4 receives this break in service when requiring Si, its content that can require Si according to this break in service (for example, adopt the lowest priority interrupt type), and the number information NO of all these 4 microprocessor P1～P4 and working load information PL are all directly exported in this comparison means 32 earlier.For example, this database 311 among Fig. 5 B all stores the related data (NO of four groups of microprocessors, PL), comprise: (0,5), (1,2), (2, F), (3, F), so this north bridge chipset NB3 directly this break in service of response requires Si and produces a comparison signal CMP, and exported to this comparison means 32 places, so that this comparison means 32 compares the size of the working load information PL between these 4 microprocessor P1～P4, and produce the number information Sn that output has this particular microprocessor of lowest workload information.In brief, with this preferred embodiment is example, can correctly notify and be in this duty and minimum this microprocessor P2 of working load and respond this break in service and require Si, with the break in service mistake phenomenon of avoiding being taken place in the aforementioned prior art, and this north bridge chipset NB3 reduces manufacturing cost because of the usage quantity that reduces circuit unit, and further prevents the generation of signal delay phenomenon.
In addition, now reintroduce of the present invention one preferable implementation method, cooperate the preferable enforcement structure shown in Fig. 4 and Fig. 5 A, Fig. 5 B, see also preferable implementation step shown in Figure 6:
Step 61: beginning;
Step 62: the number information NO that stores 4 microprocessor P1～P4 is to this storage device 31;
Step 63: the working load information PL that stores these 4 microprocessor P1～P4 is to this storage device 31; Wherein, between the storage location of the storage location of the number information of arbitrary microprocessor and arbitrary working load information, form one and correspondingly store relation, and this arbitrary working load information is minimum (0)～the highest (F) any in totally 16 working load grades;
Step 64: respond this initialization directive In, with with among this working load information PL, be in the corresponding working load information of microprocessor of this idle state, be initially set high work load grade (F), and will not be in the corresponding working load information of microprocessor of this idle state, be initially set high work load grade (F) other working load grade in addition; And
Step 65: respond this break in service requirement Si, to compare this working load information PL, make the particular microprocessor that is not in this idle state and has the lowest workload grade among these 4 microprocessor P1～P4, can this break in service of priority processing require Si;
Step 66: finish.
In sum, this case can reduce cost and avoid making the signal transmission of the north bridge chipset that is applied to high velocity environment to take place under the situation of delay, with correct initial value a plurality of microprocessors can be chosen by arbitration correctly, make specific microprocessor energy real-time response break in service requirement.
Claims (22)
1, the arbitration structure that the response break in service requires in a kind of multi-micro processor system has a m microprocessor and a chipset that is electrically connected on this m microprocessor with a bus at least; It is characterized in that this chipset comprises:
One storage device stores m working load information, to represent the working load grade of corresponding microprocessor respectively; Wherein, this arbitrary working load information is for being low to moderate most the highest any that is total in n the working load grade, and in this m working load information, be in the corresponding working load information of microprocessor of an idle state, for being initially set high work load grade, and not being in the corresponding working load information of microprocessor of this idle state, is other working load grade that is initially set beyond the high work load grade; And
One comparison means, be electrically connected on this storage device, this comparison means can respond a comparison signal, to compare this m working load information, make the particular microprocessor that is not in this idle state in this m microprocessor and has the lowest workload grade, can priority processing one break in service requirement.
2, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 1 is characterized in that this bus is a FSB bus.
3, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 1, it is characterized in that, this arbitrary working load grade represent an operating system in the same time by each job task of this m microprocessor processes, the priority order of being set respectively.
4, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 3 is characterized in that, this is low to moderate this highest n working load grade altogether most and represents to be low to moderate most the highest n right of priority altogether respectively.
5, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 4 is characterized in that this chipset comprises a north bridge and South Bridge chip group.
6, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 5 is characterized in that this storage device and this comparison means all are arranged in this north bridge chipset.
7, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 5 is characterized in that, this South Bridge chip group can respond the look-at-me of a peripheral unit and produce and export this break in service and require to this north bridge chipset.
8, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 5, it is characterized in that, this north bridge chipset can respond the priority order that arbitrary microprocessor is changed when switching the different work task, and cooperate the priority order of will this arbitrary microprocessor handled new job task of this operating system, be re-set in this storage device.
9, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 5, it is characterized in that, this north bridge chipset can respond an initialization directive that is produced by a basic input/output, will be in the corresponding working load information of microprocessor of this idle state, be initially set this high work load grade, and will not be in the corresponding working load information of microprocessor of this idle state, be initially set other working load grade beyond this high work load grade.
10, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 1, it is characterized in that, this storage device also can comprise the number information of m microprocessor, so that this chipset is learnt the quantity with its microprocessor that is electrically connected mutually, and between the storage location of the storage location of the number information of arbitrary microprocessor and arbitrary working load information, form a corresponding relation that stores.
11, the arbitration structure that the response break in service requires in the multi-micro processor system as claimed in claim 11, it is characterized in that, this comparison means can will correspond to the number information of the microprocessor of this particular microprocessor in this storage device, export this particular microprocessor to, respond this break in service requirement to impel this particular microprocessor.
12, the referee method that the response break in service requires in a kind of multi-micro processor system is characterized in that, comprises the following steps:
Store in m working load information to one storage device each working load grade of a corresponding m microprocessor to learn; Wherein, this arbitrary working load information is minimum to the highest any that is total in n the working load grade;
Respond an initialization directive, with with in this m the working load information, be in the corresponding working load information of microprocessor of an idle state, be initially set high work load grade, and will not be in the corresponding working load information of microprocessor of this idle state, be initially set other working load grade beyond the high work load grade; And
Respond a break in service requirement,, make the particular microprocessor that is not in this idle state in this m microprocessor and has the lowest workload grade to compare this m working load information, can this break in service requirement of priority processing.
13, the referee method that the response break in service requires in the multi-micro processor system as claimed in claim 12, it is characterized in that, this arbitrary working load grade represent an operating system in the same time by each job task of this m microprocessor processes, the priority order of being set respectively.
14, the referee method that the response break in service requires in the multi-micro processor system as claimed in claim 13 is characterized in that, this is minimum represents minimum the highest n the right of priority that be total to that arrive respectively to this highest n working load grade altogether.
15, the referee method that the response break in service requires in the multi-micro processor system as claimed in claim 14 it is characterized in that this storage device can be located in the chipset, and this chipset is electrically connected with this m microprocessor with a bus.
16, the referee method that the response break in service requires in the multi-micro processor system as claimed in claim 15 is characterized in that this bus is a FSB bus.
17, the referee method that the response break in service requires in the multi-micro processor system as claimed in claim 15, it is characterized in that, this chipset comprises a north bridge and South Bridge chip group, and this South Bridge chip group can respond the look-at-me of a peripheral unit and produce and export this break in service and requires to this north bridge chipset that includes this storage device.
18, the referee method that the response break in service requires in the multi-micro processor system as claimed in claim 17, it is characterized in that, this north bridge chipset can respond the priority order that arbitrary microprocessor is changed when switching the different work task, and cooperate the priority order of will this arbitrary microprocessor handled new job task of this operating system, be re-set in this storage device.
19, the referee method that the response break in service requires in the multi-micro processor system as claimed in claim 17, it is characterized in that, this initialization directive can be produced by a basic input/output, so that this north bridge chipset will be in the corresponding working load information of microprocessor of this idle state, be initially set this high work load grade, and will not be in the corresponding working load information of microprocessor of this idle state, be initially set other working load grade beyond this high work load grade.
20, the referee method that the response break in service requires in the multi-micro processor system as claimed in claim 17, it is characterized in that, this north bridge chipset can comprise that also one is electrically connected on the comparison means of this storage device, in order to respond the comparison signal that this north bridge chipset is produced according to this break in service requirement, to compare this m working load information, make this particular microprocessor, can this break in service requirement of priority processing.
21, the referee method that the response break in service requires in multi-micro processor system as claimed in claim 20 is characterized in that, also comprises the following steps:
The number information that stores m microprocessor is to this storage device, so that this north bridge chipset is learnt the quantity with its microprocessor that is electrically connected mutually, and between the storage location of the storage location of the number information of arbitrary microprocessor and arbitrary working load information, form a corresponding relation that stores.
22, the referee method that the response break in service requires in the multi-micro processor system as claimed in claim 21, it is characterized in that, this comparison means can will correspond to the number information of this particular microprocessor in this storage device, exported to this particular microprocessor, responded this break in service requirement to impel this particular microprocessor.
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| CN 03102642 CN1432929A (en) | 2003-02-14 | 2003-02-14 | Arbitration structure and method for responding interruption service request in multiple microprocessor system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102428451A (en) * | 2009-04-08 | 2012-04-25 | 谷歌公司 | Command and interrupt grouping for a data storage device |
| CN102880143A (en) * | 2012-09-27 | 2013-01-16 | 中国船舶重工集团公司第七一九研究所 | Single control area network (CAN) controller hot-redundant CAN bus system and implementation method thereof |
| US9244842B2 (en) | 2009-04-08 | 2016-01-26 | Google Inc. | Data storage device with copy command |
-
2003
- 2003-02-14 CN CN 03102642 patent/CN1432929A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102428451A (en) * | 2009-04-08 | 2012-04-25 | 谷歌公司 | Command and interrupt grouping for a data storage device |
| CN102428451B (en) * | 2009-04-08 | 2015-01-21 | 谷歌公司 | Command and interrupt grouping for a data storage device |
| US9244842B2 (en) | 2009-04-08 | 2016-01-26 | Google Inc. | Data storage device with copy command |
| CN102880143A (en) * | 2012-09-27 | 2013-01-16 | 中国船舶重工集团公司第七一九研究所 | Single control area network (CAN) controller hot-redundant CAN bus system and implementation method thereof |
| CN102880143B (en) * | 2012-09-27 | 2014-10-22 | 中国船舶重工集团公司第七一九研究所 | Single control area network (CAN) controller hot-redundant CAN bus system and implementation method thereof |
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