CN2711857Y - Test device for embedded memory - Google Patents
Test device for embedded memory Download PDFInfo
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- CN2711857Y CN2711857Y CN 200420002627 CN200420002627U CN2711857Y CN 2711857 Y CN2711857 Y CN 2711857Y CN 200420002627 CN200420002627 CN 200420002627 CN 200420002627 U CN200420002627 U CN 200420002627U CN 2711857 Y CN2711857 Y CN 2711857Y
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- address generator
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- storer
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- 230000015654 memory Effects 0.000 title claims abstract description 184
- 238000012360 testing method Methods 0.000 title claims abstract description 94
- 230000004044 response Effects 0.000 claims abstract description 58
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000009434 installation Methods 0.000 claims description 16
- 230000000052 comparative effect Effects 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000012085 test solution Substances 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005039 memory span Effects 0.000 description 1
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Abstract
The utility model relates to a test device for embedded memory, belonging to the testing field of the memory. The utility model can save the area and power consumption of a chip. The embedded memory test control module of the utility model comprises an address generator, a finite state machine and a vector generator. The address generator corresponds to the memory which is deepest in the N groups of the memory modules. The vector generator corresponds to the memory which is widest in the N groups of the memory modules. When the address generator addressing to the N groups of the memory modules exceeds the depth of the address generator, the address generator sends an inhibit signal to the multi-channel selector switch of the memory module whose depth exceeds the depth of the address generator to forbid the multi-channel selector switch from sending the test vector into the memory of the memory module. Simultaneously the address generator sends the inhibit signal to a response analyzer which corresponds to the memory module whose depth exceeds the depth of the address generator to forbid the response analyzer working.
Description
Technical field
The utility model relates to the field tests of storer, relates in particular to the proving installation of in-line memory.
Background technology
Large-scale, complicated circuit comprises the logical gate that many places are difficult to test usually, even with regard to the best large-scale design of testability, need to expend the substantive test rise time too, take a large amount of ATE (Automated Test Equipment auto testing instrument) storer and the ATE test duration, all these is very expensive, but is again essential for employing ATPG method is tested.In addition, because the blemish type is different from the defect type of general logic, storer level among fairly large design is darker, ATPG (the automatic test vector of Automatic TestPattern Generation produces method) can not provide complete memory test solution usually, and embedded memory test technology (MBIST) then can address these problems.BIST (the embedded self testing circuit of Build In Self Test) can provide a kind of memory test solution under the prerequisite of not sacrificing the detection quality, under many circumstances, the needs that outside test vector generated (and ATE machine memory span) and test application time can thoroughly be eliminated or reduce to greatest extent to the BIST structure.The designer can carry out embedded memory test (MBIST) circuit in certain design inside, and realizes the full speed test easily owing to the contiguous tested storer of embedded memory test (MBIST) circuit.It is one or more defect types of testing memory and special design that embedded memory test (MBIST) adopts one or more algorithms usually, embedded memory test controller circuitry comprises the address generator circuit, finite state machine circuit, vector generator circuit, response analysis device four parts.Referring to Fig. 1, the proving installation of existing in-line memory, the in-line memory testing control module and the N group memory module that comprise receiving chip external terminal commencing signal, every group of memory module comprises multidiameter option switch and storer, the output terminal of multidiameter option switch connects the input end of described storer, and the in-line memory testing control module comprises and corresponding N response analysis device of described N group memory module, a N vector generator, a N address generator and N finite state machine.The finite state machine sending controling instruction is given the multidiameter option switch of described N group memory module, a described finite states machine control N address generator and N vector generator produce address and test vector, and the multidiameter option switch that the address that produces and test vector are sent to described N group memory module, described N response analysis device compared with the output data of N storer respectively according to the corresponding correct response vector of different conditions generation of N finite state machine, and described N response analysis device delivered to embedded memory test top-level module with comparative result.So as can be seen, memory module quantity is many more in the prior art, and the quantity of corresponding address generator, vector generator and finite state machine will be many more, caused a large amount of wastes of chip area and power consumption.
The utility model content
In order to overcome the problems of the prior art and deficiency, the purpose of this utility model has been to provide a kind of proving installation of in-line memory.
The utility model make different in-line memorys can shared same finite state machine, address generator, can save chip area and power consumption.
The utility model make different in-line memorys can shared same finite state machine, address generator and test vector generator, can save chip area and power consumption.
The utility model makes that different in-line memorys can shared same test vector generator, can save chip area and power consumption.
In order to realize the foregoing invention purpose, the technical solution of the utility model realizes as follows:
A kind of proving installation of in-line memory, the in-line memory testing control module and the N group memory module that comprise receiving chip external terminal commencing signal, every group of memory module comprises multidiameter option switch and storer, and the output terminal of described multidiameter option switch connects the input end of described storer.Described in-line memory testing control module comprises and described N group corresponding N response analysis device of memory module and N vector generator.Its design feature is that described in-line memory testing control module comprises an address generator and a finite state machine, and described address generator is to organize the darkest storer corresponding address generator of the degree of depth in the memory module with described N.Described finite state machine sending controling instruction is given the multidiameter option switch of described N group memory module, described finite states machine control address generator and N vector generator produce address and test vector, and address and the test vector that produces sent to the multidiameter option switch that described N organizes memory module.When address generator when addressing surpasses the degree of depth of address generator to described N group memory module, described address generator sends multidiameter option switch that inhibit signal surpasses the memory module of the address generator degree of depth to the degree of depth and forbids that this multidiameter option switch sends into test vector the storer of this memory module, address generator sends inhibit signal to the memory module corresponding response analyzer of the degree of depth above the address generator degree of depth simultaneously, forbids this response analysis device work.Described N response analysis device compared with the output data of N storer respectively according to the corresponding correct response vector of different conditions generation of finite state machine, and described N response analysis device delivered to embedded memory test top-level module with comparative result.
N 〉=2 in the above-mentioned N group memory module.
A kind of proving installation of in-line memory, the in-line memory testing control module and the N group memory module that comprise receiving chip external terminal commencing signal, every group of memory module comprises multidiameter option switch and storer, and the output terminal of described multidiameter option switch connects the input end of described storer.Described in-line memory testing control module comprises and corresponding N response analysis device of described N group memory module.Its design feature is, described in-line memory testing control module comprises an address generator, a finite state machine and a vector generator, described address generator is to organize the darkest storer corresponding address generator of the degree of depth in the memory module with described N, and described vector generator is to organize the wideest corresponding vector generator of storer of bit wide in the memory module with described N.Described finite state machine sending controling instruction is given the multidiameter option switch of described N group memory module, described finite states machine control address generator and vector generator produce address and test vector, and address and the test vector that produces sent to the multidiameter option switch that described N organizes memory module.When address generator when addressing surpasses the degree of depth of address generator to described N group memory module, described address generator sends multidiameter option switch that inhibit signal surpasses the memory module of the address generator degree of depth to the degree of depth and forbids that this multidiameter option switch sends into test vector the storer of this memory module, address generator sends inhibit signal to the memory module corresponding response analyzer of the degree of depth above the address generator degree of depth simultaneously, forbids this response analysis device work.Described N response analysis device compared with the output data of N storer respectively according to the corresponding correct response vector of different conditions generation of finite state machine, and described N response analysis device delivered to embedded memory test top-level module with comparative result.
N 〉=2 in the above-mentioned N group memory module.
A kind of proving installation of in-line memory, the in-line memory testing control module and the N group memory module that comprise receiving chip external terminal commencing signal, every group of memory module comprises multidiameter option switch and storer, and the output terminal of described multidiameter option switch connects the input end of described storer.Described in-line memory testing control module comprises and corresponding N response analysis device of described N group memory module, a N address generator and N finite state machine.Described N finite state machine sending controling instruction given the multidiameter option switch of described N group memory module, described N finite state machine sending controling instruction given the multidiameter option switch of described N group memory module, described N address generator of a described N finite states machine control produces the address, and the address that produces sent to the multidiameter option switch of described N group memory module.Described N response analysis device compared with the output data of N storer respectively according to the corresponding correct response vector of different conditions generation of a described N finite state machine, and described N response analysis device delivered to embedded memory test top-level module with comparative result.Its design feature is, described in-line memory testing control module comprises a vector generator, described vector generator is to organize the wideest corresponding vector generator of storer of bit wide in the memory module with described N, described N finite states machine control vector generator produces test vector, and the test vector that produces sent to the multidiameter option switch of described N group memory module.
N 〉=2 in the above-mentioned N group memory module.
The utility model is for the storer of different depth, with the darkest address generator of the degree of depth as the public address generator, storer for other degree of depth, when the test vector addressing surpasses its degree of depth, produce control signal, forbid that multi-way switch sends test vector into storer, forbid the work of response analysis device simultaneously, prevent that the response analysis device from producing error result.Like this, can shared same address generator and finite state machine for the storer of different depth, saved area of chip and power consumption greatly.
The utility model can be saved as public vector generator with the wideest vector generator of bit wide for the storer of different bit wides.Be used as public vector generator with the wideest vector generator of bit wide, other storer only intercepts the part vector that meets self bit wide in the public vector.Like this, can shared same vector generator for the storer of different bit wides, saved area of chip and power consumption greatly.
The utility model with the darkest address generator of the degree of depth as the public address generator, be used as public vector generator with the wideest vector generator of bit wide, like this, the storer of different depth and bit wide can shared same address generator, finite state machine and a vector generator, has saved area of chip and power consumption greatly.
Description of drawings
Fig. 1 is an embedded memory test circuit block diagram in the prior art;
Fig. 2 is the circuit block diagram of the utility model embodiment 1;
Fig. 3 is the circuit block diagram of the utility model embodiment 2;
Fig. 4 is the circuit block diagram of the utility model embodiment 3.
Below in conjunction with the drawings and specific embodiments the utility model is further specified.
Embodiment
Referring to Fig. 2, a kind of proving installation of in-line memory, the in-line memory testing control module 2 that comprises 2 groups of memory module 1a, 1b and receiving chip external terminal commencing signal, memory module 1a comprises multidiameter option switch 3a and storer 4a, and memory module 1b comprises multidiameter option switch 3b and storer 4b.The degree of depth of storer 1a is greater than the degree of depth of storer 1b.The output terminal of multidiameter option switch 3a connects the input end of described storer 4a.The output terminal of multidiameter option switch 3b connects the input end of described storer 4b.Described in-line memory testing control module 2 comprises and corresponding 2 response analysis device 8a, the 8b of described 2 groups of memory module 1a, 1b and 2 vector generator 7a, 7b.Described in-line memory testing control module 2 comprises an address generator 5 and a finite state machine 6, described address generator 5 is and memory module 1a corresponding address generator, described finite state machine 6 sending controling instructions are given described 2 groups of memory module 1a, the multidiameter option switch 3a of 1b, 3b, described finite state machine 6 control address generators 5 and 2 vector generator 7a, 7b produces address and test vector, and address and the test vector that produces sent to described 2 groups of memory module 1a respectively, 2 multidiameter option switch 3a of 1b, 3b, when generator 5 pairs of described memory module 1b addressing in address surpass the degree of depth of address generator 5, described address generator 5 transmission inhibit signals forbid that to the multidiameter option switch 3b of memory module 1b this multidiameter option switch 3b sends into test vector the storer 4b of this memory module 1b, address generator 5 sends inhibit signal to memory module 1b corresponding response analyzer 8b simultaneously, forbid this response analysis device 8b work, described 2 response analysis device 8a, 8b according to the different conditions of finite state machine 6 produce corresponding correct response vector respectively with 2 storer 4a, the output data of 4b is compared, described 2 response analysis device 8a, 8b delivers to embedded memory test top-level module with comparative result.
Referring to Fig. 3, a kind of proving installation of in-line memory, the in-line memory testing control module 2 that comprises 2 groups of memory module 1a, 1b and receiving chip external terminal commencing signal, memory module 1a comprises multidiameter option switch 3a and storer 4a, and memory module 1b comprises multidiameter option switch 3b and storer 4b.The output terminal of described multidiameter option switch 3a connects the input end of described storer 4a, and the output terminal of described multidiameter option switch 3b connects the input end of described storer 4b.The degree of depth of storer 1a is greater than the degree of depth of storer 1b, and the width of storer 1a is greater than the width of storer 1b.Described in-line memory testing control module 2 comprises and described 2 groups of corresponding N of memory module 1a, 1b response analysis device 8a, 8b.Described in-line memory testing control module 2 comprises an address generator 5, a finite state machine 6 and a vector generator 7, described address generator 5 is a memory module 1a corresponding address generator, described vector generator 7 is the vector generator of memory module 1a correspondence, described finite state machine 6 sending controling instructions are given described 2 groups of memory module 1a, the multidiameter option switch 3a of 1b, 3b, described finite state machine 6 control address generators 5 and vector generator 7 produce address and test vector, and address and the test vector that produces sent to described 2 groups of memory module 1a, the multidiameter option switch 3a of 1b, 3b, when 5 couples of described 2 groups of memory module 1b of address generator addressing surpasses the degree of depth of address generator 5, described address generator 5 transmission inhibit signals forbid that to the multidiameter option switch 3b of memory module 1b this multidiameter option switch 3b sends into test vector the storer 4b of this memory module 1b, address generator 5 sends inhibit signal to response analysis device 8b simultaneously, forbid this response analysis device 8b work, described 2 response analysis device 8a, 8b according to the different conditions of finite state machine 6 produce corresponding correct response vector respectively with 2 storer 4a, the output data of 4b is compared, described 2 response analysis device 8a, 8b delivers to embedded memory test top-level module with comparative result.
Referring to Fig. 4, a kind of proving installation of in-line memory, the in-line memory testing control module 2 that comprises 2 groups of memory module 1a, 1b and receiving chip external terminal commencing signal, memory module 1a comprises multidiameter option switch 3a and storer 4a, and memory module 1b comprises multidiameter option switch 3b and storer 4b.The output terminal of described multidiameter option switch 3a connects the input end of described storer 4a, and the output terminal of described multidiameter option switch 3b connects the input end of described storer 4b.The width of storer 1a is greater than the width of storer 1b.Described in-line memory testing control module 2 comprises and described 2 groups of memory module 1a, 1b corresponding 2 response analysis device 8a, 8b, 2 address generator 5a, 5b and 2 finite state machine 6a, 6b.Described 2 finite state machine 6a, 6b sending controling instruction are given multidiameter option switch 3a, the 3b of described 2 groups of memory module 1a, 1b, and described 2 finite state machine 6a, 6b sending controling instruction are given multidiameter option switch 3a, the 3b of described 2 groups of memory module 1a, 1b.Described 2 finite state machine 6a, 6b control described 2 address generator 5a, 5b and produce the address, and the address that produces is sent to multidiameter option switch 3a, the 3b of described 2 groups of memory module 1a, 1b, described 2 response analysis device 8a, 8b compare with the output data of 2 storer 4a, 4b respectively according to the corresponding correct response vector of different conditions generation of described 2 finite state machine 6a, 6b, and described 2 response analysis device 8a, 8b deliver to embedded memory test top-level module with comparative result.Described in-line memory testing control module 2 comprises a vector generator 7, described vector generator 7 is the vector generator corresponding with memory module 1a, described 2 finite state machine 6a, 6b control vector generator 7 produce test vector, and the test vector that produces are sent to multidiameter option switch 3a, the 3b of described 2 groups of memory module 1a, 1b.
Embedded memory test top-level module is synthetic with each response analysis device comparative result at last, and the place sends by the chip exterior pin.The utility model not only goes for the different memory of the different bit wides of different depth, can also be applicable to the different memory of the different bit wides of same depth, the storer that the perhaps storer of same bit-width different depth, or the degree of depth is all identical with bit wide.
Claims (6)
1. the proving installation of an in-line memory, the in-line memory testing control module (2) and the N group memory module that comprise receiving chip external terminal commencing signal, every group of memory module comprises multidiameter option switch and storer, the output terminal of described multidiameter option switch connects the input end of described storer, described in-line memory testing control module (2) comprises and described N group corresponding N response analysis device of memory module (8) and N vector generator (7), it is characterized in that, described in-line memory testing control module (2) comprises an address generator (5) and a finite state machine (6), described address generator (5) is to organize the darkest storer corresponding address generator of the degree of depth in the memory module with described N, described finite state machine (6) sending controling instruction is given the multidiameter option switch of described N group memory module, described finite state machine (6) control address generator (5) and N vector generator (7) produce address and test vector, and the multidiameter option switch that the address that produces and test vector are sent to described N group memory module, when address generator (5) when addressing surpasses the degree of depth of address generator (5) to described N group memory module, described address generator (5) sends multidiameter option switch that inhibit signal surpasses the memory module of address generator (5) degree of depth to the degree of depth and forbids that this multidiameter option switch sends into test vector the storer of this memory module, address generator (5) sends inhibit signal surpasses address generator (5) degree of depth to the degree of depth memory module corresponding response analyzer (8) simultaneously, forbid this response analysis device (8) work, described N response analysis device (8) compared with the output data of N storer respectively according to the corresponding correct response vector of different conditions generation of finite state machine (6), and described N response analysis device (8) delivered to embedded memory test top-level module with comparative result.
2. according to the proving installation of the described in-line memory of claim 1, it is characterized in that N 〉=2 in the described N group memory module.
3. the proving installation of an in-line memory, the in-line memory testing control module (2) and the N group memory module that comprise receiving chip external terminal commencing signal, every group of memory module comprises multidiameter option switch and storer, the output terminal of described multidiameter option switch connects the input end of described storer, described in-line memory testing control module (2) comprises and described N group corresponding N response analysis device of memory module (8), it is characterized in that, described in-line memory testing control module (2) comprises an address generator (5), a finite state machine (6) and a vector generator (7), described address generator (5) is to organize the darkest storer corresponding address generator of the degree of depth in the memory module with described N, described vector generator (7) is to organize the wideest corresponding vector generator of storer of bit wide in the memory module with described N, described finite state machine (6) sending controling instruction is given the multidiameter option switch of described N group memory module, described finite state machine (6) control address generator (5) and vector generator (7) produce address and test vector, and the multidiameter option switch that the address that produces and test vector are sent to described N group memory module, when address generator (5) when addressing surpasses the degree of depth of address generator (5) to described N group memory module, described address generator (5) sends multidiameter option switch that inhibit signal surpasses the memory module of address generator (5) degree of depth to the degree of depth and forbids that this multidiameter option switch sends into test vector the storer of this memory module, address generator (5) sends inhibit signal surpasses address generator (5) degree of depth to the degree of depth memory module corresponding response analyzer (8) simultaneously, forbid this response analysis device (8) work, described N response analysis device (8) compared with the output data of N storer respectively according to the corresponding correct response vector of different conditions generation of finite state machine (6), and described N response analysis device (8) delivered to embedded memory test top-level module with comparative result.
4. according to the proving installation of the described in-line memory of claim 3, it is characterized in that N 〉=2 in the described N group memory module.
5. the proving installation of an in-line memory, the in-line memory testing control module (2) and the N group memory module that comprise receiving chip external terminal commencing signal, every group of memory module comprises multidiameter option switch and storer, the output terminal of described multidiameter option switch connects the input end of described storer, described in-line memory testing control module (2) comprises and described N group corresponding N response analysis device of memory module (8), N address generator (5) and N finite state machine (6), a described N finite state machine (6) sending controling instruction is given the multidiameter option switch of described N group memory module, a described N finite state machine (6) sending controling instruction is given the multidiameter option switch of described N group memory module, a described N finite state machine (a 6) control described N address generator (5) produces the address, and the address that produces is sent to the multidiameter option switch of described N group memory module, described N response analysis device (8) compared with the output data of N storer respectively according to the corresponding correct response vector of different conditions generation of a described N finite state machine (6), described N response analysis device (8) delivered to embedded memory test top-level module with comparative result, it is characterized in that, described in-line memory testing control module (2) comprises a vector generator (7), described vector generator (7) is to organize the wideest corresponding vector generator of storer of bit wide in the memory module with described N, a described N finite state machine (6) control vector generator (7) produces test vector, and the test vector that produces is sent to the multidiameter option switch of described N group memory module.
6. according to the proving installation of the described in-line memory of claim 5, it is characterized in that N 〉=2 in the described N group memory module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420002627 CN2711857Y (en) | 2004-01-30 | 2004-01-30 | Test device for embedded memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200420002627 CN2711857Y (en) | 2004-01-30 | 2004-01-30 | Test device for embedded memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100356481C (en) * | 2004-01-30 | 2007-12-19 | 北京中星微电子有限公司 | Test device for masiac storage |
| CN101706711B (en) * | 2009-11-26 | 2011-11-02 | 盛科网络（苏州）有限公司 | FIFO memory control circuit and method |
-
2004
- 2004-01-30 CN CN 200420002627 patent/CN2711857Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100356481C (en) * | 2004-01-30 | 2007-12-19 | 北京中星微电子有限公司 | Test device for masiac storage |
| CN101706711B (en) * | 2009-11-26 | 2011-11-02 | 盛科网络（苏州）有限公司 | FIFO memory control circuit and method |
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Granted publication date: 20050720 Termination date: 20120130 |