CN2702310Y - Unit combined type multiple channel supersonic crack detector - Google Patents
Unit combined type multiple channel supersonic crack detector Download PDFInfo
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- CN2702310Y CN2702310Y CN 200420030313 CN200420030313U CN2702310Y CN 2702310 Y CN2702310 Y CN 2702310Y CN 200420030313 CN200420030313 CN 200420030313 CN 200420030313 U CN200420030313 U CN 200420030313U CN 2702310 Y CN2702310 Y CN 2702310Y
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Abstract
The utility model relates to the field of non-destructive inspection defect detection. The unit combined type multiple passage supersonic defect detector is composed of a transmitting unit, a receiving unit, high speed data processing cards, defect detecting computers, the Ethernet, computer main stations, a display, and a defect detecting control system software, wherein, each computer main station can be connected with N defect detecting computers through the Ethernet, while each defect detecting computer can be inserted by three high speed data processing cards, and each high speed data processing card can be connected with 8, 4, 2, and 1 transmitting units and receiving units. The defect detecting passage number of the unit combined type multiple passage supersonic defect detector is one at least and N at most. The utility model has the advantages of unitization, modularity structure design and data storage and calculation, which realizes automatic discrimination, automatic alarm, automatic storage and waveform playback to the defect and enhances the objectivity, the accuracy and the dependability of the supersonic detection.
Description
Technical field
The utility model relates to the Non-Destructive Testing inspection field, particularly a kind of unit-combination type multiple path ultrasonic flaw detector.
Background technology
The hyperchannel defect-detecting equipment all belongs to one-piece construction both at home and abroad at present, and manufacturer carries out specialized designs according to customer requirements, because customer requirements is ever-changing, has the requirement inspection speed high, and many (can reach the 8*N passage at most) of requirement flaw detection passage also arranged.Because robotization flaw detection industry is also just risen, therefore, standardization, normalized work also realize far away.
Summary of the invention
The purpose of this utility model provides a kind of unit-combination type multiple path ultrasonic flaw detector with blocking, modular construction design.
This device is by transmitting element, receiving element, the high-speed data transaction card, the flaw detection computing machine, Ethernet, computing machine master station, promptly detect a flaw computer software and the total station software of computing machine of display and flaw detection control system software formed, wherein each computing machine master station can connect N flaw detection computing machine by Ethernet, in each flaw detection computing machine, can insert three high-speed data transaction cards, each high-speed data transaction card can connect 8,4,2,1 transmitting element and receiving element, the flaw detection port number of unit-combination type multiple path ultrasonic flaw detector is minimum to be 1 passage, is at most 8*N.As shown in Figure 1.
1, transmitting element
The transmitting element circuit is to be connected to form successively by monostable trigger, driver, multi-way switch, programmable gate array CPLD and four driving circuits, and the annexation of each driving circuit is as follows: driver U5A, U5B (U5C, U5D that resistance R 50 (R51, R52, R53) is in parallel with two; U5E, U5F; U3B, U3C) connect, reconnect and draw resistance R 54 (R55, R56, R57), and then be connected with field effect transistor T10 (T11, T12, T13), connect resistance R 58 (R59, R60, R61), capacitor C 6 (C8, C10, C12), capacitor C 7 (C9, C11, C13), resistance R 62 (R63, R64, R65) and diode D31 (D33, D35, D37), D30 (D32, D34, D36), resistance R 66 (R67, R68, R69) again.
Synchronizing signal SYNC0, the SYNC1 that sends from the high-speed data transaction card, the programmable gate array that SYNC2 enters transmitting element, by writing of programmable gate array internal program, output signal A and signal B go to control the break-make of multi-way switch; The synchronizing signal SYNC2 that sends from the high-speed data transaction card enters the transmitting terminal (TAN_TOU1, TAN_TOU2, TAN_TOU3, TAN_TOU4) that the corresponding driving drives is connected to probe by monostable trigger, driver, multi-way switch.Four driving circuits that function is identical are wherein arranged, and the signal after it drives by two drivers are in parallel is through drawing on the resistance R, after entering field effect transistor T amplification, under the high-tension effect of 400V, pass through resistance and diode again, produce the high voltage pulse of excitation ultrasound ripple probe.
This unit can make 8,4,2,1 four kind of passage sending module, major function is the synchronizing signal of high speed processing card, through pulse shaping, driving, by the driving circuit of multi-way switch to appointment, this passage probe is sent broad-adjustable ultrasonic high pressure pulse signal, with 4 passages is example, and schematic diagram as shown in Figure 2.
2, receiving element
The receiving element circuit is to be connected to form successively by 4 driving circuits, multi-way switch, low noise amplifier and programmable gate array CPLD, and each driving circuit is by resistance R 20, R21 (R25, R22; R26, R23; R27, R24) connect diode D11, D13 (D15, D17; D19, D21; D23, D25) and stabilivolt D12, D14 (D16, D18; D20, D22; D24, D26), and connect triode Q1 (Q2, Q3, Q4), again with filter resistance R29 (R30, R31, R32) and capacitor C 12, C13 (C16, C17; C19, C20; C23, C24) connect, be connected on the corresponding pin of multi-way switch. wherein power supply+5V and-5V is by inductance L 1, L2 (L3, L4; L5, L6; L7, L8) be connected to the other end of the collector and emitter resistance R 29 (R30, R31, R32) of triode Q1 (Q2, Q3, Q4).
The echoed signal that each driving circuit receives corresponding probe is connected on diode and the stabilivolt by resistance, and be connected to triode, after connection resistance and electric capacity carry out filtering, be connected on the corresponding pin of multi-way switch, wherein power supply+5V and-5V is connected to the other end of the collector and emitter resistance of triode by two inductance.Synchronizing signal SYNC0, the SYNC1 that sends from the high-speed data transaction card, the programmable gate array that SYNC2 enters transmitting element, by writing of programmable gate array internal program, output signal A and signal B go to control the break-make of multi-way switch.
This unit can make 8,4,2,1 four kind of passage receive mode, and major function is to select novel high-quality amplifier for use, and low hot-tempered sound, high-fidelity are amplified, and the ultrasonic probe echoed signal is amplified to certain level, and its interference free performance is strengthened greatly.Carry out 100 meters with interior wideband transmit in industry spot, should be able to guarantee the integral device performance index.Be example with 4 passages now, schematic diagram as shown in Figure 3.
3, high-speed data transaction card
The high-speed data transaction card is connected to form by two-stage programmable amplifier unit, high-speed data processing unit, computer interface unit three parts, is to be the data processing card of core with the high-speed data processor.Two-stage programmable amplifier unit is made up of first order digital programmable amplifier and second level digital programmable amplifier, detector diode, the high-speed data processing unit is made up of analog to digital converter, first-in first-out buffer, high-speed data processor, and computer interface unit is made up of computer interface and programmable gate array.
High-speed data transaction card major function is to receive the signal of receiving element after the two-stage programmable amplifier amplifies, carry out detection, analog to digital conversion, enter first-in first-out buffer memeory, high speed numerical processor reads these data, isolate useful signal, and the signal that forms by programmable gate array, by the ISA interface data are sent in the flaw detection computing machine again, integrated data is transferred to computing machine master station, and computing machine master station carries out a software task such as integrated data processing such as A sweep, B scanning, C scanning.High-speed data processing unit process flow diagram as shown in Figure 4.Select the high TMS320C5000 family chip of performance price comparison at present for use.
4, the software of two levels (the total station software of computer software and computing machine of promptly detecting a flaw)
They are to be compiled into software by VC++, and the flaw detection computer software is meant the program in embedded system (or industrial computer), and it mainly finishes the collection of integrated data, demonstration in real time, real-time network transmission data.The total station software of computing machine is that the program in the computing machine of computing machine master station is mainly finished real-time network reception data, handles integrated data, formed the flaw detection report.
The utility model has the advantages that: unit-combination type hyperchannel defectoscope adopts blocking, modular construction design, the basic function that not only has the simulation reflectoscope, the characteristic that also has the digitalized ultrasonic defectoscope, can carry out data storage, calculating, and realized the automatic differentiation of defective, automatically report to the police, store automatically and the defective waveform playback, simplified writing task, realized that the file of objective information puts on record, be convenient to scientific management, improved objectivity, accuracy and the reliability of Ultrasonic Detection.
Description of drawings
Fig. 1 is a general structure synoptic diagram of the present utility model.
Fig. 2 is the transmitting element structural drawing.
Fig. 3 is the receiving element structural drawing.
Fig. 4 is a high-speed data transaction card structural drawing.
Fig. 5 is a two-stage amplifying unit schematic diagram able to programme.
Fig. 6 is a high-speed data processing unit schematic diagram.
Fig. 7 is the computer interface unit schematic diagram.
Embodiment
The utility model unit-combination type multiple path ultrasonic flaw detector is realized as follows:
See Fig. 1, this device is by transmitting element, receiving element, the high-speed data transaction card, the flaw detection computing machine, Ethernet, computing machine master station, promptly detect a flaw computer software and the total station software of computing machine of display and flaw detection control system software formed, wherein each computing machine master station can connect N flaw detection computing machine by the two-way Ethernet, its flaw detection computing machine can insert three high-speed data transaction cards at each, each high-speed data processing unit can connect 8,4,2,1 transmitting element and receiving element, the flaw detection port number of unit-combination type multiple path ultrasonic flaw detector is minimum to be 1 passage, is at most N.
The unit-combination type multiple path ultrasonic flaw detector can satisfy most customer requirements.The user that passage is few can only use the single flaw detection system for computer that does not have Ethernet, fireballing user, can reduce transmitting element and receiving element port number, if use single probe flaw detection (being the internal loopback probe), transmitting element and receiving element can be integrated.This system can satisfy 120 meters/minute inspection speeds, and the flaw detection port number can reach 8*N passage.
Fig. 2 is the transmitting element of unit-combination type multiple path ultrasonic flaw detector, be to have realized shaping pulse by monostable trigger, form broad-adjustable pulse simultaneously, drive through the driver paired pulses, two codings that sent by programmable gate array CPLD are opened corresponding multi-way switch, forward the corresponding driving circuit to, form broad-adjustable ultrasound wave high voltage pulse signal, deliver to the transmitting terminal of corresponding probe.
Fig. 3 is the receiving element of unit-combination type multiple path ultrasonic flaw detector.After the probe transmitting terminal receives transponder pulse, promptly to being detected the very strong transmitted wave of object emission, also produce very strong echo simultaneously, after receiving element is finished echo reception, amplitude limit, filtering exactly, two codings that sent by programmable gate array are opened corresponding multi-way switch, the echo of corresponding driving circuit by multi-way switch, is selected for use novel high-quality, low hot-tempered sound, high fidelity amplifier AD8021, be amplified to certain level visiting the object echo.
Fig. 4 is the structural drawing of the high-speed data transaction card of unit-combination type multiple path ultrasonic flaw detector.This card is made up of two-stage programmable amplifier unit, high-speed data processing unit, computer interface unit three parts, is to be the data processing card of core with the high-speed data processor.
Fig. 5 is a two-stage amplifying unit schematic diagram able to programme.Echo after receiving element is handled enters first order digital programmable amplifier, first order digital programmable amplifier is to be controlled through three output terminals after the driver drives by the data line of DSP, can control different decibels (db) successively, after by multi-way switch the echo of differential declines being delivered to lownoiseamplifier, enter second level digital programmable amplifier.Second level digital programmable amplifier is by gain programmable linear amplifier AD8321, serial port control by high-speed data processor, gain margin can change at 0-53db, after signal amplifies through gain, delivering to lownoiseamplifier again amplifies once more, through diode detection, the signal (ADOUT) after amplifier amplifies is delivered to the high-speed data processing unit.
Fig. 6 is a high-speed data processing unit schematic diagram.What this high-speed data processor adopted is (TMS5409) chip of 5000 series.Through two-stage amplifying unit amplifying signal able to programme (ADOUT), enter the input end (AIN) of high-speed AD converter AD9057, it is analog signal conversion 8 digital signal, advance 16 high speed first-in first-out buffers that go out by 8, the digital signal of conversion is delivered to high-speed data processor, high-speed data processor can reach the speed of 100MHz, the storer of high-speed data processor is 16K simultaneously, also has the DMA function, therefore the speed of deal with data is very fast, and the data after high-speed data processor is handled pass to computer interface unit to data fast through the HPI mouth of itself.
The annexation of high-speed data processing unit is: the data line DSP[D15..D0 of high-speed data processor (TMS5409) chip] be connected the data line FIFO[D7..D0 of first-in first-out buffer input data line and high-speed AD converter AD9057 with the output data line of first-in first-out buffer] be connected; Data line DSPD0, DSPD1, the DSPD2 of high-speed data processor (TMS5409) chip are connected to driver 245, and DSP/D0, DSP/D1, the DSP/D2 through driving is connected to the first order programmable amplifier of two-stage amplifying unit able to programme; The second level programmable amplifier that the data line serial port DATEN of high-speed data processor (TMS5409) chip, SDATA, CLK are connected to two-stage amplifying unit able to programme; High-speed data processor (TMS5409) chip /IOSTRB, R/W be connected to the input end of 2/4 code translator, and the output terminal of 2/4 code translator is connected to the sheet choosing end of first-in first-out buffer.The parallel port HPI data line of high-speed data processor (TMS5409) chip is connected on the pin of programmable gate array of computer interface unit.
Fig. 7 is the computer interface unit schematic diagram.The design adopts the ISA interface, realize being connected of high-speed data processor and ISA interface by programmable gate array, by the address that toggle switch is selected and other integrated circuit boards of computing machine do not conflict, finish the communication of computing machine and high-speed data processor, make the flaw detection computing machine receive data in the high-speed data processor internal memory very soon.
The annexation of computer interface unit is: data line DB7..DB0, the address wire A9..A0 of Computer I SA interface, control signal AEN, NIOW, NIOR ,/RESET is connected to programmable gate array, the N9..N3 of toggle switch is connected to programmable gate array, synchronizing signal SYNC0, SYNC1, SYNC2, SYNC3 are connected to transmitting element and receiving element, and other pins of programmable gate array are connected to the parallel port HPI data line of high-speed data processor (TMS5409) chip.
Flaw detection control system software design comprises flaw detection computer software and the total station software of computing machine.Flaw detection computer software and the total station software of computing machine all adopt the VC++ platform, and its friendly interface is simple to operate, can realize demonstration, data management, report generation and printing function to defect echo.
The flaw detection computer software is the program in embedded system (or industrial computer), mainly finishes the decay of the collection of real time data, demonstration in real time, real-time network transmission data, real time altering sampling parameter and change echo.The total station software of computing machine is the program in the computing machine of computing machine master station, mainly finishes real-time network and receives functions such as data, processing integrated data, warning automatically, wave shape playback and file.Automatically report to the police by comparing the amplitude of wave height, when the wave height amplitude surpassed certain altitude, warning function will send warning message automatically automatically; Figure, position, time that file functional module record flaw detection parameter and result of detection, wave shape playback functional module can playback go out flaw echo.
Claims (8)
1, the unit-combination type multiple path ultrasonic flaw detector, it is characterized in that: this device is by transmitting element, receiving element, the high-speed data transaction card, the flaw detection computing machine, Ethernet, computing machine master station, promptly detect a flaw computer software and the total station software of computing machine of display and flaw detection control system software formed, wherein each computing machine master station can connect N flaw detection computing machine by Ethernet, can insert three high-speed data transaction cards at each flaw detection computing machine, each high-speed data transaction card can connect 8,4,2,1 transmitting element and receiving element, the flaw detection port number of unit-combination type multiple path ultrasonic flaw detector is minimum to be 1 passage, is at most N.
2, unit-combination type multiple path ultrasonic flaw detector according to claim 1 is characterized in that: single probe flaw detection, transmitting element and receiving element can be integrated.
3, unit-combination type multiple path ultrasonic flaw detector according to claim 1, it is characterized in that: the transmitting element circuit is to be connected to form successively by monostable trigger, driver, multi-way switch, four driving circuits, and the annexation of each driving circuit is as follows: resistance (R50, R51, R52, R53) and two drivers in parallel (U5A, U5B; U5C, U5D; U5E, U5F; U3B, U3C) connect, reconnect and draw resistance (R54, R55, R56, R57), and then be connected with field effect transistor (T10, T11, T12, T13), connect resistance (R58, R59, R60, R61), electric capacity (C6, C8, C10, C12), electric capacity (C7, C9, C11, C13), resistance (R62, R63, R64, R65) and diode (D31, D33, D35, D37), (D30, D32, D34, D36), resistance (R66, R67, R68, R69) again.
4, unit-combination type multiple path ultrasonic flaw detector according to claim 1 is characterized in that: the receiving element circuit is to be connected to form successively by four driving circuits, multi-way switch, amplifiers.Each driving circuit is by resistance (R20, R21; R25, R22; R26, R23; R27, R24) connection diode (D11, D13; D15, D17; D19, D21; D23, D25) and stabilivolt (D12, D14; D16, D18; D20, D22; D24, D26), and connect triode (Q1, Q2, Q3, Q4), again with filter resistance (R29, R30, R31, R32) and electric capacity (C12, C13; C16, C17; C19, C20; C23, C24) connect, be connected on the corresponding pin of multi-way switch, wherein power supply+5V and-5V is by inductance (L1, L2; L3, L4; L5, L6; L7, L8) be connected to the other end of the collector and emitter resistance (R29, R30, R31, R32) of triode (Q1, Q2, Q3, Q4).
5, unit-combination type multiple path ultrasonic flaw detector according to claim 1, it is characterized in that: the high-speed data transaction card is by two-stage amplifying unit able to programme, the high-speed data processing unit, computer interface unit three parts connect to form, be to be the data processing card of core with the high-speed data processor, two-stage programmable amplifier unit is by first order digital programmable amplifier and second level digital programmable amplifier, detector diode is formed, the high-speed data processing unit is by analog to digital converter, first-in first-out buffer, high-speed data processor is formed, and computer interface unit is made up of computer interface and programmable gate array.
6, unit-combination type multiple path ultrasonic flaw detector according to claim 5, the line connecting relation that it is characterized in that two-stage amplifying unit able to programme is: first order digital programmable amplifier is to be controlled through three output terminals after the driver drives by the data line of DSP, be connected with lownoiseamplifier by multi-way switch, be connected with second level digital programmable Amplifier Gain proframmable linear amplifier AD8321 then, serial port control by high-speed data processor, be connected with lownoiseamplifier again, be connected with detector diode, amplifier more at last.
7, unit-combination type multiple path ultrasonic flaw detector according to claim 5, the annexation that it is characterized in that the high-speed data processing unit is: the data line of high-speed data processor (TMS5409) chip (DSP[D15..D0]) is connected with the output data line of first-in first-out buffer, and the data line of first-in first-out buffer input data line and high-speed AD converter (AD9057) (FIFO[D7..D0]) be connected; The data line (DSPD0, DSPD1, DSPD2) of high-speed data processor (TMS5409) chip is connected to driver, and the data line (DSP/D0, DSP/D1, DSP/D2) through driving is connected to the first order programmable amplifier of two-stage amplifying unit able to programme; The data line serial port (DATEN, SDATA, CLK) of high-speed data processor (TMS5409) chip is connected to the second level programmable amplifier of two-stage amplifying unit able to programme; High-speed data processor (TMS5409) chip /IOSTRB, R/W be connected to the input end of 2/4 code translator, and the output terminal of 2/4 code translator is connected to the sheet choosing end of first-in first-out buffer.The parallel port HPI data line of high-speed data processor (TMS5409) chip is connected on the pin of programmable gate array of computer interface unit.
8, unit-combination type multiple path ultrasonic flaw detector according to claim 5, it is characterized in that: the annexation of computer interface unit is: the data line of Computer I SA interface (DB7..DB0), address wire (A9..A0), control signal (AEN, NIOW, NIOR, / RESET) all be connected to programmable gate array, (N9..N3) of toggle switch is connected to programmable gate array, synchronizing signal (SYNC0, SYNC1, SYNC2, SYNC3) be connected to transmitting element and receiving element, other pins of programmable gate array are connected to the parallel port HPI data line of high-speed data processor (TMS5409) chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200420030313 CN2702310Y (en) | 2004-02-08 | 2004-02-08 | Unit combined type multiple channel supersonic crack detector |
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| CN 200420030313 CN2702310Y (en) | 2004-02-08 | 2004-02-08 | Unit combined type multiple channel supersonic crack detector |
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| CN2702310Y true CN2702310Y (en) | 2005-05-25 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101067618B (en) * | 2007-06-08 | 2010-05-19 | 华中科技大学 | Multichannel ultrasonic collecting device for detecting nonmetal medium |
| CN101789682A (en) * | 2010-02-10 | 2010-07-28 | 福建星网锐捷网络有限公司 | Multiple output power supply time sequence control device and method |
| CN103487511A (en) * | 2013-05-06 | 2014-01-01 | 清华大学 | Dynamic multithread multichannel ultrasonic signal processing apparatus and processing method |
| CN103808796A (en) * | 2012-11-07 | 2014-05-21 | 有研亿金新材料股份有限公司 | Method used for detecting welding quality of welding carried out in intermediate layer connection manner |
| CN111505122A (en) * | 2020-05-26 | 2020-08-07 | 上海市东方海事工程技术有限公司 | Multichannel ultrasonic flaw detection signal processing system and flaw detection vehicle |
| CN111497894A (en) * | 2020-05-26 | 2020-08-07 | 上海市东方海事工程技术有限公司 | Double-rail type high-speed stable ultrasonic flaw detector |
-
2004
- 2004-02-08 CN CN 200420030313 patent/CN2702310Y/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101067618B (en) * | 2007-06-08 | 2010-05-19 | 华中科技大学 | Multichannel ultrasonic collecting device for detecting nonmetal medium |
| CN101789682A (en) * | 2010-02-10 | 2010-07-28 | 福建星网锐捷网络有限公司 | Multiple output power supply time sequence control device and method |
| CN101789682B (en) * | 2010-02-10 | 2012-12-12 | 福建星网锐捷网络有限公司 | Multiple output power supply time sequence control device and method |
| CN103808796A (en) * | 2012-11-07 | 2014-05-21 | 有研亿金新材料股份有限公司 | Method used for detecting welding quality of welding carried out in intermediate layer connection manner |
| CN103808796B (en) * | 2012-11-07 | 2015-11-11 | 有研亿金新材料股份有限公司 | A kind of method detecting the welding quality adopting middle layer connected mode welding |
| CN103487511A (en) * | 2013-05-06 | 2014-01-01 | 清华大学 | Dynamic multithread multichannel ultrasonic signal processing apparatus and processing method |
| CN103487511B (en) * | 2013-05-06 | 2015-10-28 | 清华大学 | Dynamic multi streaming channel ultrasonic signal processing method |
| CN111505122A (en) * | 2020-05-26 | 2020-08-07 | 上海市东方海事工程技术有限公司 | Multichannel ultrasonic flaw detection signal processing system and flaw detection vehicle |
| CN111497894A (en) * | 2020-05-26 | 2020-08-07 | 上海市东方海事工程技术有限公司 | Double-rail type high-speed stable ultrasonic flaw detector |
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